1VERT 2DCL IN[0] 3DCL IN[1] 4DCL OUT[0], GENERIC[0] 5DCL OUT[1], GENERIC[1] 6IMM[0] INT32 {1, 0, 0, 0} 7MOV OUT[0], IN[0] 8UADD OUT[1].x, IN[1].xxxx, IMM[0].xxxx 9END 10