1 /*
2 * Copyright 2017 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
7 #include <errno.h>
8 #include <stdint.h>
9 #include <stdio.h>
10 #include <string.h>
11 #include <sys/mman.h>
12 #include <virtgpu_drm.h>
13 #include <xf86drm.h>
14
15 #include "drv_priv.h"
16 #include "helpers.h"
17 #include "util.h"
18 #include "virgl_hw.h"
19
20 #ifndef PAGE_SIZE
21 #define PAGE_SIZE 0x1000
22 #endif
23 #define PIPE_TEXTURE_2D 2
24
25 #define MESA_LLVMPIPE_TILE_ORDER 6
26 #define MESA_LLVMPIPE_TILE_SIZE (1 << MESA_LLVMPIPE_TILE_ORDER)
27
28 static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
29 DRM_FORMAT_BGR888, DRM_FORMAT_RGB565,
30 DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB8888 };
31
32 static const uint32_t dumb_texture_source_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_YVU420,
33 DRM_FORMAT_YVU420_ANDROID };
34
35 static const uint32_t texture_source_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_RG88 };
36
37 struct virtio_gpu_priv {
38 int has_3d;
39 };
40
translate_format(uint32_t drm_fourcc,uint32_t plane)41 static uint32_t translate_format(uint32_t drm_fourcc, uint32_t plane)
42 {
43 switch (drm_fourcc) {
44 case DRM_FORMAT_XRGB8888:
45 return VIRGL_FORMAT_B8G8R8X8_UNORM;
46 case DRM_FORMAT_ARGB8888:
47 return VIRGL_FORMAT_B8G8R8A8_UNORM;
48 case DRM_FORMAT_XBGR8888:
49 return VIRGL_FORMAT_R8G8B8X8_UNORM;
50 case DRM_FORMAT_ABGR8888:
51 return VIRGL_FORMAT_R8G8B8A8_UNORM;
52 case DRM_FORMAT_RGB565:
53 return VIRGL_FORMAT_B5G6R5_UNORM;
54 case DRM_FORMAT_R8:
55 return VIRGL_FORMAT_R8_UNORM;
56 case DRM_FORMAT_RG88:
57 return VIRGL_FORMAT_R8G8_UNORM;
58 default:
59 return 0;
60 }
61 }
62
virtio_dumb_bo_create(struct bo * bo,uint32_t width,uint32_t height,uint32_t format,uint64_t use_flags)63 static int virtio_dumb_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
64 uint64_t use_flags)
65 {
66 width = ALIGN(width, MESA_LLVMPIPE_TILE_SIZE);
67 height = ALIGN(height, MESA_LLVMPIPE_TILE_SIZE);
68
69 /* HAL_PIXEL_FORMAT_YV12 requires that the buffer's height not be aligned. */
70 if (bo->format == DRM_FORMAT_YVU420_ANDROID)
71 height = bo->height;
72
73 return drv_dumb_bo_create(bo, width, height, format, use_flags);
74 }
75
virtio_virgl_bo_create(struct bo * bo,uint32_t width,uint32_t height,uint32_t format,uint64_t use_flags)76 static int virtio_virgl_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
77 uint64_t use_flags)
78 {
79 int ret;
80 ssize_t plane;
81 ssize_t num_planes = drv_num_planes_from_format(format);
82 uint32_t stride0;
83
84 for (plane = 0; plane < num_planes; plane++) {
85 uint32_t stride = drv_stride_from_format(format, width, plane);
86 uint32_t size = drv_size_from_format(format, stride, height, plane);
87 uint32_t res_format = translate_format(format, plane);
88 struct drm_virtgpu_resource_create res_create;
89
90 memset(&res_create, 0, sizeof(res_create));
91 size = ALIGN(size, PAGE_SIZE);
92 /*
93 * Setting the target is intended to ensure this resource gets bound as a 2D
94 * texture in the host renderer's GL state. All of these resource properties are
95 * sent unchanged by the kernel to the host, which in turn sends them unchanged to
96 * virglrenderer. When virglrenderer makes a resource, it will convert the target
97 * enum to the equivalent one in GL and then bind the resource to that target.
98 */
99 res_create.target = PIPE_TEXTURE_2D;
100 res_create.format = res_format;
101 res_create.bind = VIRGL_BIND_RENDER_TARGET;
102 res_create.width = width;
103 res_create.height = height;
104 res_create.depth = 1;
105 res_create.array_size = 1;
106 res_create.last_level = 0;
107 res_create.nr_samples = 0;
108 res_create.stride = stride;
109 res_create.size = size;
110
111 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_RESOURCE_CREATE, &res_create);
112 if (ret) {
113 drv_log("DRM_IOCTL_VIRTGPU_RESOURCE_CREATE failed with %s\n",
114 strerror(errno));
115 goto fail;
116 }
117
118 bo->handles[plane].u32 = res_create.bo_handle;
119 }
120
121 stride0 = drv_stride_from_format(format, width, 0);
122 drv_bo_from_format(bo, stride0, height, format);
123
124 for (plane = 0; plane < num_planes; plane++)
125 bo->offsets[plane] = 0;
126
127 return 0;
128
129 fail:
130 for (plane--; plane >= 0; plane--) {
131 struct drm_gem_close gem_close;
132 memset(&gem_close, 0, sizeof(gem_close));
133 gem_close.handle = bo->handles[plane].u32;
134 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
135 }
136
137 return ret;
138 }
139
virtio_virgl_bo_map(struct bo * bo,struct vma * vma,size_t plane,uint32_t map_flags)140 static void *virtio_virgl_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
141 {
142 int ret;
143 struct drm_virtgpu_map gem_map;
144
145 memset(&gem_map, 0, sizeof(gem_map));
146 gem_map.handle = bo->handles[0].u32;
147
148 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_MAP, &gem_map);
149 if (ret) {
150 drv_log("DRM_IOCTL_VIRTGPU_MAP failed with %s\n", strerror(errno));
151 return MAP_FAILED;
152 }
153
154 vma->length = bo->total_size;
155 return mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
156 gem_map.offset);
157 }
158
virtio_gpu_init(struct driver * drv)159 static int virtio_gpu_init(struct driver *drv)
160 {
161 int ret;
162 struct virtio_gpu_priv *priv;
163 struct drm_virtgpu_getparam args;
164
165 priv = calloc(1, sizeof(*priv));
166 drv->priv = priv;
167
168 memset(&args, 0, sizeof(args));
169 args.param = VIRTGPU_PARAM_3D_FEATURES;
170 args.value = (uint64_t)(uintptr_t)&priv->has_3d;
171 ret = drmIoctl(drv->fd, DRM_IOCTL_VIRTGPU_GETPARAM, &args);
172 if (ret) {
173 drv_log("virtio 3D acceleration is not available\n");
174 /* Be paranoid */
175 priv->has_3d = 0;
176 }
177
178 drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
179 &LINEAR_METADATA, BO_USE_RENDER_MASK);
180
181 if (priv->has_3d)
182 drv_add_combinations(drv, texture_source_formats,
183 ARRAY_SIZE(texture_source_formats), &LINEAR_METADATA,
184 BO_USE_TEXTURE_MASK);
185 else
186 drv_add_combinations(drv, dumb_texture_source_formats,
187 ARRAY_SIZE(dumb_texture_source_formats), &LINEAR_METADATA,
188 BO_USE_TEXTURE_MASK);
189
190 return drv_modify_linear_combinations(drv);
191 }
192
virtio_gpu_close(struct driver * drv)193 static void virtio_gpu_close(struct driver *drv)
194 {
195 free(drv->priv);
196 drv->priv = NULL;
197 }
198
virtio_gpu_bo_create(struct bo * bo,uint32_t width,uint32_t height,uint32_t format,uint64_t use_flags)199 static int virtio_gpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
200 uint64_t use_flags)
201 {
202 struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)bo->drv->priv;
203 if (priv->has_3d)
204 return virtio_virgl_bo_create(bo, width, height, format, use_flags);
205 else
206 return virtio_dumb_bo_create(bo, width, height, format, use_flags);
207 }
208
virtio_gpu_bo_destroy(struct bo * bo)209 static int virtio_gpu_bo_destroy(struct bo *bo)
210 {
211 struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)bo->drv->priv;
212 if (priv->has_3d)
213 return drv_gem_bo_destroy(bo);
214 else
215 return drv_dumb_bo_destroy(bo);
216 }
217
virtio_gpu_bo_map(struct bo * bo,struct vma * vma,size_t plane,uint32_t map_flags)218 static void *virtio_gpu_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
219 {
220 struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)bo->drv->priv;
221 if (priv->has_3d)
222 return virtio_virgl_bo_map(bo, vma, plane, map_flags);
223 else
224 return drv_dumb_bo_map(bo, vma, plane, map_flags);
225 }
226
virtio_gpu_bo_invalidate(struct bo * bo,struct mapping * mapping)227 static int virtio_gpu_bo_invalidate(struct bo *bo, struct mapping *mapping)
228 {
229 int ret;
230 struct drm_virtgpu_3d_transfer_from_host xfer;
231 struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)bo->drv->priv;
232
233 if (!priv->has_3d)
234 return 0;
235
236 memset(&xfer, 0, sizeof(xfer));
237 xfer.bo_handle = mapping->vma->handle;
238 xfer.box.x = mapping->rect.x;
239 xfer.box.y = mapping->rect.y;
240 xfer.box.w = mapping->rect.width;
241 xfer.box.h = mapping->rect.height;
242 xfer.box.d = 1;
243
244 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST, &xfer);
245 if (ret) {
246 drv_log("DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST failed with %s\n", strerror(errno));
247 return ret;
248 }
249
250 return 0;
251 }
252
virtio_gpu_bo_flush(struct bo * bo,struct mapping * mapping)253 static int virtio_gpu_bo_flush(struct bo *bo, struct mapping *mapping)
254 {
255 int ret;
256 struct drm_virtgpu_3d_transfer_to_host xfer;
257 struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)bo->drv->priv;
258
259 if (!priv->has_3d)
260 return 0;
261
262 if (!(mapping->vma->map_flags & BO_MAP_WRITE))
263 return 0;
264
265 memset(&xfer, 0, sizeof(xfer));
266 xfer.bo_handle = mapping->vma->handle;
267 xfer.box.x = mapping->rect.x;
268 xfer.box.y = mapping->rect.y;
269 xfer.box.w = mapping->rect.width;
270 xfer.box.h = mapping->rect.height;
271 xfer.box.d = 1;
272
273 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST, &xfer);
274 if (ret) {
275 drv_log("DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST failed with %s\n", strerror(errno));
276 return ret;
277 }
278
279 return 0;
280 }
281
virtio_gpu_resolve_format(uint32_t format,uint64_t use_flags)282 static uint32_t virtio_gpu_resolve_format(uint32_t format, uint64_t use_flags)
283 {
284 switch (format) {
285 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
286 /*HACK: See b/28671744 */
287 return DRM_FORMAT_XBGR8888;
288 case DRM_FORMAT_FLEX_YCbCr_420_888:
289 return DRM_FORMAT_YVU420;
290 default:
291 return format;
292 }
293 }
294
295 const struct backend backend_virtio_gpu = {
296 .name = "virtio_gpu",
297 .init = virtio_gpu_init,
298 .close = virtio_gpu_close,
299 .bo_create = virtio_gpu_bo_create,
300 .bo_destroy = virtio_gpu_bo_destroy,
301 .bo_import = drv_prime_bo_import,
302 .bo_map = virtio_gpu_bo_map,
303 .bo_unmap = drv_bo_munmap,
304 .bo_invalidate = virtio_gpu_bo_invalidate,
305 .bo_flush = virtio_gpu_bo_flush,
306 .resolve_format = virtio_gpu_resolve_format,
307 };
308