1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides ARM specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "ARMMCTargetDesc.h"
15 #include "ARMMCAsmInfo.h"
16 #include "ARMBaseInfo.h"
17 #include "InstPrinter/ARMInstPrinter.h"
18 #include "llvm/MC/MCCodeGenInfo.h"
19 #include "llvm/MC/MCInstrAnalysis.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/TargetRegistry.h"
26
27 #define GET_REGINFO_MC_DESC
28 #include "ARMGenRegisterInfo.inc"
29
30 #define GET_INSTRINFO_MC_DESC
31 #include "ARMGenInstrInfo.inc"
32
33 #define GET_SUBTARGETINFO_MC_DESC
34 #include "ARMGenSubtargetInfo.inc"
35
36 using namespace llvm;
37
ParseARMTriple(StringRef TT)38 std::string ARM_MC::ParseARMTriple(StringRef TT) {
39 // Set the boolean corresponding to the current target triple, or the default
40 // if one cannot be determined, to true.
41 unsigned Len = TT.size();
42 unsigned Idx = 0;
43
44 // FIXME: Enhance Triple helper class to extract ARM version.
45 bool isThumb = false;
46 if (Len >= 5 && TT.substr(0, 4) == "armv")
47 Idx = 4;
48 else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
49 isThumb = true;
50 if (Len >= 7 && TT[5] == 'v')
51 Idx = 6;
52 }
53
54 std::string ARMArchFeature;
55 if (Idx) {
56 unsigned SubVer = TT[Idx];
57 if (SubVer >= '7' && SubVer <= '9') {
58 if (Len >= Idx+2 && TT[Idx+1] == 'm') {
59 // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
60 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
61 } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
62 // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
63 // FeatureT2XtPk, FeatureMClass
64 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
65 } else
66 // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
67 ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
68 } else if (SubVer == '6') {
69 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
70 ARMArchFeature = "+v6t2";
71 else if (Len >= Idx+2 && TT[Idx+1] == 'm')
72 // v6m: FeatureNoARM, FeatureMClass
73 ARMArchFeature = "+v6t2,+noarm,+mclass";
74 else
75 ARMArchFeature = "+v6";
76 } else if (SubVer == '5') {
77 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
78 ARMArchFeature = "+v5te";
79 else
80 ARMArchFeature = "+v5t";
81 } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
82 ARMArchFeature = "+v4t";
83 }
84
85 if (isThumb) {
86 if (ARMArchFeature.empty())
87 ARMArchFeature = "+thumb-mode";
88 else
89 ARMArchFeature += ",+thumb-mode";
90 }
91
92 Triple TheTriple(TT);
93 if (TheTriple.getOS() == Triple::NativeClient) {
94 if (ARMArchFeature.empty())
95 ARMArchFeature = "+nacl-mode";
96 else
97 ARMArchFeature += ",+nacl-mode";
98 }
99
100 return ARMArchFeature;
101 }
102
createARMMCSubtargetInfo(StringRef TT,StringRef CPU,StringRef FS)103 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
104 StringRef FS) {
105 std::string ArchFS = ARM_MC::ParseARMTriple(TT);
106 if (!FS.empty()) {
107 if (!ArchFS.empty())
108 ArchFS = ArchFS + "," + FS.str();
109 else
110 ArchFS = FS;
111 }
112
113 MCSubtargetInfo *X = new MCSubtargetInfo();
114 InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
115 return X;
116 }
117
createARMMCInstrInfo()118 static MCInstrInfo *createARMMCInstrInfo() {
119 MCInstrInfo *X = new MCInstrInfo();
120 InitARMMCInstrInfo(X);
121 return X;
122 }
123
createARMMCRegisterInfo(StringRef Triple)124 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
125 MCRegisterInfo *X = new MCRegisterInfo();
126 InitARMMCRegisterInfo(X, ARM::LR);
127 return X;
128 }
129
createARMMCAsmInfo(const Target & T,StringRef TT)130 static MCAsmInfo *createARMMCAsmInfo(const Target &T, StringRef TT) {
131 Triple TheTriple(TT);
132
133 if (TheTriple.isOSDarwin())
134 return new ARMMCAsmInfoDarwin();
135
136 return new ARMELFMCAsmInfo();
137 }
138
createARMMCCodeGenInfo(StringRef TT,Reloc::Model RM,CodeModel::Model CM)139 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
140 CodeModel::Model CM) {
141 MCCodeGenInfo *X = new MCCodeGenInfo();
142 if (RM == Reloc::Default) {
143 Triple TheTriple(TT);
144 // Default relocation model on Darwin is PIC, not DynamicNoPIC.
145 RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
146 }
147 X->InitMCCodeGenInfo(RM, CM);
148 return X;
149 }
150
151 // This is duplicated code. Refactor this.
createMCStreamer(const Target & T,StringRef TT,MCContext & Ctx,MCAsmBackend & MAB,raw_ostream & OS,MCCodeEmitter * Emitter,bool RelaxAll,bool NoExecStack)152 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
153 MCContext &Ctx, MCAsmBackend &MAB,
154 raw_ostream &OS,
155 MCCodeEmitter *Emitter,
156 bool RelaxAll,
157 bool NoExecStack) {
158 Triple TheTriple(TT);
159
160 if (TheTriple.isOSDarwin())
161 return createMachOStreamer(Ctx, MAB, OS, Emitter, RelaxAll);
162
163 if (TheTriple.isOSWindows()) {
164 llvm_unreachable("ARM does not support Windows COFF format");
165 return NULL;
166 }
167
168 return createELFStreamer(Ctx, MAB, OS, Emitter, RelaxAll, NoExecStack);
169 }
170
createARMMCInstPrinter(const Target & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCSubtargetInfo & STI)171 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
172 unsigned SyntaxVariant,
173 const MCAsmInfo &MAI,
174 const MCSubtargetInfo &STI) {
175 if (SyntaxVariant == 0)
176 return new ARMInstPrinter(MAI, STI);
177 return 0;
178 }
179
180 namespace {
181
182 class ARMMCInstrAnalysis : public MCInstrAnalysis {
183 public:
ARMMCInstrAnalysis(const MCInstrInfo * Info)184 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
185
isUnconditionalBranch(const MCInst & Inst) const186 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
187 // BCCs with the "always" predicate are unconditional branches.
188 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
189 return true;
190 return MCInstrAnalysis::isUnconditionalBranch(Inst);
191 }
192
isConditionalBranch(const MCInst & Inst) const193 virtual bool isConditionalBranch(const MCInst &Inst) const {
194 // BCCs with the "always" predicate are unconditional branches.
195 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
196 return false;
197 return MCInstrAnalysis::isConditionalBranch(Inst);
198 }
199
evaluateBranch(const MCInst & Inst,uint64_t Addr,uint64_t Size) const200 uint64_t evaluateBranch(const MCInst &Inst, uint64_t Addr,
201 uint64_t Size) const {
202 // We only handle PCRel branches for now.
203 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
204 return -1ULL;
205
206 int64_t Imm = Inst.getOperand(0).getImm();
207 // FIXME: This is not right for thumb.
208 return Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
209 }
210 };
211
212 }
213
createARMMCInstrAnalysis(const MCInstrInfo * Info)214 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
215 return new ARMMCInstrAnalysis(Info);
216 }
217
218 // Force static initialization.
LLVMInitializeARMTargetMC()219 extern "C" void LLVMInitializeARMTargetMC() {
220 // Register the MC asm info.
221 RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
222 RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
223
224 // Register the MC codegen info.
225 TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
226 TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
227
228 // Register the MC instruction info.
229 TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
230 TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
231
232 // Register the MC register info.
233 TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
234 TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
235
236 // Register the MC subtarget info.
237 TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
238 ARM_MC::createARMMCSubtargetInfo);
239 TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
240 ARM_MC::createARMMCSubtargetInfo);
241
242 // Register the MC instruction analyzer.
243 TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget,
244 createARMMCInstrAnalysis);
245 TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget,
246 createARMMCInstrAnalysis);
247
248 // Register the MC Code Emitter
249 TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
250 TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
251
252 // Register the asm backend.
253 TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
254 TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
255
256 // Register the object streamer.
257 TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
258 TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
259
260 // Register the MCInstPrinter.
261 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
262 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
263 }
264