1; RUN: llc < %s -march=arm -mattr=+neon,+fp16 | FileCheck %s 2 3define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind { 4;CHECK: vcvt_f32tos32: 5;CHECK: vcvt.s32.f32 6 %tmp1 = load <2 x float>* %A 7 %tmp2 = fptosi <2 x float> %tmp1 to <2 x i32> 8 ret <2 x i32> %tmp2 9} 10 11define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind { 12;CHECK: vcvt_f32tou32: 13;CHECK: vcvt.u32.f32 14 %tmp1 = load <2 x float>* %A 15 %tmp2 = fptoui <2 x float> %tmp1 to <2 x i32> 16 ret <2 x i32> %tmp2 17} 18 19define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind { 20;CHECK: vcvt_s32tof32: 21;CHECK: vcvt.f32.s32 22 %tmp1 = load <2 x i32>* %A 23 %tmp2 = sitofp <2 x i32> %tmp1 to <2 x float> 24 ret <2 x float> %tmp2 25} 26 27define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind { 28;CHECK: vcvt_u32tof32: 29;CHECK: vcvt.f32.u32 30 %tmp1 = load <2 x i32>* %A 31 %tmp2 = uitofp <2 x i32> %tmp1 to <2 x float> 32 ret <2 x float> %tmp2 33} 34 35define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind { 36;CHECK: vcvtQ_f32tos32: 37;CHECK: vcvt.s32.f32 38 %tmp1 = load <4 x float>* %A 39 %tmp2 = fptosi <4 x float> %tmp1 to <4 x i32> 40 ret <4 x i32> %tmp2 41} 42 43define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind { 44;CHECK: vcvtQ_f32tou32: 45;CHECK: vcvt.u32.f32 46 %tmp1 = load <4 x float>* %A 47 %tmp2 = fptoui <4 x float> %tmp1 to <4 x i32> 48 ret <4 x i32> %tmp2 49} 50 51define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind { 52;CHECK: vcvtQ_s32tof32: 53;CHECK: vcvt.f32.s32 54 %tmp1 = load <4 x i32>* %A 55 %tmp2 = sitofp <4 x i32> %tmp1 to <4 x float> 56 ret <4 x float> %tmp2 57} 58 59define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind { 60;CHECK: vcvtQ_u32tof32: 61;CHECK: vcvt.f32.u32 62 %tmp1 = load <4 x i32>* %A 63 %tmp2 = uitofp <4 x i32> %tmp1 to <4 x float> 64 ret <4 x float> %tmp2 65} 66 67define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind { 68;CHECK: vcvt_n_f32tos32: 69;CHECK: vcvt.s32.f32 70 %tmp1 = load <2 x float>* %A 71 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1) 72 ret <2 x i32> %tmp2 73} 74 75define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind { 76;CHECK: vcvt_n_f32tou32: 77;CHECK: vcvt.u32.f32 78 %tmp1 = load <2 x float>* %A 79 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1) 80 ret <2 x i32> %tmp2 81} 82 83define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind { 84;CHECK: vcvt_n_s32tof32: 85;CHECK: vcvt.f32.s32 86 %tmp1 = load <2 x i32>* %A 87 %tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1) 88 ret <2 x float> %tmp2 89} 90 91define <2 x float> @vcvt_n_u32tof32(<2 x i32>* %A) nounwind { 92;CHECK: vcvt_n_u32tof32: 93;CHECK: vcvt.f32.u32 94 %tmp1 = load <2 x i32>* %A 95 %tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1) 96 ret <2 x float> %tmp2 97} 98 99declare <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float>, i32) nounwind readnone 100declare <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float>, i32) nounwind readnone 101declare <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone 102declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone 103 104define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind { 105;CHECK: vcvtQ_n_f32tos32: 106;CHECK: vcvt.s32.f32 107 %tmp1 = load <4 x float>* %A 108 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1) 109 ret <4 x i32> %tmp2 110} 111 112define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind { 113;CHECK: vcvtQ_n_f32tou32: 114;CHECK: vcvt.u32.f32 115 %tmp1 = load <4 x float>* %A 116 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1) 117 ret <4 x i32> %tmp2 118} 119 120define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind { 121;CHECK: vcvtQ_n_s32tof32: 122;CHECK: vcvt.f32.s32 123 %tmp1 = load <4 x i32>* %A 124 %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1) 125 ret <4 x float> %tmp2 126} 127 128define <4 x float> @vcvtQ_n_u32tof32(<4 x i32>* %A) nounwind { 129;CHECK: vcvtQ_n_u32tof32: 130;CHECK: vcvt.f32.u32 131 %tmp1 = load <4 x i32>* %A 132 %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1) 133 ret <4 x float> %tmp2 134} 135 136declare <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32) nounwind readnone 137declare <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwind readnone 138declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone 139declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone 140 141define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind { 142;CHECK: vcvt_f16tof32: 143;CHECK: vcvt.f32.f16 144 %tmp1 = load <4 x i16>* %A 145 %tmp2 = call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %tmp1) 146 ret <4 x float> %tmp2 147} 148 149define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind { 150;CHECK: vcvt_f32tof16: 151;CHECK: vcvt.f16.f32 152 %tmp1 = load <4 x float>* %A 153 %tmp2 = call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %tmp1) 154 ret <4 x i16> %tmp2 155} 156 157declare <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16>) nounwind readnone 158declare <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float>) nounwind readnone 159