1; RUN: llc < %s -march=x86 -post-RA-scheduler=false | FileCheck %s 2; rdar://7226797 3 4; LLVM should omit the testl and use the flags result from the orl. 5 6; CHECK: or: 7define void @or(float* %A, i32 %IA, i32 %N) nounwind { 8entry: 9 %0 = ptrtoint float* %A to i32 ; <i32> [#uses=1] 10 %1 = and i32 %0, 3 ; <i32> [#uses=1] 11 %2 = xor i32 %IA, 1 ; <i32> [#uses=1] 12; CHECK: orl %e 13; CHECK-NEXT: je 14 %3 = or i32 %2, %1 ; <i32> [#uses=1] 15 %4 = icmp eq i32 %3, 0 ; <i1> [#uses=1] 16 br i1 %4, label %return, label %bb 17 18bb: ; preds = %entry 19 store float 0.000000e+00, float* %A, align 4 20 ret void 21 22return: ; preds = %entry 23 ret void 24} 25; CHECK: xor: 26define void @xor(float* %A, i32 %IA, i32 %N) nounwind { 27entry: 28 %0 = ptrtoint float* %A to i32 ; <i32> [#uses=1] 29 %1 = and i32 %0, 3 ; <i32> [#uses=1] 30; CHECK: xorl $1, %e 31; CHECK-NEXT: je 32 %2 = xor i32 %IA, 1 ; <i32> [#uses=1] 33 %3 = xor i32 %2, %1 ; <i32> [#uses=1] 34 %4 = icmp eq i32 %3, 0 ; <i1> [#uses=1] 35 br i1 %4, label %return, label %bb 36 37bb: ; preds = %entry 38 store float 0.000000e+00, float* %A, align 4 39 ret void 40 41return: ; preds = %entry 42 ret void 43} 44; CHECK: and: 45define void @and(float* %A, i32 %IA, i32 %N, i8* %p) nounwind { 46entry: 47 store i8 0, i8* %p 48 %0 = ptrtoint float* %A to i32 ; <i32> [#uses=1] 49 %1 = and i32 %0, 3 ; <i32> [#uses=1] 50 %2 = xor i32 %IA, 1 ; <i32> [#uses=1] 51; CHECK: andl $3, % 52; CHECK-NEXT: movb % 53; CHECK-NEXT: je 54 %3 = and i32 %2, %1 ; <i32> [#uses=1] 55 %t = trunc i32 %3 to i8 56 store i8 %t, i8* %p 57 %4 = icmp eq i32 %3, 0 ; <i1> [#uses=1] 58 br i1 %4, label %return, label %bb 59 60bb: ; preds = %entry 61 store float 0.000000e+00, float* null, align 4 62 ret void 63 64return: ; preds = %entry 65 ret void 66} 67 68; Just like @and, but without the trunc+store. This should use a testb 69; instead of an andl. 70; CHECK: test: 71define void @test(float* %A, i32 %IA, i32 %N, i8* %p) nounwind { 72entry: 73 store i8 0, i8* %p 74 %0 = ptrtoint float* %A to i32 ; <i32> [#uses=1] 75 %1 = and i32 %0, 3 ; <i32> [#uses=1] 76 %2 = xor i32 %IA, 1 ; <i32> [#uses=1] 77; CHECK: testb $3, % 78; CHECK-NEXT: je 79 %3 = and i32 %2, %1 ; <i32> [#uses=1] 80 %4 = icmp eq i32 %3, 0 ; <i1> [#uses=1] 81 br i1 %4, label %return, label %bb 82 83bb: ; preds = %entry 84 store float 0.000000e+00, float* null, align 4 85 ret void 86 87return: ; preds = %entry 88 ret void 89} 90