1; This test makes sure that these instructions are properly eliminated. 2; PR1822 3 4; RUN: opt < %s -instcombine -S | FileCheck %s 5 6define i32 @test1(i32 %A, i32 %B) { 7 %C = select i1 false, i32 %A, i32 %B 8 ret i32 %C 9; CHECK: @test1 10; CHECK: ret i32 %B 11} 12 13define i32 @test2(i32 %A, i32 %B) { 14 %C = select i1 true, i32 %A, i32 %B 15 ret i32 %C 16; CHECK: @test2 17; CHECK: ret i32 %A 18} 19 20 21define i32 @test3(i1 %C, i32 %I) { 22 ; V = I 23 %V = select i1 %C, i32 %I, i32 %I 24 ret i32 %V 25; CHECK: @test3 26; CHECK: ret i32 %I 27} 28 29define i1 @test4(i1 %C) { 30 ; V = C 31 %V = select i1 %C, i1 true, i1 false 32 ret i1 %V 33; CHECK: @test4 34; CHECK: ret i1 %C 35} 36 37define i1 @test5(i1 %C) { 38 ; V = !C 39 %V = select i1 %C, i1 false, i1 true 40 ret i1 %V 41; CHECK: @test5 42; CHECK: xor i1 %C, true 43; CHECK: ret i1 44} 45 46define i32 @test6(i1 %C) { 47 ; V = cast C to int 48 %V = select i1 %C, i32 1, i32 0 49 ret i32 %V 50; CHECK: @test6 51; CHECK: %V = zext i1 %C to i32 52; CHECK: ret i32 %V 53} 54 55define i1 @test7(i1 %C, i1 %X) { 56 ; R = or C, X 57 %R = select i1 %C, i1 true, i1 %X 58 ret i1 %R 59; CHECK: @test7 60; CHECK: %R = or i1 %C, %X 61; CHECK: ret i1 %R 62} 63 64define i1 @test8(i1 %C, i1 %X) { 65 ; R = and C, X 66 %R = select i1 %C, i1 %X, i1 false 67 ret i1 %R 68; CHECK: @test8 69; CHECK: %R = and i1 %C, %X 70; CHECK: ret i1 %R 71} 72 73define i1 @test9(i1 %C, i1 %X) { 74 ; R = and !C, X 75 %R = select i1 %C, i1 false, i1 %X 76 ret i1 %R 77; CHECK: @test9 78; CHECK: xor i1 %C, true 79; CHECK: %R = and i1 80; CHECK: ret i1 %R 81} 82 83define i1 @test10(i1 %C, i1 %X) { 84 ; R = or !C, X 85 %R = select i1 %C, i1 %X, i1 true 86 ret i1 %R 87; CHECK: @test10 88; CHECK: xor i1 %C, true 89; CHECK: %R = or i1 90; CHECK: ret i1 %R 91} 92 93define i32 @test11(i32 %a) { 94 %C = icmp eq i32 %a, 0 95 %R = select i1 %C, i32 0, i32 1 96 ret i32 %R 97; CHECK: @test11 98; CHECK: icmp ne i32 %a, 0 99; CHECK: %R = zext i1 100; CHECK: ret i32 %R 101} 102 103define i32 @test12(i1 %cond, i32 %a) { 104 %b = or i32 %a, 1 105 %c = select i1 %cond, i32 %b, i32 %a 106 ret i32 %c 107; CHECK: @test12 108; CHECK: %b = zext i1 %cond to i32 109; CHECK: %c = or i32 %b, %a 110; CHECK: ret i32 %c 111} 112 113define i32 @test12a(i1 %cond, i32 %a) { 114 %b = ashr i32 %a, 1 115 %c = select i1 %cond, i32 %b, i32 %a 116 ret i32 %c 117; CHECK: @test12a 118; CHECK: %b = zext i1 %cond to i32 119; CHECK: %c = ashr i32 %a, %b 120; CHECK: ret i32 %c 121} 122 123define i32 @test12b(i1 %cond, i32 %a) { 124 %b = ashr i32 %a, 1 125 %c = select i1 %cond, i32 %a, i32 %b 126 ret i32 %c 127; CHECK: @test12b 128; CHECK: zext i1 %cond to i32 129; CHECK: %b = xor i32 130; CHECK: %c = ashr i32 %a, %b 131; CHECK: ret i32 %c 132} 133 134define i32 @test13(i32 %a, i32 %b) { 135 %C = icmp eq i32 %a, %b 136 %V = select i1 %C, i32 %a, i32 %b 137 ret i32 %V 138; CHECK: @test13 139; CHECK: ret i32 %b 140} 141 142define i32 @test13a(i32 %a, i32 %b) { 143 %C = icmp ne i32 %a, %b 144 %V = select i1 %C, i32 %a, i32 %b 145 ret i32 %V 146; CHECK: @test13a 147; CHECK: ret i32 %a 148} 149 150define i32 @test13b(i32 %a, i32 %b) { 151 %C = icmp eq i32 %a, %b 152 %V = select i1 %C, i32 %b, i32 %a 153 ret i32 %V 154; CHECK: @test13b 155; CHECK: ret i32 %a 156} 157 158define i1 @test14a(i1 %C, i32 %X) { 159 %V = select i1 %C, i32 %X, i32 0 160 ; (X < 1) | !C 161 %R = icmp slt i32 %V, 1 162 ret i1 %R 163; CHECK: @test14a 164; CHECK: icmp slt i32 %X, 1 165; CHECK: xor i1 %C, true 166; CHECK: or i1 167; CHECK: ret i1 %R 168} 169 170define i1 @test14b(i1 %C, i32 %X) { 171 %V = select i1 %C, i32 0, i32 %X 172 ; (X < 1) | C 173 %R = icmp slt i32 %V, 1 174 ret i1 %R 175; CHECK: @test14b 176; CHECK: icmp slt i32 %X, 1 177; CHECK: or i1 178; CHECK: ret i1 %R 179} 180 181;; Code sequence for (X & 16) ? 16 : 0 182define i32 @test15a(i32 %X) { 183 %t1 = and i32 %X, 16 184 %t2 = icmp eq i32 %t1, 0 185 %t3 = select i1 %t2, i32 0, i32 16 186 ret i32 %t3 187; CHECK: @test15a 188; CHECK: %t1 = and i32 %X, 16 189; CHECK: ret i32 %t1 190} 191 192;; Code sequence for (X & 32) ? 0 : 24 193define i32 @test15b(i32 %X) { 194 %t1 = and i32 %X, 32 195 %t2 = icmp eq i32 %t1, 0 196 %t3 = select i1 %t2, i32 32, i32 0 197 ret i32 %t3 198; CHECK: @test15b 199; CHECK: %t1 = and i32 %X, 32 200; CHECK: xor i32 %t1, 32 201; CHECK: ret i32 202} 203 204;; Alternate code sequence for (X & 16) ? 16 : 0 205define i32 @test15c(i32 %X) { 206 %t1 = and i32 %X, 16 207 %t2 = icmp eq i32 %t1, 16 208 %t3 = select i1 %t2, i32 16, i32 0 209 ret i32 %t3 210; CHECK: @test15c 211; CHECK: %t1 = and i32 %X, 16 212; CHECK: ret i32 %t1 213} 214 215;; Alternate code sequence for (X & 16) ? 16 : 0 216define i32 @test15d(i32 %X) { 217 %t1 = and i32 %X, 16 218 %t2 = icmp ne i32 %t1, 0 219 %t3 = select i1 %t2, i32 16, i32 0 220 ret i32 %t3 221; CHECK: @test15d 222; CHECK: %t1 = and i32 %X, 16 223; CHECK: ret i32 %t1 224} 225 226;; (a & 128) ? 256 : 0 227define i32 @test15e(i32 %X) { 228 %t1 = and i32 %X, 128 229 %t2 = icmp ne i32 %t1, 0 230 %t3 = select i1 %t2, i32 256, i32 0 231 ret i32 %t3 232; CHECK: @test15e 233; CHECK: %t1 = shl i32 %X, 1 234; CHECK: and i32 %t1, 256 235; CHECK: ret i32 236} 237 238;; (a & 128) ? 0 : 256 239define i32 @test15f(i32 %X) { 240 %t1 = and i32 %X, 128 241 %t2 = icmp ne i32 %t1, 0 242 %t3 = select i1 %t2, i32 0, i32 256 243 ret i32 %t3 244; CHECK: @test15f 245; CHECK: %t1 = shl i32 %X, 1 246; CHECK: and i32 %t1, 256 247; CHECK: xor i32 %{{.*}}, 256 248; CHECK: ret i32 249} 250 251;; (a & 8) ? -1 : -9 252define i32 @test15g(i32 %X) { 253 %t1 = and i32 %X, 8 254 %t2 = icmp ne i32 %t1, 0 255 %t3 = select i1 %t2, i32 -1, i32 -9 256 ret i32 %t3 257; CHECK: @test15g 258; CHECK-NEXT: %1 = or i32 %X, -9 259; CHECK-NEXT: ret i32 %1 260} 261 262;; (a & 8) ? -9 : -1 263define i32 @test15h(i32 %X) { 264 %t1 = and i32 %X, 8 265 %t2 = icmp ne i32 %t1, 0 266 %t3 = select i1 %t2, i32 -9, i32 -1 267 ret i32 %t3 268; CHECK: @test15h 269; CHECK-NEXT: %1 = or i32 %X, -9 270; CHECK-NEXT: %2 = xor i32 %1, 8 271; CHECK-NEXT: ret i32 %2 272} 273 274;; (a & 2) ? 577 : 1089 275define i32 @test15i(i32 %X) { 276 %t1 = and i32 %X, 2 277 %t2 = icmp ne i32 %t1, 0 278 %t3 = select i1 %t2, i32 577, i32 1089 279 ret i32 %t3 280; CHECK: @test15i 281; CHECK-NEXT: %t1 = shl i32 %X, 8 282; CHECK-NEXT: %1 = and i32 %t1, 512 283; CHECK-NEXT: %2 = xor i32 %1, 512 284; CHECK-NEXT: %3 = add i32 %2, 577 285; CHECK-NEXT: ret i32 %3 286} 287 288;; (a & 2) ? 1089 : 577 289define i32 @test15j(i32 %X) { 290 %t1 = and i32 %X, 2 291 %t2 = icmp ne i32 %t1, 0 292 %t3 = select i1 %t2, i32 1089, i32 577 293 ret i32 %t3 294; CHECK: @test15j 295; CHECK-NEXT: %t1 = shl i32 %X, 8 296; CHECK-NEXT: %1 = and i32 %t1, 512 297; CHECK-NEXT: %2 = add i32 %1, 577 298; CHECK-NEXT: ret i32 %2 299} 300 301define i32 @test16(i1 %C, i32* %P) { 302 %P2 = select i1 %C, i32* %P, i32* null 303 %V = load i32* %P2 304 ret i32 %V 305; CHECK: @test16 306; CHECK-NEXT: %V = load i32* %P 307; CHECK: ret i32 %V 308} 309 310define i1 @test17(i32* %X, i1 %C) { 311 %R = select i1 %C, i32* %X, i32* null 312 %RV = icmp eq i32* %R, null 313 ret i1 %RV 314; CHECK: @test17 315; CHECK: icmp eq i32* %X, null 316; CHECK: xor i1 %C, true 317; CHECK: %RV = or i1 318; CHECK: ret i1 %RV 319} 320 321define i32 @test18(i32 %X, i32 %Y, i1 %C) { 322 %R = select i1 %C, i32 %X, i32 0 323 %V = sdiv i32 %Y, %R 324 ret i32 %V 325; CHECK: @test18 326; CHECK: %V = sdiv i32 %Y, %X 327; CHECK: ret i32 %V 328} 329 330define i32 @test19(i32 %x) { 331 %tmp = icmp ugt i32 %x, 2147483647 332 %retval = select i1 %tmp, i32 -1, i32 0 333 ret i32 %retval 334; CHECK: @test19 335; CHECK-NEXT: ashr i32 %x, 31 336; CHECK-NEXT: ret i32 337} 338 339define i32 @test20(i32 %x) { 340 %tmp = icmp slt i32 %x, 0 341 %retval = select i1 %tmp, i32 -1, i32 0 342 ret i32 %retval 343; CHECK: @test20 344; CHECK-NEXT: ashr i32 %x, 31 345; CHECK-NEXT: ret i32 346} 347 348define i64 @test21(i32 %x) { 349 %tmp = icmp slt i32 %x, 0 350 %retval = select i1 %tmp, i64 -1, i64 0 351 ret i64 %retval 352; CHECK: @test21 353; CHECK-NEXT: ashr i32 %x, 31 354; CHECK-NEXT: sext i32 355; CHECK-NEXT: ret i64 356} 357 358define i16 @test22(i32 %x) { 359 %tmp = icmp slt i32 %x, 0 360 %retval = select i1 %tmp, i16 -1, i16 0 361 ret i16 %retval 362; CHECK: @test22 363; CHECK-NEXT: ashr i32 %x, 31 364; CHECK-NEXT: trunc i32 365; CHECK-NEXT: ret i16 366} 367 368define i1 @test23(i1 %a, i1 %b) { 369 %c = select i1 %a, i1 %b, i1 %a 370 ret i1 %c 371; CHECK: @test23 372; CHECK-NEXT: %c = and i1 %a, %b 373; CHECK-NEXT: ret i1 %c 374} 375 376define i1 @test24(i1 %a, i1 %b) { 377 %c = select i1 %a, i1 %a, i1 %b 378 ret i1 %c 379; CHECK: @test24 380; CHECK-NEXT: %c = or i1 %a, %b 381; CHECK-NEXT: ret i1 %c 382} 383 384define i32 @test25(i1 %c) { 385entry: 386 br i1 %c, label %jump, label %ret 387jump: 388 br label %ret 389ret: 390 %a = phi i1 [true, %jump], [false, %entry] 391 %b = select i1 %a, i32 10, i32 20 392 ret i32 %b 393; CHECK: @test25 394; CHECK: %a = phi i32 [ 10, %jump ], [ 20, %entry ] 395; CHECK-NEXT: ret i32 %a 396} 397 398define i32 @test26(i1 %cond) { 399entry: 400 br i1 %cond, label %jump, label %ret 401jump: 402 %c = or i1 false, false 403 br label %ret 404ret: 405 %a = phi i1 [true, %jump], [%c, %entry] 406 %b = select i1 %a, i32 10, i32 20 407 ret i32 %b 408; CHECK: @test26 409; CHECK: %a = phi i32 [ 10, %jump ], [ 20, %entry ] 410; CHECK-NEXT: ret i32 %a 411} 412 413define i32 @test27(i1 %c, i32 %A, i32 %B) { 414entry: 415 br i1 %c, label %jump, label %ret 416jump: 417 br label %ret 418ret: 419 %a = phi i1 [true, %jump], [false, %entry] 420 %b = select i1 %a, i32 %A, i32 %B 421 ret i32 %b 422; CHECK: @test27 423; CHECK: %a = phi i32 [ %A, %jump ], [ %B, %entry ] 424; CHECK-NEXT: ret i32 %a 425} 426 427define i32 @test28(i1 %cond, i32 %A, i32 %B) { 428entry: 429 br i1 %cond, label %jump, label %ret 430jump: 431 br label %ret 432ret: 433 %c = phi i32 [%A, %jump], [%B, %entry] 434 %a = phi i1 [true, %jump], [false, %entry] 435 %b = select i1 %a, i32 %A, i32 %c 436 ret i32 %b 437; CHECK: @test28 438; CHECK: %a = phi i32 [ %A, %jump ], [ %B, %entry ] 439; CHECK-NEXT: ret i32 %a 440} 441 442define i32 @test29(i1 %cond, i32 %A, i32 %B) { 443entry: 444 br i1 %cond, label %jump, label %ret 445jump: 446 br label %ret 447ret: 448 %c = phi i32 [%A, %jump], [%B, %entry] 449 %a = phi i1 [true, %jump], [false, %entry] 450 br label %next 451 452next: 453 %b = select i1 %a, i32 %A, i32 %c 454 ret i32 %b 455; CHECK: @test29 456; CHECK: %a = phi i32 [ %A, %jump ], [ %B, %entry ] 457; CHECK: ret i32 %a 458} 459 460 461; SMAX(SMAX(x, y), x) -> SMAX(x, y) 462define i32 @test30(i32 %x, i32 %y) { 463 %cmp = icmp sgt i32 %x, %y 464 %cond = select i1 %cmp, i32 %x, i32 %y 465 466 %cmp5 = icmp sgt i32 %cond, %x 467 %retval = select i1 %cmp5, i32 %cond, i32 %x 468 ret i32 %retval 469; CHECK: @test30 470; CHECK: ret i32 %cond 471} 472 473; UMAX(UMAX(x, y), x) -> UMAX(x, y) 474define i32 @test31(i32 %x, i32 %y) { 475 %cmp = icmp ugt i32 %x, %y 476 %cond = select i1 %cmp, i32 %x, i32 %y 477 %cmp5 = icmp ugt i32 %cond, %x 478 %retval = select i1 %cmp5, i32 %cond, i32 %x 479 ret i32 %retval 480; CHECK: @test31 481; CHECK: ret i32 %cond 482} 483 484; SMIN(SMIN(x, y), x) -> SMIN(x, y) 485define i32 @test32(i32 %x, i32 %y) { 486 %cmp = icmp sgt i32 %x, %y 487 %cond = select i1 %cmp, i32 %y, i32 %x 488 %cmp5 = icmp sgt i32 %cond, %x 489 %retval = select i1 %cmp5, i32 %x, i32 %cond 490 ret i32 %retval 491; CHECK: @test32 492; CHECK: ret i32 %cond 493} 494 495; MAX(MIN(x, y), x) -> x 496define i32 @test33(i32 %x, i32 %y) { 497 %cmp = icmp sgt i32 %x, %y 498 %cond = select i1 %cmp, i32 %y, i32 %x 499 %cmp5 = icmp sgt i32 %cond, %x 500 %retval = select i1 %cmp5, i32 %cond, i32 %x 501 ret i32 %retval 502; CHECK: @test33 503; CHECK: ret i32 %x 504} 505 506; MIN(MAX(x, y), x) -> x 507define i32 @test34(i32 %x, i32 %y) { 508 %cmp = icmp sgt i32 %x, %y 509 %cond = select i1 %cmp, i32 %x, i32 %y 510 %cmp5 = icmp sgt i32 %cond, %x 511 %retval = select i1 %cmp5, i32 %x, i32 %cond 512 ret i32 %retval 513; CHECK: @test34 514; CHECK: ret i32 %x 515} 516 517define i32 @test35(i32 %x) { 518 %cmp = icmp sge i32 %x, 0 519 %cond = select i1 %cmp, i32 60, i32 100 520 ret i32 %cond 521; CHECK: @test35 522; CHECK: ashr i32 %x, 31 523; CHECK: and i32 {{.*}}, 40 524; CHECK: add i32 {{.*}}, 60 525; CHECK: ret 526} 527 528define i32 @test36(i32 %x) { 529 %cmp = icmp slt i32 %x, 0 530 %cond = select i1 %cmp, i32 60, i32 100 531 ret i32 %cond 532; CHECK: @test36 533; CHECK: ashr i32 %x, 31 534; CHECK: and i32 {{.*}}, -40 535; CHECK: add i32 {{.*}}, 100 536; CHECK: ret 537} 538 539define i32 @test37(i32 %x) { 540 %cmp = icmp sgt i32 %x, -1 541 %cond = select i1 %cmp, i32 1, i32 -1 542 ret i32 %cond 543; CHECK: @test37 544; CHECK: ashr i32 %x, 31 545; CHECK: or i32 {{.*}}, 1 546; CHECK: ret 547} 548 549define i1 @test38(i1 %cond) { 550 %zero = alloca i32 551 %one = alloca i32 552 %ptr = select i1 %cond, i32* %zero, i32* %one 553 %isnull = icmp eq i32* %ptr, null 554 ret i1 %isnull 555; CHECK: @test38 556; CHECK: ret i1 false 557} 558 559define i1 @test39(i1 %cond, double %x) { 560 %s = select i1 %cond, double %x, double 0x7FF0000000000000 ; RHS = +infty 561 %cmp = fcmp ule double %x, %s 562 ret i1 %cmp 563; CHECK: @test39 564; CHECK: ret i1 true 565} 566 567define i1 @test40(i1 %cond) { 568 %a = alloca i32 569 %b = alloca i32 570 %c = alloca i32 571 %s = select i1 %cond, i32* %a, i32* %b 572 %r = icmp eq i32* %s, %c 573 ret i1 %r 574; CHECK: @test40 575; CHECK: ret i1 false 576} 577 578define i32 @test41(i1 %cond, i32 %x, i32 %y) { 579 %z = and i32 %x, %y 580 %s = select i1 %cond, i32 %y, i32 %z 581 %r = and i32 %x, %s 582 ret i32 %r 583; CHECK: @test41 584; CHECK-NEXT: and i32 %x, %y 585; CHECK-NEXT: ret i32 586} 587 588define i32 @test42(i32 %x, i32 %y) { 589 %b = add i32 %y, -1 590 %cond = icmp eq i32 %x, 0 591 %c = select i1 %cond, i32 %b, i32 %y 592 ret i32 %c 593; CHECK: @test42 594; CHECK-NEXT: %cond = icmp eq i32 %x, 0 595; CHECK-NEXT: %b = sext i1 %cond to i32 596; CHECK-NEXT: %c = add i32 %b, %y 597; CHECK-NEXT: ret i32 %c 598} 599 600define i64 @test43(i32 %a) nounwind { 601 %a_ext = sext i32 %a to i64 602 %is_a_nonnegative = icmp sgt i32 %a, -1 603 %max = select i1 %is_a_nonnegative, i64 %a_ext, i64 0 604 ret i64 %max 605; CHECK: @test43 606; CHECK-NEXT: %a_ext = sext i32 %a to i64 607; CHECK-NEXT: %is_a_nonnegative = icmp slt i64 %a_ext, 0 608; CHECK-NEXT: %max = select i1 %is_a_nonnegative, i64 0, i64 %a_ext 609; CHECK-NEXT: ret i64 %max 610} 611 612define i64 @test44(i32 %a) nounwind { 613 %a_ext = sext i32 %a to i64 614 %is_a_nonpositive = icmp slt i32 %a, 1 615 %min = select i1 %is_a_nonpositive, i64 %a_ext, i64 0 616 ret i64 %min 617; CHECK: @test44 618; CHECK-NEXT: %a_ext = sext i32 %a to i64 619; CHECK-NEXT: %is_a_nonpositive = icmp sgt i64 %a_ext, 0 620; CHECK-NEXT: %min = select i1 %is_a_nonpositive, i64 0, i64 %a_ext 621; CHECK-NEXT: ret i64 %min 622} 623define i64 @test45(i32 %a) nounwind { 624 %a_ext = zext i32 %a to i64 625 %is_a_nonnegative = icmp ugt i32 %a, 2 626 %max = select i1 %is_a_nonnegative, i64 %a_ext, i64 3 627 ret i64 %max 628; CHECK: @test45 629; CHECK-NEXT: %a_ext = zext i32 %a to i64 630; CHECK-NEXT: %is_a_nonnegative = icmp ult i64 %a_ext, 3 631; CHECK-NEXT: %max = select i1 %is_a_nonnegative, i64 3, i64 %a_ext 632; CHECK-NEXT: ret i64 %max 633} 634 635define i64 @test46(i32 %a) nounwind { 636 %a_ext = zext i32 %a to i64 637 %is_a_nonpositive = icmp ult i32 %a, 3 638 %min = select i1 %is_a_nonpositive, i64 %a_ext, i64 2 639 ret i64 %min 640; CHECK: @test46 641; CHECK-NEXT: %a_ext = zext i32 %a to i64 642; CHECK-NEXT: %is_a_nonpositive = icmp ugt i64 %a_ext, 2 643; CHECK-NEXT: %min = select i1 %is_a_nonpositive, i64 2, i64 %a_ext 644; CHECK-NEXT: ret i64 %min 645} 646define i64 @test47(i32 %a) nounwind { 647 %a_ext = sext i32 %a to i64 648 %is_a_nonnegative = icmp ugt i32 %a, 2 649 %max = select i1 %is_a_nonnegative, i64 %a_ext, i64 3 650 ret i64 %max 651; CHECK: @test47 652; CHECK-NEXT: %a_ext = sext i32 %a to i64 653; CHECK-NEXT: %is_a_nonnegative = icmp ult i64 %a_ext, 3 654; CHECK-NEXT: %max = select i1 %is_a_nonnegative, i64 3, i64 %a_ext 655; CHECK-NEXT: ret i64 %max 656} 657 658define i64 @test48(i32 %a) nounwind { 659 %a_ext = sext i32 %a to i64 660 %is_a_nonpositive = icmp ult i32 %a, 3 661 %min = select i1 %is_a_nonpositive, i64 %a_ext, i64 2 662 ret i64 %min 663; CHECK: @test48 664; CHECK-NEXT: %a_ext = sext i32 %a to i64 665; CHECK-NEXT: %is_a_nonpositive = icmp ugt i64 %a_ext, 2 666; CHECK-NEXT: %min = select i1 %is_a_nonpositive, i64 2, i64 %a_ext 667; CHECK-NEXT: ret i64 %min 668} 669 670define i64 @test49(i32 %a) nounwind { 671 %a_ext = sext i32 %a to i64 672 %is_a_nonpositive = icmp ult i32 %a, 3 673 %min = select i1 %is_a_nonpositive, i64 2, i64 %a_ext 674 ret i64 %min 675; CHECK: @test49 676; CHECK-NEXT: %a_ext = sext i32 %a to i64 677; CHECK-NEXT: %is_a_nonpositive = icmp ugt i64 %a_ext, 2 678; CHECK-NEXT: %min = select i1 %is_a_nonpositive, i64 %a_ext, i64 2 679; CHECK-NEXT: ret i64 %min 680} 681define i64 @test50(i32 %a) nounwind { 682 %is_a_nonpositive = icmp ult i32 %a, 3 683 %a_ext = sext i32 %a to i64 684 %min = select i1 %is_a_nonpositive, i64 2, i64 %a_ext 685 ret i64 %min 686; CHECK: @test50 687; CHECK-NEXT: %a_ext = sext i32 %a to i64 688; CHECK-NEXT: %is_a_nonpositive = icmp ugt i64 %a_ext, 2 689; CHECK-NEXT: %min = select i1 %is_a_nonpositive, i64 %a_ext, i64 2 690; CHECK-NEXT: ret i64 %min 691} 692 693; PR8994 694 695; This select instruction can't be eliminated because trying to do so would 696; change the number of vector elements. This used to assert. 697define i48 @test51(<3 x i1> %icmp, <3 x i16> %tmp) { 698; CHECK: @test51 699 %select = select <3 x i1> %icmp, <3 x i16> zeroinitializer, <3 x i16> %tmp 700; CHECK: select <3 x i1> 701 %tmp2 = bitcast <3 x i16> %select to i48 702 ret i48 %tmp2 703} 704 705; PR8575 706 707define i32 @test52(i32 %n, i32 %m) nounwind { 708; CHECK: @test52 709 %cmp = icmp sgt i32 %n, %m 710 %. = select i1 %cmp, i32 1, i32 3 711 %add = add nsw i32 %., 3 712 %storemerge = select i1 %cmp, i32 %., i32 %add 713; CHECK: select i1 %cmp, i32 1, i32 6 714 ret i32 %storemerge 715} 716 717; PR9454 718define i32 @test53(i32 %x) nounwind { 719 %and = and i32 %x, 2 720 %cmp = icmp eq i32 %and, %x 721 %sel = select i1 %cmp, i32 2, i32 1 722 ret i32 %sel 723; CHECK: @test53 724; CHECK: select i1 %cmp 725; CHECK: ret 726} 727 728define i32 @test54(i32 %X, i32 %Y) { 729 %A = ashr exact i32 %X, %Y 730 %B = icmp eq i32 %A, 0 731 %C = select i1 %B, i32 %A, i32 1 732 ret i32 %C 733; CHECK: @test54 734; CHECK-NOT: ashr 735; CHECK-NOT: select 736; CHECK: icmp ne i32 %X, 0 737; CHECK: zext 738; CHECK: ret 739} 740 741define i1 @test55(i1 %X, i32 %Y, i32 %Z) { 742 %A = ashr exact i32 %Y, %Z 743 %B = select i1 %X, i32 %Y, i32 %A 744 %C = icmp eq i32 %B, 0 745 ret i1 %C 746; CHECK: @test55 747; CHECK-NOT: ashr 748; CHECK-NOT: select 749; CHECK: icmp eq 750; CHECK: ret i1 751} 752 753define i32 @test56(i16 %x) nounwind { 754 %tobool = icmp eq i16 %x, 0 755 %conv = zext i16 %x to i32 756 %cond = select i1 %tobool, i32 0, i32 %conv 757 ret i32 %cond 758; CHECK: @test56 759; CHECK-NEXT: zext 760; CHECK-NEXT: ret 761} 762 763define i32 @test57(i32 %x, i32 %y) nounwind { 764 %and = and i32 %x, %y 765 %tobool = icmp eq i32 %x, 0 766 %.and = select i1 %tobool, i32 0, i32 %and 767 ret i32 %.and 768; CHECK: @test57 769; CHECK-NEXT: and i32 %x, %y 770; CHECK-NEXT: ret 771} 772 773define i32 @test58(i16 %x) nounwind { 774 %tobool = icmp ne i16 %x, 1 775 %conv = zext i16 %x to i32 776 %cond = select i1 %tobool, i32 %conv, i32 1 777 ret i32 %cond 778; CHECK: @test58 779; CHECK-NEXT: zext 780; CHECK-NEXT: ret 781} 782 783define i32 @test59(i32 %x, i32 %y) nounwind { 784 %and = and i32 %x, %y 785 %tobool = icmp ne i32 %x, %y 786 %.and = select i1 %tobool, i32 %and, i32 %y 787 ret i32 %.and 788; CHECK: @test59 789; CHECK-NEXT: and i32 %x, %y 790; CHECK-NEXT: ret 791} 792 793define i1 @test60(i32 %x, i1* %y) nounwind { 794 %cmp = icmp eq i32 %x, 0 795 %load = load i1* %y, align 1 796 %cmp1 = icmp slt i32 %x, 1 797 %sel = select i1 %cmp, i1 %load, i1 %cmp1 798 ret i1 %sel 799; CHECK: @test60 800; CHECK: select 801} 802 803@glbl = constant i32 10 804define i32 @test61(i32* %ptr) { 805 %A = load i32* %ptr 806 %B = icmp eq i32* %ptr, @glbl 807 %C = select i1 %B, i32 %A, i32 10 808 ret i32 %C 809; CHECK: @test61 810; CHECK: ret i32 10 811} 812