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1 //===- TableGen.cpp - Top-Level TableGen implementation for LLVM ----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the main function for LLVM's TableGen.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AsmMatcherEmitter.h"
15 #include "AsmWriterEmitter.h"
16 #include "CallingConvEmitter.h"
17 #include "CodeEmitterGen.h"
18 #include "DAGISelEmitter.h"
19 #include "DisassemblerEmitter.h"
20 #include "EDEmitter.h"
21 #include "FastISelEmitter.h"
22 #include "InstrInfoEmitter.h"
23 #include "IntrinsicEmitter.h"
24 #include "PseudoLoweringEmitter.h"
25 #include "RegisterInfoEmitter.h"
26 #include "ARMDecoderEmitter.h"
27 #include "SubtargetEmitter.h"
28 #include "SetTheory.h"
29 
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/PrettyStackTrace.h"
32 #include "llvm/Support/Signals.h"
33 #include "llvm/TableGen/Error.h"
34 #include "llvm/TableGen/Main.h"
35 #include "llvm/TableGen/Record.h"
36 #include "llvm/TableGen/TableGenAction.h"
37 
38 using namespace llvm;
39 
40 enum ActionType {
41   PrintRecords,
42   GenEmitter,
43   GenRegisterInfo,
44   GenInstrInfo,
45   GenAsmWriter,
46   GenAsmMatcher,
47   GenARMDecoder,
48   GenDisassembler,
49   GenPseudoLowering,
50   GenCallingConv,
51   GenDAGISel,
52   GenFastISel,
53   GenSubtarget,
54   GenIntrinsic,
55   GenTgtIntrinsic,
56   GenEDInfo,
57   PrintEnums,
58   PrintSets
59 };
60 
61 namespace {
62   cl::opt<ActionType>
63   Action(cl::desc("Action to perform:"),
64          cl::values(clEnumValN(PrintRecords, "print-records",
65                                "Print all records to stdout (default)"),
66                     clEnumValN(GenEmitter, "gen-emitter",
67                                "Generate machine code emitter"),
68                     clEnumValN(GenRegisterInfo, "gen-register-info",
69                                "Generate registers and register classes info"),
70                     clEnumValN(GenInstrInfo, "gen-instr-info",
71                                "Generate instruction descriptions"),
72                     clEnumValN(GenCallingConv, "gen-callingconv",
73                                "Generate calling convention descriptions"),
74                     clEnumValN(GenAsmWriter, "gen-asm-writer",
75                                "Generate assembly writer"),
76                     clEnumValN(GenARMDecoder, "gen-arm-decoder",
77                                "Generate decoders for ARM/Thumb"),
78                     clEnumValN(GenDisassembler, "gen-disassembler",
79                                "Generate disassembler"),
80                     clEnumValN(GenPseudoLowering, "gen-pseudo-lowering",
81                                "Generate pseudo instruction lowering"),
82                     clEnumValN(GenAsmMatcher, "gen-asm-matcher",
83                                "Generate assembly instruction matcher"),
84                     clEnumValN(GenDAGISel, "gen-dag-isel",
85                                "Generate a DAG instruction selector"),
86                     clEnumValN(GenFastISel, "gen-fast-isel",
87                                "Generate a \"fast\" instruction selector"),
88                     clEnumValN(GenSubtarget, "gen-subtarget",
89                                "Generate subtarget enumerations"),
90                     clEnumValN(GenIntrinsic, "gen-intrinsic",
91                                "Generate intrinsic information"),
92                     clEnumValN(GenTgtIntrinsic, "gen-tgt-intrinsic",
93                                "Generate target intrinsic information"),
94                     clEnumValN(GenEDInfo, "gen-enhanced-disassembly-info",
95                                "Generate enhanced disassembly info"),
96                     clEnumValN(PrintEnums, "print-enums",
97                                "Print enum values for a class"),
98                     clEnumValN(PrintSets, "print-sets",
99                                "Print expanded sets for testing DAG exprs"),
100                     clEnumValEnd));
101 
102   cl::opt<std::string>
103   Class("class", cl::desc("Print Enum list for this class"),
104         cl::value_desc("class name"));
105 }
106 
107 class LLVMTableGenAction : public TableGenAction {
108 public:
operator ()(raw_ostream & OS,RecordKeeper & Records)109   bool operator()(raw_ostream &OS, RecordKeeper &Records) {
110     switch (Action) {
111     case PrintRecords:
112       OS << Records;           // No argument, dump all contents
113       break;
114     case GenEmitter:
115       CodeEmitterGen(Records).run(OS);
116       break;
117     case GenRegisterInfo:
118       RegisterInfoEmitter(Records).run(OS);
119       break;
120     case GenInstrInfo:
121       InstrInfoEmitter(Records).run(OS);
122       break;
123     case GenCallingConv:
124       CallingConvEmitter(Records).run(OS);
125       break;
126     case GenAsmWriter:
127       AsmWriterEmitter(Records).run(OS);
128       break;
129     case GenARMDecoder:
130       ARMDecoderEmitter(Records).run(OS);
131       break;
132     case GenAsmMatcher:
133       AsmMatcherEmitter(Records).run(OS);
134       break;
135     case GenDisassembler:
136       DisassemblerEmitter(Records).run(OS);
137       break;
138     case GenPseudoLowering:
139       PseudoLoweringEmitter(Records).run(OS);
140       break;
141     case GenDAGISel:
142       DAGISelEmitter(Records).run(OS);
143       break;
144     case GenFastISel:
145       FastISelEmitter(Records).run(OS);
146       break;
147     case GenSubtarget:
148       SubtargetEmitter(Records).run(OS);
149       break;
150     case GenIntrinsic:
151       IntrinsicEmitter(Records).run(OS);
152       break;
153     case GenTgtIntrinsic:
154       IntrinsicEmitter(Records, true).run(OS);
155       break;
156     case GenEDInfo:
157       EDEmitter(Records).run(OS);
158       break;
159     case PrintEnums:
160     {
161       std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);
162       for (unsigned i = 0, e = Recs.size(); i != e; ++i)
163         OS << Recs[i]->getName() << ", ";
164       OS << "\n";
165       break;
166     }
167     case PrintSets:
168     {
169       SetTheory Sets;
170       Sets.addFieldExpander("Set", "Elements");
171       std::vector<Record*> Recs = Records.getAllDerivedDefinitions("Set");
172       for (unsigned i = 0, e = Recs.size(); i != e; ++i) {
173         OS << Recs[i]->getName() << " = [";
174         const std::vector<Record*> *Elts = Sets.expand(Recs[i]);
175         assert(Elts && "Couldn't expand Set instance");
176         for (unsigned ei = 0, ee = Elts->size(); ei != ee; ++ei)
177           OS << ' ' << (*Elts)[ei]->getName();
178         OS << " ]\n";
179       }
180       break;
181     }
182     default:
183       assert(1 && "Invalid Action");
184       return true;
185     }
186 
187     return false;
188   }
189 };
190 
main(int argc,char ** argv)191 int main(int argc, char **argv) {
192   sys::PrintStackTraceOnErrorSignal();
193   PrettyStackTraceProgram X(argc, argv);
194   cl::ParseCommandLineOptions(argc, argv);
195 
196   LLVMTableGenAction Action;
197   return TableGenMain(argv[0], Action);
198 }
199