1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* "Fast" Instruction Selector for the AArch64 target *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10// FastEmit Immediate Predicate functions. 11static bool Predicate_imm0_31(int64_t Imm) { 12 13 return ((uint64_t)Imm) < 32; 14 15} 16static bool Predicate_imm0_63(int64_t Imm) { 17 18 return ((uint64_t)Imm) < 64; 19 20} 21static bool Predicate_imm32_0_31(int64_t Imm) { 22 23 return ((uint64_t)Imm) < 32; 24 25} 26static bool Predicate_tbz_imm0_31_diag(int64_t Imm) { 27 28 return (((uint32_t)Imm) < 32); 29 30} 31static bool Predicate_tbz_imm32_63(int64_t Imm) { 32 33 return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64); 34 35} 36static bool Predicate_VectorIndexD(int64_t Imm) { 37 return ((uint64_t)Imm) < 2; 38} 39static bool Predicate_VectorIndexS(int64_t Imm) { 40 return ((uint64_t)Imm) < 4; 41} 42static bool Predicate_VectorIndexH(int64_t Imm) { 43 return ((uint64_t)Imm) < 8; 44} 45static bool Predicate_VectorIndexB(int64_t Imm) { 46 return ((uint64_t)Imm) < 16; 47} 48static bool Predicate_imm0_255(int64_t Imm) { 49 50 return ((uint32_t)Imm) < 256; 51 52} 53static bool Predicate_vecshiftL64(int64_t Imm) { 54 55 return (((uint32_t)Imm) < 64); 56 57} 58static bool Predicate_vecshiftL32(int64_t Imm) { 59 60 return (((uint32_t)Imm) < 32); 61 62} 63static bool Predicate_vecshiftR64(int64_t Imm) { 64 65 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65); 66 67} 68static bool Predicate_vecshiftL8(int64_t Imm) { 69 70 return (((uint32_t)Imm) < 8); 71 72} 73static bool Predicate_vecshiftL16(int64_t Imm) { 74 75 return (((uint32_t)Imm) < 16); 76 77} 78static bool Predicate_vecshiftR8(int64_t Imm) { 79 80 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9); 81 82} 83static bool Predicate_vecshiftR16(int64_t Imm) { 84 85 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); 86 87} 88static bool Predicate_vecshiftR32(int64_t Imm) { 89 90 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33); 91 92} 93 94 95// FastEmit functions for AArch64ISD::THREAD_POINTER. 96 97unsigned fastEmit_AArch64ISD_THREAD_POINTER_MVT_i64_(MVT RetVT) { 98 if (RetVT.SimpleTy != MVT::i64) 99 return 0; 100 return fastEmitInst_(AArch64::MOVbaseTLS, &AArch64::GPR64RegClass); 101} 102 103unsigned fastEmit_AArch64ISD_THREAD_POINTER_(MVT VT, MVT RetVT) { 104 switch (VT.SimpleTy) { 105 case MVT::i64: return fastEmit_AArch64ISD_THREAD_POINTER_MVT_i64_(RetVT); 106 default: return 0; 107 } 108} 109 110// Top-level FastEmit function. 111 112unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode) override { 113 switch (Opcode) { 114 case AArch64ISD::THREAD_POINTER: return fastEmit_AArch64ISD_THREAD_POINTER_(VT, RetVT); 115 default: return 0; 116 } 117} 118 119// FastEmit functions for AArch64ISD::CALL. 120 121unsigned fastEmit_AArch64ISD_CALL_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 122 if (RetVT.SimpleTy != MVT::isVoid) 123 return 0; 124 return fastEmitInst_r(AArch64::BLR, &AArch64::GPR64RegClass, Op0, Op0IsKill); 125} 126 127unsigned fastEmit_AArch64ISD_CALL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 128 switch (VT.SimpleTy) { 129 case MVT::i64: return fastEmit_AArch64ISD_CALL_MVT_i64_r(RetVT, Op0, Op0IsKill); 130 default: return 0; 131 } 132} 133 134// FastEmit functions for AArch64ISD::CMEQz. 135 136unsigned fastEmit_AArch64ISD_CMEQz_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 137 if (RetVT.SimpleTy != MVT::v8i8) 138 return 0; 139 if ((Subtarget->hasNEON())) { 140 return fastEmitInst_r(AArch64::CMEQv8i8rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 141 } 142 return 0; 143} 144 145unsigned fastEmit_AArch64ISD_CMEQz_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 146 if (RetVT.SimpleTy != MVT::v16i8) 147 return 0; 148 if ((Subtarget->hasNEON())) { 149 return fastEmitInst_r(AArch64::CMEQv16i8rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 150 } 151 return 0; 152} 153 154unsigned fastEmit_AArch64ISD_CMEQz_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 155 if (RetVT.SimpleTy != MVT::v4i16) 156 return 0; 157 if ((Subtarget->hasNEON())) { 158 return fastEmitInst_r(AArch64::CMEQv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 159 } 160 return 0; 161} 162 163unsigned fastEmit_AArch64ISD_CMEQz_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 164 if (RetVT.SimpleTy != MVT::v8i16) 165 return 0; 166 if ((Subtarget->hasNEON())) { 167 return fastEmitInst_r(AArch64::CMEQv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 168 } 169 return 0; 170} 171 172unsigned fastEmit_AArch64ISD_CMEQz_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 173 if (RetVT.SimpleTy != MVT::v2i32) 174 return 0; 175 if ((Subtarget->hasNEON())) { 176 return fastEmitInst_r(AArch64::CMEQv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 177 } 178 return 0; 179} 180 181unsigned fastEmit_AArch64ISD_CMEQz_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 182 if (RetVT.SimpleTy != MVT::v4i32) 183 return 0; 184 if ((Subtarget->hasNEON())) { 185 return fastEmitInst_r(AArch64::CMEQv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 186 } 187 return 0; 188} 189 190unsigned fastEmit_AArch64ISD_CMEQz_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 191 if (RetVT.SimpleTy != MVT::v1i64) 192 return 0; 193 if ((Subtarget->hasNEON())) { 194 return fastEmitInst_r(AArch64::CMEQv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 195 } 196 return 0; 197} 198 199unsigned fastEmit_AArch64ISD_CMEQz_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 200 if (RetVT.SimpleTy != MVT::v2i64) 201 return 0; 202 if ((Subtarget->hasNEON())) { 203 return fastEmitInst_r(AArch64::CMEQv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 204 } 205 return 0; 206} 207 208unsigned fastEmit_AArch64ISD_CMEQz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 209 switch (VT.SimpleTy) { 210 case MVT::v8i8: return fastEmit_AArch64ISD_CMEQz_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 211 case MVT::v16i8: return fastEmit_AArch64ISD_CMEQz_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 212 case MVT::v4i16: return fastEmit_AArch64ISD_CMEQz_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 213 case MVT::v8i16: return fastEmit_AArch64ISD_CMEQz_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 214 case MVT::v2i32: return fastEmit_AArch64ISD_CMEQz_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 215 case MVT::v4i32: return fastEmit_AArch64ISD_CMEQz_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 216 case MVT::v1i64: return fastEmit_AArch64ISD_CMEQz_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 217 case MVT::v2i64: return fastEmit_AArch64ISD_CMEQz_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 218 default: return 0; 219 } 220} 221 222// FastEmit functions for AArch64ISD::CMGEz. 223 224unsigned fastEmit_AArch64ISD_CMGEz_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 225 if (RetVT.SimpleTy != MVT::v8i8) 226 return 0; 227 if ((Subtarget->hasNEON())) { 228 return fastEmitInst_r(AArch64::CMGEv8i8rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 229 } 230 return 0; 231} 232 233unsigned fastEmit_AArch64ISD_CMGEz_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 234 if (RetVT.SimpleTy != MVT::v16i8) 235 return 0; 236 if ((Subtarget->hasNEON())) { 237 return fastEmitInst_r(AArch64::CMGEv16i8rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 238 } 239 return 0; 240} 241 242unsigned fastEmit_AArch64ISD_CMGEz_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 243 if (RetVT.SimpleTy != MVT::v4i16) 244 return 0; 245 if ((Subtarget->hasNEON())) { 246 return fastEmitInst_r(AArch64::CMGEv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 247 } 248 return 0; 249} 250 251unsigned fastEmit_AArch64ISD_CMGEz_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 252 if (RetVT.SimpleTy != MVT::v8i16) 253 return 0; 254 if ((Subtarget->hasNEON())) { 255 return fastEmitInst_r(AArch64::CMGEv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 256 } 257 return 0; 258} 259 260unsigned fastEmit_AArch64ISD_CMGEz_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 261 if (RetVT.SimpleTy != MVT::v2i32) 262 return 0; 263 if ((Subtarget->hasNEON())) { 264 return fastEmitInst_r(AArch64::CMGEv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 265 } 266 return 0; 267} 268 269unsigned fastEmit_AArch64ISD_CMGEz_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 270 if (RetVT.SimpleTy != MVT::v4i32) 271 return 0; 272 if ((Subtarget->hasNEON())) { 273 return fastEmitInst_r(AArch64::CMGEv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 274 } 275 return 0; 276} 277 278unsigned fastEmit_AArch64ISD_CMGEz_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 279 if (RetVT.SimpleTy != MVT::v1i64) 280 return 0; 281 if ((Subtarget->hasNEON())) { 282 return fastEmitInst_r(AArch64::CMGEv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 283 } 284 return 0; 285} 286 287unsigned fastEmit_AArch64ISD_CMGEz_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 288 if (RetVT.SimpleTy != MVT::v2i64) 289 return 0; 290 if ((Subtarget->hasNEON())) { 291 return fastEmitInst_r(AArch64::CMGEv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 292 } 293 return 0; 294} 295 296unsigned fastEmit_AArch64ISD_CMGEz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 297 switch (VT.SimpleTy) { 298 case MVT::v8i8: return fastEmit_AArch64ISD_CMGEz_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 299 case MVT::v16i8: return fastEmit_AArch64ISD_CMGEz_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 300 case MVT::v4i16: return fastEmit_AArch64ISD_CMGEz_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 301 case MVT::v8i16: return fastEmit_AArch64ISD_CMGEz_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 302 case MVT::v2i32: return fastEmit_AArch64ISD_CMGEz_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 303 case MVT::v4i32: return fastEmit_AArch64ISD_CMGEz_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 304 case MVT::v1i64: return fastEmit_AArch64ISD_CMGEz_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 305 case MVT::v2i64: return fastEmit_AArch64ISD_CMGEz_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 306 default: return 0; 307 } 308} 309 310// FastEmit functions for AArch64ISD::CMGTz. 311 312unsigned fastEmit_AArch64ISD_CMGTz_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 313 if (RetVT.SimpleTy != MVT::v8i8) 314 return 0; 315 if ((Subtarget->hasNEON())) { 316 return fastEmitInst_r(AArch64::CMGTv8i8rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 317 } 318 return 0; 319} 320 321unsigned fastEmit_AArch64ISD_CMGTz_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 322 if (RetVT.SimpleTy != MVT::v16i8) 323 return 0; 324 if ((Subtarget->hasNEON())) { 325 return fastEmitInst_r(AArch64::CMGTv16i8rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 326 } 327 return 0; 328} 329 330unsigned fastEmit_AArch64ISD_CMGTz_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 331 if (RetVT.SimpleTy != MVT::v4i16) 332 return 0; 333 if ((Subtarget->hasNEON())) { 334 return fastEmitInst_r(AArch64::CMGTv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 335 } 336 return 0; 337} 338 339unsigned fastEmit_AArch64ISD_CMGTz_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 340 if (RetVT.SimpleTy != MVT::v8i16) 341 return 0; 342 if ((Subtarget->hasNEON())) { 343 return fastEmitInst_r(AArch64::CMGTv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 344 } 345 return 0; 346} 347 348unsigned fastEmit_AArch64ISD_CMGTz_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 349 if (RetVT.SimpleTy != MVT::v2i32) 350 return 0; 351 if ((Subtarget->hasNEON())) { 352 return fastEmitInst_r(AArch64::CMGTv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 353 } 354 return 0; 355} 356 357unsigned fastEmit_AArch64ISD_CMGTz_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 358 if (RetVT.SimpleTy != MVT::v4i32) 359 return 0; 360 if ((Subtarget->hasNEON())) { 361 return fastEmitInst_r(AArch64::CMGTv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 362 } 363 return 0; 364} 365 366unsigned fastEmit_AArch64ISD_CMGTz_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 367 if (RetVT.SimpleTy != MVT::v1i64) 368 return 0; 369 if ((Subtarget->hasNEON())) { 370 return fastEmitInst_r(AArch64::CMGTv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 371 } 372 return 0; 373} 374 375unsigned fastEmit_AArch64ISD_CMGTz_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 376 if (RetVT.SimpleTy != MVT::v2i64) 377 return 0; 378 if ((Subtarget->hasNEON())) { 379 return fastEmitInst_r(AArch64::CMGTv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 380 } 381 return 0; 382} 383 384unsigned fastEmit_AArch64ISD_CMGTz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 385 switch (VT.SimpleTy) { 386 case MVT::v8i8: return fastEmit_AArch64ISD_CMGTz_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 387 case MVT::v16i8: return fastEmit_AArch64ISD_CMGTz_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 388 case MVT::v4i16: return fastEmit_AArch64ISD_CMGTz_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 389 case MVT::v8i16: return fastEmit_AArch64ISD_CMGTz_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 390 case MVT::v2i32: return fastEmit_AArch64ISD_CMGTz_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 391 case MVT::v4i32: return fastEmit_AArch64ISD_CMGTz_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 392 case MVT::v1i64: return fastEmit_AArch64ISD_CMGTz_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 393 case MVT::v2i64: return fastEmit_AArch64ISD_CMGTz_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 394 default: return 0; 395 } 396} 397 398// FastEmit functions for AArch64ISD::CMLEz. 399 400unsigned fastEmit_AArch64ISD_CMLEz_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 401 if (RetVT.SimpleTy != MVT::v8i8) 402 return 0; 403 if ((Subtarget->hasNEON())) { 404 return fastEmitInst_r(AArch64::CMLEv8i8rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 405 } 406 return 0; 407} 408 409unsigned fastEmit_AArch64ISD_CMLEz_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 410 if (RetVT.SimpleTy != MVT::v16i8) 411 return 0; 412 if ((Subtarget->hasNEON())) { 413 return fastEmitInst_r(AArch64::CMLEv16i8rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 414 } 415 return 0; 416} 417 418unsigned fastEmit_AArch64ISD_CMLEz_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 419 if (RetVT.SimpleTy != MVT::v4i16) 420 return 0; 421 if ((Subtarget->hasNEON())) { 422 return fastEmitInst_r(AArch64::CMLEv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 423 } 424 return 0; 425} 426 427unsigned fastEmit_AArch64ISD_CMLEz_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 428 if (RetVT.SimpleTy != MVT::v8i16) 429 return 0; 430 if ((Subtarget->hasNEON())) { 431 return fastEmitInst_r(AArch64::CMLEv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 432 } 433 return 0; 434} 435 436unsigned fastEmit_AArch64ISD_CMLEz_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 437 if (RetVT.SimpleTy != MVT::v2i32) 438 return 0; 439 if ((Subtarget->hasNEON())) { 440 return fastEmitInst_r(AArch64::CMLEv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 441 } 442 return 0; 443} 444 445unsigned fastEmit_AArch64ISD_CMLEz_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 446 if (RetVT.SimpleTy != MVT::v4i32) 447 return 0; 448 if ((Subtarget->hasNEON())) { 449 return fastEmitInst_r(AArch64::CMLEv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 450 } 451 return 0; 452} 453 454unsigned fastEmit_AArch64ISD_CMLEz_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 455 if (RetVT.SimpleTy != MVT::v1i64) 456 return 0; 457 if ((Subtarget->hasNEON())) { 458 return fastEmitInst_r(AArch64::CMLEv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 459 } 460 return 0; 461} 462 463unsigned fastEmit_AArch64ISD_CMLEz_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 464 if (RetVT.SimpleTy != MVT::v2i64) 465 return 0; 466 if ((Subtarget->hasNEON())) { 467 return fastEmitInst_r(AArch64::CMLEv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 468 } 469 return 0; 470} 471 472unsigned fastEmit_AArch64ISD_CMLEz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 473 switch (VT.SimpleTy) { 474 case MVT::v8i8: return fastEmit_AArch64ISD_CMLEz_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 475 case MVT::v16i8: return fastEmit_AArch64ISD_CMLEz_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 476 case MVT::v4i16: return fastEmit_AArch64ISD_CMLEz_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 477 case MVT::v8i16: return fastEmit_AArch64ISD_CMLEz_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 478 case MVT::v2i32: return fastEmit_AArch64ISD_CMLEz_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 479 case MVT::v4i32: return fastEmit_AArch64ISD_CMLEz_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 480 case MVT::v1i64: return fastEmit_AArch64ISD_CMLEz_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 481 case MVT::v2i64: return fastEmit_AArch64ISD_CMLEz_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 482 default: return 0; 483 } 484} 485 486// FastEmit functions for AArch64ISD::CMLTz. 487 488unsigned fastEmit_AArch64ISD_CMLTz_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 489 if (RetVT.SimpleTy != MVT::v8i8) 490 return 0; 491 if ((Subtarget->hasNEON())) { 492 return fastEmitInst_r(AArch64::CMLTv8i8rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 493 } 494 return 0; 495} 496 497unsigned fastEmit_AArch64ISD_CMLTz_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 498 if (RetVT.SimpleTy != MVT::v16i8) 499 return 0; 500 if ((Subtarget->hasNEON())) { 501 return fastEmitInst_r(AArch64::CMLTv16i8rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 502 } 503 return 0; 504} 505 506unsigned fastEmit_AArch64ISD_CMLTz_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 507 if (RetVT.SimpleTy != MVT::v4i16) 508 return 0; 509 if ((Subtarget->hasNEON())) { 510 return fastEmitInst_r(AArch64::CMLTv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 511 } 512 return 0; 513} 514 515unsigned fastEmit_AArch64ISD_CMLTz_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 516 if (RetVT.SimpleTy != MVT::v8i16) 517 return 0; 518 if ((Subtarget->hasNEON())) { 519 return fastEmitInst_r(AArch64::CMLTv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 520 } 521 return 0; 522} 523 524unsigned fastEmit_AArch64ISD_CMLTz_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 525 if (RetVT.SimpleTy != MVT::v2i32) 526 return 0; 527 if ((Subtarget->hasNEON())) { 528 return fastEmitInst_r(AArch64::CMLTv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 529 } 530 return 0; 531} 532 533unsigned fastEmit_AArch64ISD_CMLTz_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 534 if (RetVT.SimpleTy != MVT::v4i32) 535 return 0; 536 if ((Subtarget->hasNEON())) { 537 return fastEmitInst_r(AArch64::CMLTv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 538 } 539 return 0; 540} 541 542unsigned fastEmit_AArch64ISD_CMLTz_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 543 if (RetVT.SimpleTy != MVT::v1i64) 544 return 0; 545 if ((Subtarget->hasNEON())) { 546 return fastEmitInst_r(AArch64::CMLTv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 547 } 548 return 0; 549} 550 551unsigned fastEmit_AArch64ISD_CMLTz_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 552 if (RetVT.SimpleTy != MVT::v2i64) 553 return 0; 554 if ((Subtarget->hasNEON())) { 555 return fastEmitInst_r(AArch64::CMLTv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 556 } 557 return 0; 558} 559 560unsigned fastEmit_AArch64ISD_CMLTz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 561 switch (VT.SimpleTy) { 562 case MVT::v8i8: return fastEmit_AArch64ISD_CMLTz_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 563 case MVT::v16i8: return fastEmit_AArch64ISD_CMLTz_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 564 case MVT::v4i16: return fastEmit_AArch64ISD_CMLTz_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 565 case MVT::v8i16: return fastEmit_AArch64ISD_CMLTz_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 566 case MVT::v2i32: return fastEmit_AArch64ISD_CMLTz_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 567 case MVT::v4i32: return fastEmit_AArch64ISD_CMLTz_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 568 case MVT::v1i64: return fastEmit_AArch64ISD_CMLTz_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 569 case MVT::v2i64: return fastEmit_AArch64ISD_CMLTz_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 570 default: return 0; 571 } 572} 573 574// FastEmit functions for AArch64ISD::DUP. 575 576unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 577 if ((Subtarget->hasNEON())) { 578 return fastEmitInst_r(AArch64::DUPv8i8gpr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 579 } 580 return 0; 581} 582 583unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 584 if ((Subtarget->hasNEON())) { 585 return fastEmitInst_r(AArch64::DUPv16i8gpr, &AArch64::FPR128RegClass, Op0, Op0IsKill); 586 } 587 return 0; 588} 589 590unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 591 if ((Subtarget->hasNEON())) { 592 return fastEmitInst_r(AArch64::DUPv4i16gpr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 593 } 594 return 0; 595} 596 597unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 598 if ((Subtarget->hasNEON())) { 599 return fastEmitInst_r(AArch64::DUPv8i16gpr, &AArch64::FPR128RegClass, Op0, Op0IsKill); 600 } 601 return 0; 602} 603 604unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 605 if ((Subtarget->hasNEON())) { 606 return fastEmitInst_r(AArch64::DUPv2i32gpr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 607 } 608 return 0; 609} 610 611unsigned fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 612 if ((Subtarget->hasNEON())) { 613 return fastEmitInst_r(AArch64::DUPv4i32gpr, &AArch64::FPR128RegClass, Op0, Op0IsKill); 614 } 615 return 0; 616} 617 618unsigned fastEmit_AArch64ISD_DUP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 619switch (RetVT.SimpleTy) { 620 case MVT::v8i8: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v8i8_r(Op0, Op0IsKill); 621 case MVT::v16i8: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v16i8_r(Op0, Op0IsKill); 622 case MVT::v4i16: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v4i16_r(Op0, Op0IsKill); 623 case MVT::v8i16: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v8i16_r(Op0, Op0IsKill); 624 case MVT::v2i32: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v2i32_r(Op0, Op0IsKill); 625 case MVT::v4i32: return fastEmit_AArch64ISD_DUP_MVT_i32_MVT_v4i32_r(Op0, Op0IsKill); 626 default: return 0; 627} 628} 629 630unsigned fastEmit_AArch64ISD_DUP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 631 if (RetVT.SimpleTy != MVT::v2i64) 632 return 0; 633 if ((Subtarget->hasNEON())) { 634 return fastEmitInst_r(AArch64::DUPv2i64gpr, &AArch64::FPR128RegClass, Op0, Op0IsKill); 635 } 636 return 0; 637} 638 639unsigned fastEmit_AArch64ISD_DUP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 640 switch (VT.SimpleTy) { 641 case MVT::i32: return fastEmit_AArch64ISD_DUP_MVT_i32_r(RetVT, Op0, Op0IsKill); 642 case MVT::i64: return fastEmit_AArch64ISD_DUP_MVT_i64_r(RetVT, Op0, Op0IsKill); 643 default: return 0; 644 } 645} 646 647// FastEmit functions for AArch64ISD::FCMEQz. 648 649unsigned fastEmit_AArch64ISD_FCMEQz_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 650 if (RetVT.SimpleTy != MVT::v4i16) 651 return 0; 652 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 653 return fastEmitInst_r(AArch64::FCMEQv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 654 } 655 return 0; 656} 657 658unsigned fastEmit_AArch64ISD_FCMEQz_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 659 if (RetVT.SimpleTy != MVT::v8i16) 660 return 0; 661 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 662 return fastEmitInst_r(AArch64::FCMEQv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 663 } 664 return 0; 665} 666 667unsigned fastEmit_AArch64ISD_FCMEQz_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 668 if (RetVT.SimpleTy != MVT::v2i32) 669 return 0; 670 if ((Subtarget->hasNEON())) { 671 return fastEmitInst_r(AArch64::FCMEQv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 672 } 673 return 0; 674} 675 676unsigned fastEmit_AArch64ISD_FCMEQz_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 677 if (RetVT.SimpleTy != MVT::v4i32) 678 return 0; 679 if ((Subtarget->hasNEON())) { 680 return fastEmitInst_r(AArch64::FCMEQv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 681 } 682 return 0; 683} 684 685unsigned fastEmit_AArch64ISD_FCMEQz_MVT_v1f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 686 if (RetVT.SimpleTy != MVT::v1i64) 687 return 0; 688 if ((Subtarget->hasNEON())) { 689 return fastEmitInst_r(AArch64::FCMEQv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 690 } 691 return 0; 692} 693 694unsigned fastEmit_AArch64ISD_FCMEQz_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 695 if (RetVT.SimpleTy != MVT::v2i64) 696 return 0; 697 if ((Subtarget->hasNEON())) { 698 return fastEmitInst_r(AArch64::FCMEQv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 699 } 700 return 0; 701} 702 703unsigned fastEmit_AArch64ISD_FCMEQz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 704 switch (VT.SimpleTy) { 705 case MVT::v4f16: return fastEmit_AArch64ISD_FCMEQz_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 706 case MVT::v8f16: return fastEmit_AArch64ISD_FCMEQz_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 707 case MVT::v2f32: return fastEmit_AArch64ISD_FCMEQz_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 708 case MVT::v4f32: return fastEmit_AArch64ISD_FCMEQz_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 709 case MVT::v1f64: return fastEmit_AArch64ISD_FCMEQz_MVT_v1f64_r(RetVT, Op0, Op0IsKill); 710 case MVT::v2f64: return fastEmit_AArch64ISD_FCMEQz_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 711 default: return 0; 712 } 713} 714 715// FastEmit functions for AArch64ISD::FCMGEz. 716 717unsigned fastEmit_AArch64ISD_FCMGEz_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 718 if (RetVT.SimpleTy != MVT::v4i16) 719 return 0; 720 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 721 return fastEmitInst_r(AArch64::FCMGEv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 722 } 723 return 0; 724} 725 726unsigned fastEmit_AArch64ISD_FCMGEz_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 727 if (RetVT.SimpleTy != MVT::v8i16) 728 return 0; 729 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 730 return fastEmitInst_r(AArch64::FCMGEv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 731 } 732 return 0; 733} 734 735unsigned fastEmit_AArch64ISD_FCMGEz_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 736 if (RetVT.SimpleTy != MVT::v2i32) 737 return 0; 738 if ((Subtarget->hasNEON())) { 739 return fastEmitInst_r(AArch64::FCMGEv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 740 } 741 return 0; 742} 743 744unsigned fastEmit_AArch64ISD_FCMGEz_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 745 if (RetVT.SimpleTy != MVT::v4i32) 746 return 0; 747 if ((Subtarget->hasNEON())) { 748 return fastEmitInst_r(AArch64::FCMGEv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 749 } 750 return 0; 751} 752 753unsigned fastEmit_AArch64ISD_FCMGEz_MVT_v1f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 754 if (RetVT.SimpleTy != MVT::v1i64) 755 return 0; 756 if ((Subtarget->hasNEON())) { 757 return fastEmitInst_r(AArch64::FCMGEv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 758 } 759 return 0; 760} 761 762unsigned fastEmit_AArch64ISD_FCMGEz_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 763 if (RetVT.SimpleTy != MVT::v2i64) 764 return 0; 765 if ((Subtarget->hasNEON())) { 766 return fastEmitInst_r(AArch64::FCMGEv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 767 } 768 return 0; 769} 770 771unsigned fastEmit_AArch64ISD_FCMGEz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 772 switch (VT.SimpleTy) { 773 case MVT::v4f16: return fastEmit_AArch64ISD_FCMGEz_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 774 case MVT::v8f16: return fastEmit_AArch64ISD_FCMGEz_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 775 case MVT::v2f32: return fastEmit_AArch64ISD_FCMGEz_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 776 case MVT::v4f32: return fastEmit_AArch64ISD_FCMGEz_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 777 case MVT::v1f64: return fastEmit_AArch64ISD_FCMGEz_MVT_v1f64_r(RetVT, Op0, Op0IsKill); 778 case MVT::v2f64: return fastEmit_AArch64ISD_FCMGEz_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 779 default: return 0; 780 } 781} 782 783// FastEmit functions for AArch64ISD::FCMGTz. 784 785unsigned fastEmit_AArch64ISD_FCMGTz_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 786 if (RetVT.SimpleTy != MVT::v4i16) 787 return 0; 788 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 789 return fastEmitInst_r(AArch64::FCMGTv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 790 } 791 return 0; 792} 793 794unsigned fastEmit_AArch64ISD_FCMGTz_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 795 if (RetVT.SimpleTy != MVT::v8i16) 796 return 0; 797 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 798 return fastEmitInst_r(AArch64::FCMGTv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 799 } 800 return 0; 801} 802 803unsigned fastEmit_AArch64ISD_FCMGTz_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 804 if (RetVT.SimpleTy != MVT::v2i32) 805 return 0; 806 if ((Subtarget->hasNEON())) { 807 return fastEmitInst_r(AArch64::FCMGTv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 808 } 809 return 0; 810} 811 812unsigned fastEmit_AArch64ISD_FCMGTz_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 813 if (RetVT.SimpleTy != MVT::v4i32) 814 return 0; 815 if ((Subtarget->hasNEON())) { 816 return fastEmitInst_r(AArch64::FCMGTv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 817 } 818 return 0; 819} 820 821unsigned fastEmit_AArch64ISD_FCMGTz_MVT_v1f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 822 if (RetVT.SimpleTy != MVT::v1i64) 823 return 0; 824 if ((Subtarget->hasNEON())) { 825 return fastEmitInst_r(AArch64::FCMGTv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 826 } 827 return 0; 828} 829 830unsigned fastEmit_AArch64ISD_FCMGTz_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 831 if (RetVT.SimpleTy != MVT::v2i64) 832 return 0; 833 if ((Subtarget->hasNEON())) { 834 return fastEmitInst_r(AArch64::FCMGTv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 835 } 836 return 0; 837} 838 839unsigned fastEmit_AArch64ISD_FCMGTz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 840 switch (VT.SimpleTy) { 841 case MVT::v4f16: return fastEmit_AArch64ISD_FCMGTz_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 842 case MVT::v8f16: return fastEmit_AArch64ISD_FCMGTz_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 843 case MVT::v2f32: return fastEmit_AArch64ISD_FCMGTz_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 844 case MVT::v4f32: return fastEmit_AArch64ISD_FCMGTz_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 845 case MVT::v1f64: return fastEmit_AArch64ISD_FCMGTz_MVT_v1f64_r(RetVT, Op0, Op0IsKill); 846 case MVT::v2f64: return fastEmit_AArch64ISD_FCMGTz_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 847 default: return 0; 848 } 849} 850 851// FastEmit functions for AArch64ISD::FCMLEz. 852 853unsigned fastEmit_AArch64ISD_FCMLEz_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 854 if (RetVT.SimpleTy != MVT::v4i16) 855 return 0; 856 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 857 return fastEmitInst_r(AArch64::FCMLEv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 858 } 859 return 0; 860} 861 862unsigned fastEmit_AArch64ISD_FCMLEz_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 863 if (RetVT.SimpleTy != MVT::v8i16) 864 return 0; 865 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 866 return fastEmitInst_r(AArch64::FCMLEv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 867 } 868 return 0; 869} 870 871unsigned fastEmit_AArch64ISD_FCMLEz_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 872 if (RetVT.SimpleTy != MVT::v2i32) 873 return 0; 874 if ((Subtarget->hasNEON())) { 875 return fastEmitInst_r(AArch64::FCMLEv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 876 } 877 return 0; 878} 879 880unsigned fastEmit_AArch64ISD_FCMLEz_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 881 if (RetVT.SimpleTy != MVT::v4i32) 882 return 0; 883 if ((Subtarget->hasNEON())) { 884 return fastEmitInst_r(AArch64::FCMLEv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 885 } 886 return 0; 887} 888 889unsigned fastEmit_AArch64ISD_FCMLEz_MVT_v1f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 890 if (RetVT.SimpleTy != MVT::v1i64) 891 return 0; 892 if ((Subtarget->hasNEON())) { 893 return fastEmitInst_r(AArch64::FCMLEv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 894 } 895 return 0; 896} 897 898unsigned fastEmit_AArch64ISD_FCMLEz_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 899 if (RetVT.SimpleTy != MVT::v2i64) 900 return 0; 901 if ((Subtarget->hasNEON())) { 902 return fastEmitInst_r(AArch64::FCMLEv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 903 } 904 return 0; 905} 906 907unsigned fastEmit_AArch64ISD_FCMLEz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 908 switch (VT.SimpleTy) { 909 case MVT::v4f16: return fastEmit_AArch64ISD_FCMLEz_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 910 case MVT::v8f16: return fastEmit_AArch64ISD_FCMLEz_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 911 case MVT::v2f32: return fastEmit_AArch64ISD_FCMLEz_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 912 case MVT::v4f32: return fastEmit_AArch64ISD_FCMLEz_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 913 case MVT::v1f64: return fastEmit_AArch64ISD_FCMLEz_MVT_v1f64_r(RetVT, Op0, Op0IsKill); 914 case MVT::v2f64: return fastEmit_AArch64ISD_FCMLEz_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 915 default: return 0; 916 } 917} 918 919// FastEmit functions for AArch64ISD::FCMLTz. 920 921unsigned fastEmit_AArch64ISD_FCMLTz_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 922 if (RetVT.SimpleTy != MVT::v4i16) 923 return 0; 924 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 925 return fastEmitInst_r(AArch64::FCMLTv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 926 } 927 return 0; 928} 929 930unsigned fastEmit_AArch64ISD_FCMLTz_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 931 if (RetVT.SimpleTy != MVT::v8i16) 932 return 0; 933 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 934 return fastEmitInst_r(AArch64::FCMLTv8i16rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 935 } 936 return 0; 937} 938 939unsigned fastEmit_AArch64ISD_FCMLTz_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 940 if (RetVT.SimpleTy != MVT::v2i32) 941 return 0; 942 if ((Subtarget->hasNEON())) { 943 return fastEmitInst_r(AArch64::FCMLTv2i32rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 944 } 945 return 0; 946} 947 948unsigned fastEmit_AArch64ISD_FCMLTz_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 949 if (RetVT.SimpleTy != MVT::v4i32) 950 return 0; 951 if ((Subtarget->hasNEON())) { 952 return fastEmitInst_r(AArch64::FCMLTv4i32rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 953 } 954 return 0; 955} 956 957unsigned fastEmit_AArch64ISD_FCMLTz_MVT_v1f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 958 if (RetVT.SimpleTy != MVT::v1i64) 959 return 0; 960 if ((Subtarget->hasNEON())) { 961 return fastEmitInst_r(AArch64::FCMLTv1i64rz, &AArch64::FPR64RegClass, Op0, Op0IsKill); 962 } 963 return 0; 964} 965 966unsigned fastEmit_AArch64ISD_FCMLTz_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 967 if (RetVT.SimpleTy != MVT::v2i64) 968 return 0; 969 if ((Subtarget->hasNEON())) { 970 return fastEmitInst_r(AArch64::FCMLTv2i64rz, &AArch64::FPR128RegClass, Op0, Op0IsKill); 971 } 972 return 0; 973} 974 975unsigned fastEmit_AArch64ISD_FCMLTz_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 976 switch (VT.SimpleTy) { 977 case MVT::v4f16: return fastEmit_AArch64ISD_FCMLTz_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 978 case MVT::v8f16: return fastEmit_AArch64ISD_FCMLTz_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 979 case MVT::v2f32: return fastEmit_AArch64ISD_FCMLTz_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 980 case MVT::v4f32: return fastEmit_AArch64ISD_FCMLTz_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 981 case MVT::v1f64: return fastEmit_AArch64ISD_FCMLTz_MVT_v1f64_r(RetVT, Op0, Op0IsKill); 982 case MVT::v2f64: return fastEmit_AArch64ISD_FCMLTz_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 983 default: return 0; 984 } 985} 986 987// FastEmit functions for AArch64ISD::FRECPE. 988 989unsigned fastEmit_AArch64ISD_FRECPE_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 990 if (RetVT.SimpleTy != MVT::f32) 991 return 0; 992 return fastEmitInst_r(AArch64::FRECPEv1i32, &AArch64::FPR32RegClass, Op0, Op0IsKill); 993} 994 995unsigned fastEmit_AArch64ISD_FRECPE_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 996 if (RetVT.SimpleTy != MVT::f64) 997 return 0; 998 return fastEmitInst_r(AArch64::FRECPEv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill); 999} 1000 1001unsigned fastEmit_AArch64ISD_FRECPE_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1002 if (RetVT.SimpleTy != MVT::v2f32) 1003 return 0; 1004 return fastEmitInst_r(AArch64::FRECPEv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1005} 1006 1007unsigned fastEmit_AArch64ISD_FRECPE_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1008 if (RetVT.SimpleTy != MVT::v4f32) 1009 return 0; 1010 return fastEmitInst_r(AArch64::FRECPEv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1011} 1012 1013unsigned fastEmit_AArch64ISD_FRECPE_MVT_v1f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1014 if (RetVT.SimpleTy != MVT::v1f64) 1015 return 0; 1016 return fastEmitInst_r(AArch64::FRECPEv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1017} 1018 1019unsigned fastEmit_AArch64ISD_FRECPE_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1020 if (RetVT.SimpleTy != MVT::v2f64) 1021 return 0; 1022 return fastEmitInst_r(AArch64::FRECPEv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1023} 1024 1025unsigned fastEmit_AArch64ISD_FRECPE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1026 switch (VT.SimpleTy) { 1027 case MVT::f32: return fastEmit_AArch64ISD_FRECPE_MVT_f32_r(RetVT, Op0, Op0IsKill); 1028 case MVT::f64: return fastEmit_AArch64ISD_FRECPE_MVT_f64_r(RetVT, Op0, Op0IsKill); 1029 case MVT::v2f32: return fastEmit_AArch64ISD_FRECPE_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 1030 case MVT::v4f32: return fastEmit_AArch64ISD_FRECPE_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 1031 case MVT::v1f64: return fastEmit_AArch64ISD_FRECPE_MVT_v1f64_r(RetVT, Op0, Op0IsKill); 1032 case MVT::v2f64: return fastEmit_AArch64ISD_FRECPE_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 1033 default: return 0; 1034 } 1035} 1036 1037// FastEmit functions for AArch64ISD::FRSQRTE. 1038 1039unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1040 if (RetVT.SimpleTy != MVT::f32) 1041 return 0; 1042 return fastEmitInst_r(AArch64::FRSQRTEv1i32, &AArch64::FPR32RegClass, Op0, Op0IsKill); 1043} 1044 1045unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1046 if (RetVT.SimpleTy != MVT::f64) 1047 return 0; 1048 return fastEmitInst_r(AArch64::FRSQRTEv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1049} 1050 1051unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1052 if (RetVT.SimpleTy != MVT::v2f32) 1053 return 0; 1054 return fastEmitInst_r(AArch64::FRSQRTEv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1055} 1056 1057unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1058 if (RetVT.SimpleTy != MVT::v4f32) 1059 return 0; 1060 return fastEmitInst_r(AArch64::FRSQRTEv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1061} 1062 1063unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_v1f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1064 if (RetVT.SimpleTy != MVT::v1f64) 1065 return 0; 1066 return fastEmitInst_r(AArch64::FRSQRTEv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1067} 1068 1069unsigned fastEmit_AArch64ISD_FRSQRTE_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1070 if (RetVT.SimpleTy != MVT::v2f64) 1071 return 0; 1072 return fastEmitInst_r(AArch64::FRSQRTEv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1073} 1074 1075unsigned fastEmit_AArch64ISD_FRSQRTE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1076 switch (VT.SimpleTy) { 1077 case MVT::f32: return fastEmit_AArch64ISD_FRSQRTE_MVT_f32_r(RetVT, Op0, Op0IsKill); 1078 case MVT::f64: return fastEmit_AArch64ISD_FRSQRTE_MVT_f64_r(RetVT, Op0, Op0IsKill); 1079 case MVT::v2f32: return fastEmit_AArch64ISD_FRSQRTE_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 1080 case MVT::v4f32: return fastEmit_AArch64ISD_FRSQRTE_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 1081 case MVT::v1f64: return fastEmit_AArch64ISD_FRSQRTE_MVT_v1f64_r(RetVT, Op0, Op0IsKill); 1082 case MVT::v2f64: return fastEmit_AArch64ISD_FRSQRTE_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 1083 default: return 0; 1084 } 1085} 1086 1087// FastEmit functions for AArch64ISD::NEG. 1088 1089unsigned fastEmit_AArch64ISD_NEG_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1090 if (RetVT.SimpleTy != MVT::v8i8) 1091 return 0; 1092 return fastEmitInst_r(AArch64::NEGv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1093} 1094 1095unsigned fastEmit_AArch64ISD_NEG_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1096 if (RetVT.SimpleTy != MVT::v16i8) 1097 return 0; 1098 return fastEmitInst_r(AArch64::NEGv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1099} 1100 1101unsigned fastEmit_AArch64ISD_NEG_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1102 if (RetVT.SimpleTy != MVT::v4i16) 1103 return 0; 1104 return fastEmitInst_r(AArch64::NEGv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1105} 1106 1107unsigned fastEmit_AArch64ISD_NEG_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1108 if (RetVT.SimpleTy != MVT::v8i16) 1109 return 0; 1110 return fastEmitInst_r(AArch64::NEGv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1111} 1112 1113unsigned fastEmit_AArch64ISD_NEG_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1114 if (RetVT.SimpleTy != MVT::v2i32) 1115 return 0; 1116 return fastEmitInst_r(AArch64::NEGv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1117} 1118 1119unsigned fastEmit_AArch64ISD_NEG_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1120 if (RetVT.SimpleTy != MVT::v4i32) 1121 return 0; 1122 return fastEmitInst_r(AArch64::NEGv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1123} 1124 1125unsigned fastEmit_AArch64ISD_NEG_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1126 if (RetVT.SimpleTy != MVT::v1i64) 1127 return 0; 1128 return fastEmitInst_r(AArch64::NEGv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1129} 1130 1131unsigned fastEmit_AArch64ISD_NEG_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1132 if (RetVT.SimpleTy != MVT::v2i64) 1133 return 0; 1134 return fastEmitInst_r(AArch64::NEGv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1135} 1136 1137unsigned fastEmit_AArch64ISD_NEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1138 switch (VT.SimpleTy) { 1139 case MVT::v8i8: return fastEmit_AArch64ISD_NEG_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1140 case MVT::v16i8: return fastEmit_AArch64ISD_NEG_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1141 case MVT::v4i16: return fastEmit_AArch64ISD_NEG_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 1142 case MVT::v8i16: return fastEmit_AArch64ISD_NEG_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1143 case MVT::v2i32: return fastEmit_AArch64ISD_NEG_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 1144 case MVT::v4i32: return fastEmit_AArch64ISD_NEG_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 1145 case MVT::v1i64: return fastEmit_AArch64ISD_NEG_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 1146 case MVT::v2i64: return fastEmit_AArch64ISD_NEG_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 1147 default: return 0; 1148 } 1149} 1150 1151// FastEmit functions for AArch64ISD::NOT. 1152 1153unsigned fastEmit_AArch64ISD_NOT_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1154 if (RetVT.SimpleTy != MVT::v8i8) 1155 return 0; 1156 return fastEmitInst_r(AArch64::NOTv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1157} 1158 1159unsigned fastEmit_AArch64ISD_NOT_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1160 if (RetVT.SimpleTy != MVT::v16i8) 1161 return 0; 1162 return fastEmitInst_r(AArch64::NOTv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1163} 1164 1165unsigned fastEmit_AArch64ISD_NOT_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1166 if (RetVT.SimpleTy != MVT::v4i16) 1167 return 0; 1168 return fastEmitInst_r(AArch64::NOTv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1169} 1170 1171unsigned fastEmit_AArch64ISD_NOT_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1172 if (RetVT.SimpleTy != MVT::v8i16) 1173 return 0; 1174 return fastEmitInst_r(AArch64::NOTv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1175} 1176 1177unsigned fastEmit_AArch64ISD_NOT_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1178 if (RetVT.SimpleTy != MVT::v2i32) 1179 return 0; 1180 return fastEmitInst_r(AArch64::NOTv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1181} 1182 1183unsigned fastEmit_AArch64ISD_NOT_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1184 if (RetVT.SimpleTy != MVT::v4i32) 1185 return 0; 1186 return fastEmitInst_r(AArch64::NOTv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1187} 1188 1189unsigned fastEmit_AArch64ISD_NOT_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1190 if (RetVT.SimpleTy != MVT::v1i64) 1191 return 0; 1192 return fastEmitInst_r(AArch64::NOTv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1193} 1194 1195unsigned fastEmit_AArch64ISD_NOT_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1196 if (RetVT.SimpleTy != MVT::v2i64) 1197 return 0; 1198 return fastEmitInst_r(AArch64::NOTv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1199} 1200 1201unsigned fastEmit_AArch64ISD_NOT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1202 switch (VT.SimpleTy) { 1203 case MVT::v8i8: return fastEmit_AArch64ISD_NOT_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1204 case MVT::v16i8: return fastEmit_AArch64ISD_NOT_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1205 case MVT::v4i16: return fastEmit_AArch64ISD_NOT_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 1206 case MVT::v8i16: return fastEmit_AArch64ISD_NOT_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1207 case MVT::v2i32: return fastEmit_AArch64ISD_NOT_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 1208 case MVT::v4i32: return fastEmit_AArch64ISD_NOT_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 1209 case MVT::v1i64: return fastEmit_AArch64ISD_NOT_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 1210 case MVT::v2i64: return fastEmit_AArch64ISD_NOT_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 1211 default: return 0; 1212 } 1213} 1214 1215// FastEmit functions for AArch64ISD::REV16. 1216 1217unsigned fastEmit_AArch64ISD_REV16_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1218 if (RetVT.SimpleTy != MVT::v8i8) 1219 return 0; 1220 if ((Subtarget->hasNEON())) { 1221 return fastEmitInst_r(AArch64::REV16v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1222 } 1223 return 0; 1224} 1225 1226unsigned fastEmit_AArch64ISD_REV16_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1227 if (RetVT.SimpleTy != MVT::v16i8) 1228 return 0; 1229 if ((Subtarget->hasNEON())) { 1230 return fastEmitInst_r(AArch64::REV16v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1231 } 1232 return 0; 1233} 1234 1235unsigned fastEmit_AArch64ISD_REV16_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1236 switch (VT.SimpleTy) { 1237 case MVT::v8i8: return fastEmit_AArch64ISD_REV16_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1238 case MVT::v16i8: return fastEmit_AArch64ISD_REV16_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1239 default: return 0; 1240 } 1241} 1242 1243// FastEmit functions for AArch64ISD::REV32. 1244 1245unsigned fastEmit_AArch64ISD_REV32_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1246 if (RetVT.SimpleTy != MVT::v8i8) 1247 return 0; 1248 if ((Subtarget->hasNEON())) { 1249 return fastEmitInst_r(AArch64::REV32v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1250 } 1251 return 0; 1252} 1253 1254unsigned fastEmit_AArch64ISD_REV32_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1255 if (RetVT.SimpleTy != MVT::v16i8) 1256 return 0; 1257 if ((Subtarget->hasNEON())) { 1258 return fastEmitInst_r(AArch64::REV32v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1259 } 1260 return 0; 1261} 1262 1263unsigned fastEmit_AArch64ISD_REV32_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1264 if (RetVT.SimpleTy != MVT::v4i16) 1265 return 0; 1266 if ((Subtarget->hasNEON())) { 1267 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1268 } 1269 return 0; 1270} 1271 1272unsigned fastEmit_AArch64ISD_REV32_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1273 if (RetVT.SimpleTy != MVT::v8i16) 1274 return 0; 1275 if ((Subtarget->hasNEON())) { 1276 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1277 } 1278 return 0; 1279} 1280 1281unsigned fastEmit_AArch64ISD_REV32_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1282 if (RetVT.SimpleTy != MVT::v4f16) 1283 return 0; 1284 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1285} 1286 1287unsigned fastEmit_AArch64ISD_REV32_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1288 if (RetVT.SimpleTy != MVT::v8f16) 1289 return 0; 1290 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1291} 1292 1293unsigned fastEmit_AArch64ISD_REV32_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1294 switch (VT.SimpleTy) { 1295 case MVT::v8i8: return fastEmit_AArch64ISD_REV32_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1296 case MVT::v16i8: return fastEmit_AArch64ISD_REV32_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1297 case MVT::v4i16: return fastEmit_AArch64ISD_REV32_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 1298 case MVT::v8i16: return fastEmit_AArch64ISD_REV32_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1299 case MVT::v4f16: return fastEmit_AArch64ISD_REV32_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 1300 case MVT::v8f16: return fastEmit_AArch64ISD_REV32_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 1301 default: return 0; 1302 } 1303} 1304 1305// FastEmit functions for AArch64ISD::REV64. 1306 1307unsigned fastEmit_AArch64ISD_REV64_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1308 if (RetVT.SimpleTy != MVT::v8i8) 1309 return 0; 1310 if ((Subtarget->hasNEON())) { 1311 return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1312 } 1313 return 0; 1314} 1315 1316unsigned fastEmit_AArch64ISD_REV64_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1317 if (RetVT.SimpleTy != MVT::v16i8) 1318 return 0; 1319 if ((Subtarget->hasNEON())) { 1320 return fastEmitInst_r(AArch64::REV64v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1321 } 1322 return 0; 1323} 1324 1325unsigned fastEmit_AArch64ISD_REV64_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1326 if (RetVT.SimpleTy != MVT::v4i16) 1327 return 0; 1328 if ((Subtarget->hasNEON())) { 1329 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1330 } 1331 return 0; 1332} 1333 1334unsigned fastEmit_AArch64ISD_REV64_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1335 if (RetVT.SimpleTy != MVT::v8i16) 1336 return 0; 1337 if ((Subtarget->hasNEON())) { 1338 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1339 } 1340 return 0; 1341} 1342 1343unsigned fastEmit_AArch64ISD_REV64_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1344 if (RetVT.SimpleTy != MVT::v2i32) 1345 return 0; 1346 if ((Subtarget->hasNEON())) { 1347 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1348 } 1349 return 0; 1350} 1351 1352unsigned fastEmit_AArch64ISD_REV64_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1353 if (RetVT.SimpleTy != MVT::v4i32) 1354 return 0; 1355 if ((Subtarget->hasNEON())) { 1356 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1357 } 1358 return 0; 1359} 1360 1361unsigned fastEmit_AArch64ISD_REV64_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1362 if (RetVT.SimpleTy != MVT::v4f16) 1363 return 0; 1364 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1365} 1366 1367unsigned fastEmit_AArch64ISD_REV64_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1368 if (RetVT.SimpleTy != MVT::v8f16) 1369 return 0; 1370 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1371} 1372 1373unsigned fastEmit_AArch64ISD_REV64_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1374 if (RetVT.SimpleTy != MVT::v2f32) 1375 return 0; 1376 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1377} 1378 1379unsigned fastEmit_AArch64ISD_REV64_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1380 if (RetVT.SimpleTy != MVT::v4f32) 1381 return 0; 1382 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1383} 1384 1385unsigned fastEmit_AArch64ISD_REV64_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1386 switch (VT.SimpleTy) { 1387 case MVT::v8i8: return fastEmit_AArch64ISD_REV64_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1388 case MVT::v16i8: return fastEmit_AArch64ISD_REV64_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1389 case MVT::v4i16: return fastEmit_AArch64ISD_REV64_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 1390 case MVT::v8i16: return fastEmit_AArch64ISD_REV64_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1391 case MVT::v2i32: return fastEmit_AArch64ISD_REV64_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 1392 case MVT::v4i32: return fastEmit_AArch64ISD_REV64_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 1393 case MVT::v4f16: return fastEmit_AArch64ISD_REV64_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 1394 case MVT::v8f16: return fastEmit_AArch64ISD_REV64_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 1395 case MVT::v2f32: return fastEmit_AArch64ISD_REV64_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 1396 case MVT::v4f32: return fastEmit_AArch64ISD_REV64_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 1397 default: return 0; 1398 } 1399} 1400 1401// FastEmit functions for AArch64ISD::SITOF. 1402 1403unsigned fastEmit_AArch64ISD_SITOF_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1404 if (RetVT.SimpleTy != MVT::f16) 1405 return 0; 1406 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 1407 return fastEmitInst_r(AArch64::SCVTFv1i16, &AArch64::FPR16RegClass, Op0, Op0IsKill); 1408 } 1409 return 0; 1410} 1411 1412unsigned fastEmit_AArch64ISD_SITOF_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1413 if (RetVT.SimpleTy != MVT::f32) 1414 return 0; 1415 if ((Subtarget->hasNEON())) { 1416 return fastEmitInst_r(AArch64::SCVTFv1i32, &AArch64::FPR32RegClass, Op0, Op0IsKill); 1417 } 1418 return 0; 1419} 1420 1421unsigned fastEmit_AArch64ISD_SITOF_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1422 if (RetVT.SimpleTy != MVT::f64) 1423 return 0; 1424 if ((Subtarget->hasNEON())) { 1425 return fastEmitInst_r(AArch64::SCVTFv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1426 } 1427 return 0; 1428} 1429 1430unsigned fastEmit_AArch64ISD_SITOF_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1431 switch (VT.SimpleTy) { 1432 case MVT::f16: return fastEmit_AArch64ISD_SITOF_MVT_f16_r(RetVT, Op0, Op0IsKill); 1433 case MVT::f32: return fastEmit_AArch64ISD_SITOF_MVT_f32_r(RetVT, Op0, Op0IsKill); 1434 case MVT::f64: return fastEmit_AArch64ISD_SITOF_MVT_f64_r(RetVT, Op0, Op0IsKill); 1435 default: return 0; 1436 } 1437} 1438 1439// FastEmit functions for AArch64ISD::UITOF. 1440 1441unsigned fastEmit_AArch64ISD_UITOF_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1442 if (RetVT.SimpleTy != MVT::f16) 1443 return 0; 1444 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 1445 return fastEmitInst_r(AArch64::UCVTFv1i16, &AArch64::FPR16RegClass, Op0, Op0IsKill); 1446 } 1447 return 0; 1448} 1449 1450unsigned fastEmit_AArch64ISD_UITOF_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1451 if (RetVT.SimpleTy != MVT::f32) 1452 return 0; 1453 if ((Subtarget->hasNEON())) { 1454 return fastEmitInst_r(AArch64::UCVTFv1i32, &AArch64::FPR32RegClass, Op0, Op0IsKill); 1455 } 1456 return 0; 1457} 1458 1459unsigned fastEmit_AArch64ISD_UITOF_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1460 if (RetVT.SimpleTy != MVT::f64) 1461 return 0; 1462 if ((Subtarget->hasNEON())) { 1463 return fastEmitInst_r(AArch64::UCVTFv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1464 } 1465 return 0; 1466} 1467 1468unsigned fastEmit_AArch64ISD_UITOF_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1469 switch (VT.SimpleTy) { 1470 case MVT::f16: return fastEmit_AArch64ISD_UITOF_MVT_f16_r(RetVT, Op0, Op0IsKill); 1471 case MVT::f32: return fastEmit_AArch64ISD_UITOF_MVT_f32_r(RetVT, Op0, Op0IsKill); 1472 case MVT::f64: return fastEmit_AArch64ISD_UITOF_MVT_f64_r(RetVT, Op0, Op0IsKill); 1473 default: return 0; 1474 } 1475} 1476 1477// FastEmit functions for ISD::ABS. 1478 1479unsigned fastEmit_ISD_ABS_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1480 if (RetVT.SimpleTy != MVT::i64) 1481 return 0; 1482 if ((Subtarget->hasNEON())) { 1483 return fastEmitInst_r(AArch64::ABSv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1484 } 1485 return 0; 1486} 1487 1488unsigned fastEmit_ISD_ABS_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1489 if (RetVT.SimpleTy != MVT::v8i8) 1490 return 0; 1491 if ((Subtarget->hasNEON())) { 1492 return fastEmitInst_r(AArch64::ABSv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1493 } 1494 return 0; 1495} 1496 1497unsigned fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1498 if (RetVT.SimpleTy != MVT::v16i8) 1499 return 0; 1500 if ((Subtarget->hasNEON())) { 1501 return fastEmitInst_r(AArch64::ABSv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1502 } 1503 return 0; 1504} 1505 1506unsigned fastEmit_ISD_ABS_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1507 if (RetVT.SimpleTy != MVT::v4i16) 1508 return 0; 1509 if ((Subtarget->hasNEON())) { 1510 return fastEmitInst_r(AArch64::ABSv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1511 } 1512 return 0; 1513} 1514 1515unsigned fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1516 if (RetVT.SimpleTy != MVT::v8i16) 1517 return 0; 1518 if ((Subtarget->hasNEON())) { 1519 return fastEmitInst_r(AArch64::ABSv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1520 } 1521 return 0; 1522} 1523 1524unsigned fastEmit_ISD_ABS_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1525 if (RetVT.SimpleTy != MVT::v2i32) 1526 return 0; 1527 if ((Subtarget->hasNEON())) { 1528 return fastEmitInst_r(AArch64::ABSv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1529 } 1530 return 0; 1531} 1532 1533unsigned fastEmit_ISD_ABS_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1534 if (RetVT.SimpleTy != MVT::v4i32) 1535 return 0; 1536 if ((Subtarget->hasNEON())) { 1537 return fastEmitInst_r(AArch64::ABSv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1538 } 1539 return 0; 1540} 1541 1542unsigned fastEmit_ISD_ABS_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1543 if (RetVT.SimpleTy != MVT::v1i64) 1544 return 0; 1545 if ((Subtarget->hasNEON())) { 1546 return fastEmitInst_r(AArch64::ABSv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1547 } 1548 return 0; 1549} 1550 1551unsigned fastEmit_ISD_ABS_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1552 if (RetVT.SimpleTy != MVT::v2i64) 1553 return 0; 1554 if ((Subtarget->hasNEON())) { 1555 return fastEmitInst_r(AArch64::ABSv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1556 } 1557 return 0; 1558} 1559 1560unsigned fastEmit_ISD_ABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1561 switch (VT.SimpleTy) { 1562 case MVT::i64: return fastEmit_ISD_ABS_MVT_i64_r(RetVT, Op0, Op0IsKill); 1563 case MVT::v8i8: return fastEmit_ISD_ABS_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1564 case MVT::v16i8: return fastEmit_ISD_ABS_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1565 case MVT::v4i16: return fastEmit_ISD_ABS_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 1566 case MVT::v8i16: return fastEmit_ISD_ABS_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1567 case MVT::v2i32: return fastEmit_ISD_ABS_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 1568 case MVT::v4i32: return fastEmit_ISD_ABS_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 1569 case MVT::v1i64: return fastEmit_ISD_ABS_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 1570 case MVT::v2i64: return fastEmit_ISD_ABS_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 1571 default: return 0; 1572 } 1573} 1574 1575// FastEmit functions for ISD::BITCAST. 1576 1577unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 1578 if ((!Subtarget->isLittleEndian())) { 1579 return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1580 } 1581 return 0; 1582} 1583 1584unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 1585 if ((!Subtarget->isLittleEndian())) { 1586 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1587 } 1588 return 0; 1589} 1590 1591unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 1592 if ((!Subtarget->isLittleEndian())) { 1593 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1594 } 1595 return 0; 1596} 1597 1598unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v4f16_r(unsigned Op0, bool Op0IsKill) { 1599 if ((!Subtarget->isLittleEndian())) { 1600 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1601 } 1602 return 0; 1603} 1604 1605unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 1606 if ((!Subtarget->isLittleEndian())) { 1607 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1608 } 1609 return 0; 1610} 1611 1612unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1613switch (RetVT.SimpleTy) { 1614 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(Op0, Op0IsKill); 1615 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(Op0, Op0IsKill); 1616 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(Op0, Op0IsKill); 1617 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v4f16_r(Op0, Op0IsKill); 1618 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(Op0, Op0IsKill); 1619 default: return 0; 1620} 1621} 1622 1623unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 1624 if ((!Subtarget->isLittleEndian())) { 1625 return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1626 } 1627 return 0; 1628} 1629 1630unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 1631 if ((!Subtarget->isLittleEndian())) { 1632 return fastEmitInst_r(AArch64::REV16v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1633 } 1634 return 0; 1635} 1636 1637unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 1638 if ((!Subtarget->isLittleEndian())) { 1639 return fastEmitInst_r(AArch64::REV32v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1640 } 1641 return 0; 1642} 1643 1644unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) { 1645 if ((!Subtarget->isLittleEndian())) { 1646 return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1647 } 1648 return 0; 1649} 1650 1651unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4f16_r(unsigned Op0, bool Op0IsKill) { 1652 if ((!Subtarget->isLittleEndian())) { 1653 return fastEmitInst_r(AArch64::REV16v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1654 } 1655 return 0; 1656} 1657 1658unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 1659 if ((!Subtarget->isLittleEndian())) { 1660 return fastEmitInst_r(AArch64::REV32v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1661 } 1662 return 0; 1663} 1664 1665unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1f64_r(unsigned Op0, bool Op0IsKill) { 1666 if ((!Subtarget->isLittleEndian())) { 1667 return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1668 } 1669 return 0; 1670} 1671 1672unsigned fastEmit_ISD_BITCAST_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1673switch (RetVT.SimpleTy) { 1674 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(Op0, Op0IsKill); 1675 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(Op0, Op0IsKill); 1676 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(Op0, Op0IsKill); 1677 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(Op0, Op0IsKill); 1678 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4f16_r(Op0, Op0IsKill); 1679 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(Op0, Op0IsKill); 1680 case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1f64_r(Op0, Op0IsKill); 1681 default: return 0; 1682} 1683} 1684 1685unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 1686 if ((!Subtarget->isLittleEndian())) { 1687 return fastEmitInst_r(AArch64::REV16v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1688 } 1689 return 0; 1690} 1691 1692unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 1693 if ((!Subtarget->isLittleEndian())) { 1694 return fastEmitInst_r(AArch64::REV32v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1695 } 1696 return 0; 1697} 1698 1699unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 1700 if ((!Subtarget->isLittleEndian())) { 1701 return fastEmitInst_r(AArch64::REV64v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1702 } 1703 return 0; 1704} 1705 1706unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) { 1707 if ((!Subtarget->isLittleEndian())) { 1708 return fastEmitInst_r(AArch64::REV16v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1709 } 1710 return 0; 1711} 1712 1713unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 1714 if ((!Subtarget->isLittleEndian())) { 1715 return fastEmitInst_r(AArch64::REV32v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1716 } 1717 return 0; 1718} 1719 1720unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 1721 if ((!Subtarget->isLittleEndian())) { 1722 return fastEmitInst_r(AArch64::REV64v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1723 } 1724 return 0; 1725} 1726 1727unsigned fastEmit_ISD_BITCAST_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1728switch (RetVT.SimpleTy) { 1729 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(Op0, Op0IsKill); 1730 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(Op0, Op0IsKill); 1731 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(Op0, Op0IsKill); 1732 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8f16_r(Op0, Op0IsKill); 1733 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(Op0, Op0IsKill); 1734 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(Op0, Op0IsKill); 1735 default: return 0; 1736} 1737} 1738 1739unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 1740 if ((!Subtarget->isLittleEndian())) { 1741 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1742 } 1743 return 0; 1744} 1745 1746unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 1747 if ((!Subtarget->isLittleEndian())) { 1748 return fastEmitInst_r(AArch64::REV16v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1749 } 1750 return 0; 1751} 1752 1753unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 1754 if ((!Subtarget->isLittleEndian())) { 1755 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1756 } 1757 return 0; 1758} 1759 1760unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) { 1761 if ((!Subtarget->isLittleEndian())) { 1762 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1763 } 1764 return 0; 1765} 1766 1767unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 1768 if ((!Subtarget->isLittleEndian())) { 1769 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1770 } 1771 return 0; 1772} 1773 1774unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1f64_r(unsigned Op0, bool Op0IsKill) { 1775 if ((!Subtarget->isLittleEndian())) { 1776 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1777 } 1778 return 0; 1779} 1780 1781unsigned fastEmit_ISD_BITCAST_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1782switch (RetVT.SimpleTy) { 1783 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(Op0, Op0IsKill); 1784 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(Op0, Op0IsKill); 1785 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(Op0, Op0IsKill); 1786 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(Op0, Op0IsKill); 1787 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(Op0, Op0IsKill); 1788 case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1f64_r(Op0, Op0IsKill); 1789 default: return 0; 1790} 1791} 1792 1793unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 1794 if ((!Subtarget->isLittleEndian())) { 1795 return fastEmitInst_r(AArch64::REV16v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1796 } 1797 return 0; 1798} 1799 1800unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 1801 if ((!Subtarget->isLittleEndian())) { 1802 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1803 } 1804 return 0; 1805} 1806 1807unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 1808 if ((!Subtarget->isLittleEndian())) { 1809 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1810 } 1811 return 0; 1812} 1813 1814unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 1815 if ((!Subtarget->isLittleEndian())) { 1816 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1817 } 1818 return 0; 1819} 1820 1821unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 1822 if ((!Subtarget->isLittleEndian())) { 1823 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1824 } 1825 return 0; 1826} 1827 1828unsigned fastEmit_ISD_BITCAST_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1829switch (RetVT.SimpleTy) { 1830 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(Op0, Op0IsKill); 1831 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(Op0, Op0IsKill); 1832 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(Op0, Op0IsKill); 1833 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(Op0, Op0IsKill); 1834 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(Op0, Op0IsKill); 1835 default: return 0; 1836} 1837} 1838 1839unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 1840 if ((!Subtarget->isLittleEndian())) { 1841 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1842 } 1843 return 0; 1844} 1845 1846unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 1847 if ((!Subtarget->isLittleEndian())) { 1848 return fastEmitInst_r(AArch64::REV32v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1849 } 1850 return 0; 1851} 1852 1853unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 1854 if ((!Subtarget->isLittleEndian())) { 1855 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1856 } 1857 return 0; 1858} 1859 1860unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) { 1861 if ((!Subtarget->isLittleEndian())) { 1862 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1863 } 1864 return 0; 1865} 1866 1867unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4f16_r(unsigned Op0, bool Op0IsKill) { 1868 if ((!Subtarget->isLittleEndian())) { 1869 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1870 } 1871 return 0; 1872} 1873 1874unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1f64_r(unsigned Op0, bool Op0IsKill) { 1875 if ((!Subtarget->isLittleEndian())) { 1876 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1877 } 1878 return 0; 1879} 1880 1881unsigned fastEmit_ISD_BITCAST_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1882switch (RetVT.SimpleTy) { 1883 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(Op0, Op0IsKill); 1884 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(Op0, Op0IsKill); 1885 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(Op0, Op0IsKill); 1886 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(Op0, Op0IsKill); 1887 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4f16_r(Op0, Op0IsKill); 1888 case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1f64_r(Op0, Op0IsKill); 1889 default: return 0; 1890} 1891} 1892 1893unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 1894 if ((!Subtarget->isLittleEndian())) { 1895 return fastEmitInst_r(AArch64::REV32v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1896 } 1897 return 0; 1898} 1899 1900unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 1901 if ((!Subtarget->isLittleEndian())) { 1902 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1903 } 1904 return 0; 1905} 1906 1907unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 1908 if ((!Subtarget->isLittleEndian())) { 1909 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1910 } 1911 return 0; 1912} 1913 1914unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) { 1915 if ((!Subtarget->isLittleEndian())) { 1916 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1917 } 1918 return 0; 1919} 1920 1921unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 1922 if ((!Subtarget->isLittleEndian())) { 1923 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1924 } 1925 return 0; 1926} 1927 1928unsigned fastEmit_ISD_BITCAST_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1929switch (RetVT.SimpleTy) { 1930 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(Op0, Op0IsKill); 1931 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(Op0, Op0IsKill); 1932 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(Op0, Op0IsKill); 1933 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8f16_r(Op0, Op0IsKill); 1934 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(Op0, Op0IsKill); 1935 default: return 0; 1936} 1937} 1938 1939unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 1940 if ((!Subtarget->isLittleEndian())) { 1941 return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1942 } 1943 return 0; 1944} 1945 1946unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 1947 if ((!Subtarget->isLittleEndian())) { 1948 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1949 } 1950 return 0; 1951} 1952 1953unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 1954 if ((!Subtarget->isLittleEndian())) { 1955 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1956 } 1957 return 0; 1958} 1959 1960unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4f16_r(unsigned Op0, bool Op0IsKill) { 1961 if ((!Subtarget->isLittleEndian())) { 1962 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1963 } 1964 return 0; 1965} 1966 1967unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 1968 if ((!Subtarget->isLittleEndian())) { 1969 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 1970 } 1971 return 0; 1972} 1973 1974unsigned fastEmit_ISD_BITCAST_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1975switch (RetVT.SimpleTy) { 1976 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(Op0, Op0IsKill); 1977 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(Op0, Op0IsKill); 1978 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(Op0, Op0IsKill); 1979 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4f16_r(Op0, Op0IsKill); 1980 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(Op0, Op0IsKill); 1981 default: return 0; 1982} 1983} 1984 1985unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 1986 if ((!Subtarget->isLittleEndian())) { 1987 return fastEmitInst_r(AArch64::REV64v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1988 } 1989 return 0; 1990} 1991 1992unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 1993 if ((!Subtarget->isLittleEndian())) { 1994 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 1995 } 1996 return 0; 1997} 1998 1999unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 2000 if ((!Subtarget->isLittleEndian())) { 2001 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2002 } 2003 return 0; 2004} 2005 2006unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) { 2007 if ((!Subtarget->isLittleEndian())) { 2008 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2009 } 2010 return 0; 2011} 2012 2013unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 2014 if ((!Subtarget->isLittleEndian())) { 2015 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2016 } 2017 return 0; 2018} 2019 2020unsigned fastEmit_ISD_BITCAST_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2021switch (RetVT.SimpleTy) { 2022 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(Op0, Op0IsKill); 2023 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(Op0, Op0IsKill); 2024 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(Op0, Op0IsKill); 2025 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8f16_r(Op0, Op0IsKill); 2026 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(Op0, Op0IsKill); 2027 default: return 0; 2028} 2029} 2030 2031unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 2032 if ((!Subtarget->isLittleEndian())) { 2033 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2034 } 2035 return 0; 2036} 2037 2038unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 2039 if ((!Subtarget->isLittleEndian())) { 2040 return fastEmitInst_r(AArch64::REV16v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2041 } 2042 return 0; 2043} 2044 2045unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 2046 if ((!Subtarget->isLittleEndian())) { 2047 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2048 } 2049 return 0; 2050} 2051 2052unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) { 2053 if ((!Subtarget->isLittleEndian())) { 2054 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2055 } 2056 return 0; 2057} 2058 2059unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 2060 if ((!Subtarget->isLittleEndian())) { 2061 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2062 } 2063 return 0; 2064} 2065 2066unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v1f64_r(unsigned Op0, bool Op0IsKill) { 2067 if ((!Subtarget->isLittleEndian())) { 2068 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2069 } 2070 return 0; 2071} 2072 2073unsigned fastEmit_ISD_BITCAST_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2074switch (RetVT.SimpleTy) { 2075 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_f64_r(Op0, Op0IsKill); 2076 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v8i8_r(Op0, Op0IsKill); 2077 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v2i32_r(Op0, Op0IsKill); 2078 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v1i64_r(Op0, Op0IsKill); 2079 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v2f32_r(Op0, Op0IsKill); 2080 case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v1f64_r(Op0, Op0IsKill); 2081 default: return 0; 2082} 2083} 2084 2085unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 2086 if ((!Subtarget->isLittleEndian())) { 2087 return fastEmitInst_r(AArch64::REV16v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2088 } 2089 return 0; 2090} 2091 2092unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 2093 if ((!Subtarget->isLittleEndian())) { 2094 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2095 } 2096 return 0; 2097} 2098 2099unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 2100 if ((!Subtarget->isLittleEndian())) { 2101 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2102 } 2103 return 0; 2104} 2105 2106unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 2107 if ((!Subtarget->isLittleEndian())) { 2108 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2109 } 2110 return 0; 2111} 2112 2113unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 2114 if ((!Subtarget->isLittleEndian())) { 2115 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2116 } 2117 return 0; 2118} 2119 2120unsigned fastEmit_ISD_BITCAST_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2121switch (RetVT.SimpleTy) { 2122 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v16i8_r(Op0, Op0IsKill); 2123 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4i32_r(Op0, Op0IsKill); 2124 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2i64_r(Op0, Op0IsKill); 2125 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4f32_r(Op0, Op0IsKill); 2126 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2f64_r(Op0, Op0IsKill); 2127 default: return 0; 2128} 2129} 2130 2131unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 2132 if ((!Subtarget->isLittleEndian())) { 2133 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2134 } 2135 return 0; 2136} 2137 2138unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 2139 if ((!Subtarget->isLittleEndian())) { 2140 return fastEmitInst_r(AArch64::REV32v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2141 } 2142 return 0; 2143} 2144 2145unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 2146 if ((!Subtarget->isLittleEndian())) { 2147 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2148 } 2149 return 0; 2150} 2151 2152unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) { 2153 if ((!Subtarget->isLittleEndian())) { 2154 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2155 } 2156 return 0; 2157} 2158 2159unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4f16_r(unsigned Op0, bool Op0IsKill) { 2160 if ((!Subtarget->isLittleEndian())) { 2161 return fastEmitInst_r(AArch64::REV32v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2162 } 2163 return 0; 2164} 2165 2166unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1f64_r(unsigned Op0, bool Op0IsKill) { 2167 if ((!Subtarget->isLittleEndian())) { 2168 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2169 } 2170 return 0; 2171} 2172 2173unsigned fastEmit_ISD_BITCAST_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2174switch (RetVT.SimpleTy) { 2175 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(Op0, Op0IsKill); 2176 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(Op0, Op0IsKill); 2177 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(Op0, Op0IsKill); 2178 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(Op0, Op0IsKill); 2179 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4f16_r(Op0, Op0IsKill); 2180 case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1f64_r(Op0, Op0IsKill); 2181 default: return 0; 2182} 2183} 2184 2185unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 2186 if ((!Subtarget->isLittleEndian())) { 2187 return fastEmitInst_r(AArch64::REV32v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2188 } 2189 return 0; 2190} 2191 2192unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 2193 if ((!Subtarget->isLittleEndian())) { 2194 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2195 } 2196 return 0; 2197} 2198 2199unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 2200 if ((!Subtarget->isLittleEndian())) { 2201 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2202 } 2203 return 0; 2204} 2205 2206unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) { 2207 if ((!Subtarget->isLittleEndian())) { 2208 return fastEmitInst_r(AArch64::REV32v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2209 } 2210 return 0; 2211} 2212 2213unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 2214 if ((!Subtarget->isLittleEndian())) { 2215 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2216 } 2217 return 0; 2218} 2219 2220unsigned fastEmit_ISD_BITCAST_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2221switch (RetVT.SimpleTy) { 2222 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(Op0, Op0IsKill); 2223 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(Op0, Op0IsKill); 2224 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(Op0, Op0IsKill); 2225 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8f16_r(Op0, Op0IsKill); 2226 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(Op0, Op0IsKill); 2227 default: return 0; 2228} 2229} 2230 2231unsigned fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 2232 if ((!Subtarget->isLittleEndian())) { 2233 return fastEmitInst_r(AArch64::REV64v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2234 } 2235 return 0; 2236} 2237 2238unsigned fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 2239 if ((!Subtarget->isLittleEndian())) { 2240 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2241 } 2242 return 0; 2243} 2244 2245unsigned fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 2246 if ((!Subtarget->isLittleEndian())) { 2247 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2248 } 2249 return 0; 2250} 2251 2252unsigned fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v4f16_r(unsigned Op0, bool Op0IsKill) { 2253 if ((!Subtarget->isLittleEndian())) { 2254 return fastEmitInst_r(AArch64::REV64v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2255 } 2256 return 0; 2257} 2258 2259unsigned fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 2260 if ((!Subtarget->isLittleEndian())) { 2261 return fastEmitInst_r(AArch64::REV64v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2262 } 2263 return 0; 2264} 2265 2266unsigned fastEmit_ISD_BITCAST_MVT_v1f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2267switch (RetVT.SimpleTy) { 2268 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v8i8_r(Op0, Op0IsKill); 2269 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v4i16_r(Op0, Op0IsKill); 2270 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v2i32_r(Op0, Op0IsKill); 2271 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v4f16_r(Op0, Op0IsKill); 2272 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v1f64_MVT_v2f32_r(Op0, Op0IsKill); 2273 default: return 0; 2274} 2275} 2276 2277unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 2278 if ((!Subtarget->isLittleEndian())) { 2279 return fastEmitInst_r(AArch64::REV64v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2280 } 2281 return 0; 2282} 2283 2284unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 2285 if ((!Subtarget->isLittleEndian())) { 2286 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2287 } 2288 return 0; 2289} 2290 2291unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 2292 if ((!Subtarget->isLittleEndian())) { 2293 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2294 } 2295 return 0; 2296} 2297 2298unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) { 2299 if ((!Subtarget->isLittleEndian())) { 2300 return fastEmitInst_r(AArch64::REV64v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2301 } 2302 return 0; 2303} 2304 2305unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 2306 if ((!Subtarget->isLittleEndian())) { 2307 return fastEmitInst_r(AArch64::REV64v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2308 } 2309 return 0; 2310} 2311 2312unsigned fastEmit_ISD_BITCAST_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2313switch (RetVT.SimpleTy) { 2314 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(Op0, Op0IsKill); 2315 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(Op0, Op0IsKill); 2316 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(Op0, Op0IsKill); 2317 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(Op0, Op0IsKill); 2318 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(Op0, Op0IsKill); 2319 default: return 0; 2320} 2321} 2322 2323unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2324 switch (VT.SimpleTy) { 2325 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill); 2326 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 2327 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 2328 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 2329 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 2330 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 2331 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 2332 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 2333 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 2334 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 2335 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 2336 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 2337 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 2338 case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v1f64_r(RetVT, Op0, Op0IsKill); 2339 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 2340 default: return 0; 2341 } 2342} 2343 2344// FastEmit functions for ISD::BITREVERSE. 2345 2346unsigned fastEmit_ISD_BITREVERSE_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2347 if (RetVT.SimpleTy != MVT::i32) 2348 return 0; 2349 return fastEmitInst_r(AArch64::RBITWr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 2350} 2351 2352unsigned fastEmit_ISD_BITREVERSE_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2353 if (RetVT.SimpleTy != MVT::i64) 2354 return 0; 2355 return fastEmitInst_r(AArch64::RBITXr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 2356} 2357 2358unsigned fastEmit_ISD_BITREVERSE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2359 switch (VT.SimpleTy) { 2360 case MVT::i32: return fastEmit_ISD_BITREVERSE_MVT_i32_r(RetVT, Op0, Op0IsKill); 2361 case MVT::i64: return fastEmit_ISD_BITREVERSE_MVT_i64_r(RetVT, Op0, Op0IsKill); 2362 default: return 0; 2363 } 2364} 2365 2366// FastEmit functions for ISD::BRIND. 2367 2368unsigned fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2369 if (RetVT.SimpleTy != MVT::isVoid) 2370 return 0; 2371 return fastEmitInst_r(AArch64::BR, &AArch64::GPR64RegClass, Op0, Op0IsKill); 2372} 2373 2374unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2375 switch (VT.SimpleTy) { 2376 case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0, Op0IsKill); 2377 default: return 0; 2378 } 2379} 2380 2381// FastEmit functions for ISD::BSWAP. 2382 2383unsigned fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2384 if (RetVT.SimpleTy != MVT::i32) 2385 return 0; 2386 return fastEmitInst_r(AArch64::REVWr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 2387} 2388 2389unsigned fastEmit_ISD_BSWAP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2390 if (RetVT.SimpleTy != MVT::i64) 2391 return 0; 2392 return fastEmitInst_r(AArch64::REVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 2393} 2394 2395unsigned fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2396 switch (VT.SimpleTy) { 2397 case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0, Op0IsKill); 2398 case MVT::i64: return fastEmit_ISD_BSWAP_MVT_i64_r(RetVT, Op0, Op0IsKill); 2399 default: return 0; 2400 } 2401} 2402 2403// FastEmit functions for ISD::CTLZ. 2404 2405unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2406 if (RetVT.SimpleTy != MVT::i32) 2407 return 0; 2408 return fastEmitInst_r(AArch64::CLZWr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 2409} 2410 2411unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2412 if (RetVT.SimpleTy != MVT::i64) 2413 return 0; 2414 return fastEmitInst_r(AArch64::CLZXr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 2415} 2416 2417unsigned fastEmit_ISD_CTLZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2418 if (RetVT.SimpleTy != MVT::v8i8) 2419 return 0; 2420 if ((Subtarget->hasNEON())) { 2421 return fastEmitInst_r(AArch64::CLZv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2422 } 2423 return 0; 2424} 2425 2426unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2427 if (RetVT.SimpleTy != MVT::v16i8) 2428 return 0; 2429 if ((Subtarget->hasNEON())) { 2430 return fastEmitInst_r(AArch64::CLZv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2431 } 2432 return 0; 2433} 2434 2435unsigned fastEmit_ISD_CTLZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2436 if (RetVT.SimpleTy != MVT::v4i16) 2437 return 0; 2438 if ((Subtarget->hasNEON())) { 2439 return fastEmitInst_r(AArch64::CLZv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2440 } 2441 return 0; 2442} 2443 2444unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2445 if (RetVT.SimpleTy != MVT::v8i16) 2446 return 0; 2447 if ((Subtarget->hasNEON())) { 2448 return fastEmitInst_r(AArch64::CLZv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2449 } 2450 return 0; 2451} 2452 2453unsigned fastEmit_ISD_CTLZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2454 if (RetVT.SimpleTy != MVT::v2i32) 2455 return 0; 2456 if ((Subtarget->hasNEON())) { 2457 return fastEmitInst_r(AArch64::CLZv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2458 } 2459 return 0; 2460} 2461 2462unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2463 if (RetVT.SimpleTy != MVT::v4i32) 2464 return 0; 2465 if ((Subtarget->hasNEON())) { 2466 return fastEmitInst_r(AArch64::CLZv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2467 } 2468 return 0; 2469} 2470 2471unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2472 switch (VT.SimpleTy) { 2473 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill); 2474 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0, Op0IsKill); 2475 case MVT::v8i8: return fastEmit_ISD_CTLZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 2476 case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 2477 case MVT::v4i16: return fastEmit_ISD_CTLZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 2478 case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 2479 case MVT::v2i32: return fastEmit_ISD_CTLZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 2480 case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 2481 default: return 0; 2482 } 2483} 2484 2485// FastEmit functions for ISD::CTPOP. 2486 2487unsigned fastEmit_ISD_CTPOP_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2488 if (RetVT.SimpleTy != MVT::v8i8) 2489 return 0; 2490 if ((Subtarget->hasNEON())) { 2491 return fastEmitInst_r(AArch64::CNTv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2492 } 2493 return 0; 2494} 2495 2496unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2497 if (RetVT.SimpleTy != MVT::v16i8) 2498 return 0; 2499 if ((Subtarget->hasNEON())) { 2500 return fastEmitInst_r(AArch64::CNTv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2501 } 2502 return 0; 2503} 2504 2505unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2506 switch (VT.SimpleTy) { 2507 case MVT::v8i8: return fastEmit_ISD_CTPOP_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 2508 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 2509 default: return 0; 2510 } 2511} 2512 2513// FastEmit functions for ISD::FABS. 2514 2515unsigned fastEmit_ISD_FABS_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2516 if (RetVT.SimpleTy != MVT::f16) 2517 return 0; 2518 if ((Subtarget->hasFullFP16())) { 2519 return fastEmitInst_r(AArch64::FABSHr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 2520 } 2521 return 0; 2522} 2523 2524unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2525 if (RetVT.SimpleTy != MVT::f32) 2526 return 0; 2527 if ((Subtarget->hasFPARMv8())) { 2528 return fastEmitInst_r(AArch64::FABSSr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 2529 } 2530 return 0; 2531} 2532 2533unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2534 if (RetVT.SimpleTy != MVT::f64) 2535 return 0; 2536 if ((Subtarget->hasFPARMv8())) { 2537 return fastEmitInst_r(AArch64::FABSDr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2538 } 2539 return 0; 2540} 2541 2542unsigned fastEmit_ISD_FABS_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2543 if (RetVT.SimpleTy != MVT::v4f16) 2544 return 0; 2545 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2546 return fastEmitInst_r(AArch64::FABSv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2547 } 2548 return 0; 2549} 2550 2551unsigned fastEmit_ISD_FABS_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2552 if (RetVT.SimpleTy != MVT::v8f16) 2553 return 0; 2554 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2555 return fastEmitInst_r(AArch64::FABSv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2556 } 2557 return 0; 2558} 2559 2560unsigned fastEmit_ISD_FABS_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2561 if (RetVT.SimpleTy != MVT::v2f32) 2562 return 0; 2563 if ((Subtarget->hasNEON())) { 2564 return fastEmitInst_r(AArch64::FABSv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2565 } 2566 return 0; 2567} 2568 2569unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2570 if (RetVT.SimpleTy != MVT::v4f32) 2571 return 0; 2572 if ((Subtarget->hasNEON())) { 2573 return fastEmitInst_r(AArch64::FABSv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2574 } 2575 return 0; 2576} 2577 2578unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2579 if (RetVT.SimpleTy != MVT::v2f64) 2580 return 0; 2581 if ((Subtarget->hasNEON())) { 2582 return fastEmitInst_r(AArch64::FABSv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2583 } 2584 return 0; 2585} 2586 2587unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2588 switch (VT.SimpleTy) { 2589 case MVT::f16: return fastEmit_ISD_FABS_MVT_f16_r(RetVT, Op0, Op0IsKill); 2590 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill); 2591 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill); 2592 case MVT::v4f16: return fastEmit_ISD_FABS_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 2593 case MVT::v8f16: return fastEmit_ISD_FABS_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 2594 case MVT::v2f32: return fastEmit_ISD_FABS_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 2595 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 2596 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 2597 default: return 0; 2598 } 2599} 2600 2601// FastEmit functions for ISD::FCEIL. 2602 2603unsigned fastEmit_ISD_FCEIL_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2604 if (RetVT.SimpleTy != MVT::f16) 2605 return 0; 2606 if ((Subtarget->hasFullFP16())) { 2607 return fastEmitInst_r(AArch64::FRINTPHr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 2608 } 2609 return 0; 2610} 2611 2612unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2613 if (RetVT.SimpleTy != MVT::f32) 2614 return 0; 2615 if ((Subtarget->hasFPARMv8())) { 2616 return fastEmitInst_r(AArch64::FRINTPSr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 2617 } 2618 return 0; 2619} 2620 2621unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2622 if (RetVT.SimpleTy != MVT::f64) 2623 return 0; 2624 if ((Subtarget->hasFPARMv8())) { 2625 return fastEmitInst_r(AArch64::FRINTPDr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2626 } 2627 return 0; 2628} 2629 2630unsigned fastEmit_ISD_FCEIL_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2631 if (RetVT.SimpleTy != MVT::v4f16) 2632 return 0; 2633 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2634 return fastEmitInst_r(AArch64::FRINTPv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2635 } 2636 return 0; 2637} 2638 2639unsigned fastEmit_ISD_FCEIL_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2640 if (RetVT.SimpleTy != MVT::v8f16) 2641 return 0; 2642 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2643 return fastEmitInst_r(AArch64::FRINTPv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2644 } 2645 return 0; 2646} 2647 2648unsigned fastEmit_ISD_FCEIL_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2649 if (RetVT.SimpleTy != MVT::v2f32) 2650 return 0; 2651 if ((Subtarget->hasNEON())) { 2652 return fastEmitInst_r(AArch64::FRINTPv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2653 } 2654 return 0; 2655} 2656 2657unsigned fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2658 if (RetVT.SimpleTy != MVT::v4f32) 2659 return 0; 2660 if ((Subtarget->hasNEON())) { 2661 return fastEmitInst_r(AArch64::FRINTPv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2662 } 2663 return 0; 2664} 2665 2666unsigned fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2667 if (RetVT.SimpleTy != MVT::v2f64) 2668 return 0; 2669 if ((Subtarget->hasNEON())) { 2670 return fastEmitInst_r(AArch64::FRINTPv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2671 } 2672 return 0; 2673} 2674 2675unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2676 switch (VT.SimpleTy) { 2677 case MVT::f16: return fastEmit_ISD_FCEIL_MVT_f16_r(RetVT, Op0, Op0IsKill); 2678 case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill); 2679 case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0, Op0IsKill); 2680 case MVT::v4f16: return fastEmit_ISD_FCEIL_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 2681 case MVT::v8f16: return fastEmit_ISD_FCEIL_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 2682 case MVT::v2f32: return fastEmit_ISD_FCEIL_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 2683 case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 2684 case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 2685 default: return 0; 2686 } 2687} 2688 2689// FastEmit functions for ISD::FFLOOR. 2690 2691unsigned fastEmit_ISD_FFLOOR_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2692 if (RetVT.SimpleTy != MVT::f16) 2693 return 0; 2694 if ((Subtarget->hasFullFP16())) { 2695 return fastEmitInst_r(AArch64::FRINTMHr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 2696 } 2697 return 0; 2698} 2699 2700unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2701 if (RetVT.SimpleTy != MVT::f32) 2702 return 0; 2703 if ((Subtarget->hasFPARMv8())) { 2704 return fastEmitInst_r(AArch64::FRINTMSr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 2705 } 2706 return 0; 2707} 2708 2709unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2710 if (RetVT.SimpleTy != MVT::f64) 2711 return 0; 2712 if ((Subtarget->hasFPARMv8())) { 2713 return fastEmitInst_r(AArch64::FRINTMDr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2714 } 2715 return 0; 2716} 2717 2718unsigned fastEmit_ISD_FFLOOR_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2719 if (RetVT.SimpleTy != MVT::v4f16) 2720 return 0; 2721 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2722 return fastEmitInst_r(AArch64::FRINTMv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2723 } 2724 return 0; 2725} 2726 2727unsigned fastEmit_ISD_FFLOOR_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2728 if (RetVT.SimpleTy != MVT::v8f16) 2729 return 0; 2730 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2731 return fastEmitInst_r(AArch64::FRINTMv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2732 } 2733 return 0; 2734} 2735 2736unsigned fastEmit_ISD_FFLOOR_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2737 if (RetVT.SimpleTy != MVT::v2f32) 2738 return 0; 2739 if ((Subtarget->hasNEON())) { 2740 return fastEmitInst_r(AArch64::FRINTMv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2741 } 2742 return 0; 2743} 2744 2745unsigned fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2746 if (RetVT.SimpleTy != MVT::v4f32) 2747 return 0; 2748 if ((Subtarget->hasNEON())) { 2749 return fastEmitInst_r(AArch64::FRINTMv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2750 } 2751 return 0; 2752} 2753 2754unsigned fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2755 if (RetVT.SimpleTy != MVT::v2f64) 2756 return 0; 2757 if ((Subtarget->hasNEON())) { 2758 return fastEmitInst_r(AArch64::FRINTMv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2759 } 2760 return 0; 2761} 2762 2763unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2764 switch (VT.SimpleTy) { 2765 case MVT::f16: return fastEmit_ISD_FFLOOR_MVT_f16_r(RetVT, Op0, Op0IsKill); 2766 case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill); 2767 case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0, Op0IsKill); 2768 case MVT::v4f16: return fastEmit_ISD_FFLOOR_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 2769 case MVT::v8f16: return fastEmit_ISD_FFLOOR_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 2770 case MVT::v2f32: return fastEmit_ISD_FFLOOR_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 2771 case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 2772 case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 2773 default: return 0; 2774 } 2775} 2776 2777// FastEmit functions for ISD::FNEARBYINT. 2778 2779unsigned fastEmit_ISD_FNEARBYINT_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2780 if (RetVT.SimpleTy != MVT::f16) 2781 return 0; 2782 if ((Subtarget->hasFullFP16())) { 2783 return fastEmitInst_r(AArch64::FRINTIHr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 2784 } 2785 return 0; 2786} 2787 2788unsigned fastEmit_ISD_FNEARBYINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2789 if (RetVT.SimpleTy != MVT::f32) 2790 return 0; 2791 if ((Subtarget->hasFPARMv8())) { 2792 return fastEmitInst_r(AArch64::FRINTISr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 2793 } 2794 return 0; 2795} 2796 2797unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2798 if (RetVT.SimpleTy != MVT::f64) 2799 return 0; 2800 if ((Subtarget->hasFPARMv8())) { 2801 return fastEmitInst_r(AArch64::FRINTIDr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2802 } 2803 return 0; 2804} 2805 2806unsigned fastEmit_ISD_FNEARBYINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2807 if (RetVT.SimpleTy != MVT::v4f16) 2808 return 0; 2809 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2810 return fastEmitInst_r(AArch64::FRINTIv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2811 } 2812 return 0; 2813} 2814 2815unsigned fastEmit_ISD_FNEARBYINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2816 if (RetVT.SimpleTy != MVT::v8f16) 2817 return 0; 2818 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2819 return fastEmitInst_r(AArch64::FRINTIv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2820 } 2821 return 0; 2822} 2823 2824unsigned fastEmit_ISD_FNEARBYINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2825 if (RetVT.SimpleTy != MVT::v2f32) 2826 return 0; 2827 if ((Subtarget->hasNEON())) { 2828 return fastEmitInst_r(AArch64::FRINTIv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2829 } 2830 return 0; 2831} 2832 2833unsigned fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2834 if (RetVT.SimpleTy != MVT::v4f32) 2835 return 0; 2836 if ((Subtarget->hasNEON())) { 2837 return fastEmitInst_r(AArch64::FRINTIv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2838 } 2839 return 0; 2840} 2841 2842unsigned fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2843 if (RetVT.SimpleTy != MVT::v2f64) 2844 return 0; 2845 if ((Subtarget->hasNEON())) { 2846 return fastEmitInst_r(AArch64::FRINTIv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2847 } 2848 return 0; 2849} 2850 2851unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2852 switch (VT.SimpleTy) { 2853 case MVT::f16: return fastEmit_ISD_FNEARBYINT_MVT_f16_r(RetVT, Op0, Op0IsKill); 2854 case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0, Op0IsKill); 2855 case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0, Op0IsKill); 2856 case MVT::v4f16: return fastEmit_ISD_FNEARBYINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 2857 case MVT::v8f16: return fastEmit_ISD_FNEARBYINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 2858 case MVT::v2f32: return fastEmit_ISD_FNEARBYINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 2859 case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 2860 case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 2861 default: return 0; 2862 } 2863} 2864 2865// FastEmit functions for ISD::FNEG. 2866 2867unsigned fastEmit_ISD_FNEG_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2868 if (RetVT.SimpleTy != MVT::f16) 2869 return 0; 2870 if ((Subtarget->hasFullFP16())) { 2871 return fastEmitInst_r(AArch64::FNEGHr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 2872 } 2873 return 0; 2874} 2875 2876unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2877 if (RetVT.SimpleTy != MVT::f32) 2878 return 0; 2879 if ((Subtarget->hasFPARMv8())) { 2880 return fastEmitInst_r(AArch64::FNEGSr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 2881 } 2882 return 0; 2883} 2884 2885unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2886 if (RetVT.SimpleTy != MVT::f64) 2887 return 0; 2888 if ((Subtarget->hasFPARMv8())) { 2889 return fastEmitInst_r(AArch64::FNEGDr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2890 } 2891 return 0; 2892} 2893 2894unsigned fastEmit_ISD_FNEG_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2895 if (RetVT.SimpleTy != MVT::v4f16) 2896 return 0; 2897 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2898 return fastEmitInst_r(AArch64::FNEGv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2899 } 2900 return 0; 2901} 2902 2903unsigned fastEmit_ISD_FNEG_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2904 if (RetVT.SimpleTy != MVT::v8f16) 2905 return 0; 2906 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2907 return fastEmitInst_r(AArch64::FNEGv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2908 } 2909 return 0; 2910} 2911 2912unsigned fastEmit_ISD_FNEG_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2913 if (RetVT.SimpleTy != MVT::v2f32) 2914 return 0; 2915 if ((Subtarget->hasNEON())) { 2916 return fastEmitInst_r(AArch64::FNEGv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2917 } 2918 return 0; 2919} 2920 2921unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2922 if (RetVT.SimpleTy != MVT::v4f32) 2923 return 0; 2924 if ((Subtarget->hasNEON())) { 2925 return fastEmitInst_r(AArch64::FNEGv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2926 } 2927 return 0; 2928} 2929 2930unsigned fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2931 if (RetVT.SimpleTy != MVT::v2f64) 2932 return 0; 2933 if ((Subtarget->hasNEON())) { 2934 return fastEmitInst_r(AArch64::FNEGv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2935 } 2936 return 0; 2937} 2938 2939unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2940 switch (VT.SimpleTy) { 2941 case MVT::f16: return fastEmit_ISD_FNEG_MVT_f16_r(RetVT, Op0, Op0IsKill); 2942 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill); 2943 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill); 2944 case MVT::v4f16: return fastEmit_ISD_FNEG_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 2945 case MVT::v8f16: return fastEmit_ISD_FNEG_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 2946 case MVT::v2f32: return fastEmit_ISD_FNEG_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 2947 case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 2948 case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 2949 default: return 0; 2950 } 2951} 2952 2953// FastEmit functions for ISD::FP_EXTEND. 2954 2955unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 2956 if ((Subtarget->hasFPARMv8())) { 2957 return fastEmitInst_r(AArch64::FCVTSHr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 2958 } 2959 return 0; 2960} 2961 2962unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 2963 if ((Subtarget->hasFPARMv8())) { 2964 return fastEmitInst_r(AArch64::FCVTDHr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2965 } 2966 return 0; 2967} 2968 2969unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2970switch (RetVT.SimpleTy) { 2971 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Op0, Op0IsKill); 2972 case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Op0, Op0IsKill); 2973 default: return 0; 2974} 2975} 2976 2977unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2978 if (RetVT.SimpleTy != MVT::f64) 2979 return 0; 2980 if ((Subtarget->hasFPARMv8())) { 2981 return fastEmitInst_r(AArch64::FCVTDSr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 2982 } 2983 return 0; 2984} 2985 2986unsigned fastEmit_ISD_FP_EXTEND_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2987 if (RetVT.SimpleTy != MVT::v4f32) 2988 return 0; 2989 return fastEmitInst_r(AArch64::FCVTLv4i16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2990} 2991 2992unsigned fastEmit_ISD_FP_EXTEND_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2993 if (RetVT.SimpleTy != MVT::v2f64) 2994 return 0; 2995 return fastEmitInst_r(AArch64::FCVTLv2i32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 2996} 2997 2998unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2999 switch (VT.SimpleTy) { 3000 case MVT::f16: return fastEmit_ISD_FP_EXTEND_MVT_f16_r(RetVT, Op0, Op0IsKill); 3001 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill); 3002 case MVT::v4f16: return fastEmit_ISD_FP_EXTEND_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 3003 case MVT::v2f32: return fastEmit_ISD_FP_EXTEND_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 3004 default: return 0; 3005 } 3006} 3007 3008// FastEmit functions for ISD::FP_ROUND. 3009 3010unsigned fastEmit_ISD_FP_ROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3011 if (RetVT.SimpleTy != MVT::f16) 3012 return 0; 3013 if ((Subtarget->hasFPARMv8())) { 3014 return fastEmitInst_r(AArch64::FCVTHSr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 3015 } 3016 return 0; 3017} 3018 3019unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(unsigned Op0, bool Op0IsKill) { 3020 if ((Subtarget->hasFPARMv8())) { 3021 return fastEmitInst_r(AArch64::FCVTHDr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 3022 } 3023 return 0; 3024} 3025 3026unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 3027 if ((Subtarget->hasFPARMv8())) { 3028 return fastEmitInst_r(AArch64::FCVTSDr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 3029 } 3030 return 0; 3031} 3032 3033unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3034switch (RetVT.SimpleTy) { 3035 case MVT::f16: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Op0, Op0IsKill); 3036 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Op0, Op0IsKill); 3037 default: return 0; 3038} 3039} 3040 3041unsigned fastEmit_ISD_FP_ROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3042 if (RetVT.SimpleTy != MVT::v4f16) 3043 return 0; 3044 return fastEmitInst_r(AArch64::FCVTNv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3045} 3046 3047unsigned fastEmit_ISD_FP_ROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3048 if (RetVT.SimpleTy != MVT::v2f32) 3049 return 0; 3050 return fastEmitInst_r(AArch64::FCVTNv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3051} 3052 3053unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3054 switch (VT.SimpleTy) { 3055 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f32_r(RetVT, Op0, Op0IsKill); 3056 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill); 3057 case MVT::v4f32: return fastEmit_ISD_FP_ROUND_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 3058 case MVT::v2f64: return fastEmit_ISD_FP_ROUND_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 3059 default: return 0; 3060 } 3061} 3062 3063// FastEmit functions for ISD::FP_TO_SINT. 3064 3065unsigned fastEmit_ISD_FP_TO_SINT_MVT_f16_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 3066 if ((Subtarget->hasFullFP16())) { 3067 return fastEmitInst_r(AArch64::FCVTZSUWHr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 3068 } 3069 return 0; 3070} 3071 3072unsigned fastEmit_ISD_FP_TO_SINT_MVT_f16_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 3073 if ((Subtarget->hasFullFP16())) { 3074 return fastEmitInst_r(AArch64::FCVTZSUXHr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 3075 } 3076 return 0; 3077} 3078 3079unsigned fastEmit_ISD_FP_TO_SINT_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3080switch (RetVT.SimpleTy) { 3081 case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f16_MVT_i32_r(Op0, Op0IsKill); 3082 case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f16_MVT_i64_r(Op0, Op0IsKill); 3083 default: return 0; 3084} 3085} 3086 3087unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 3088 if ((Subtarget->hasFPARMv8())) { 3089 return fastEmitInst_r(AArch64::FCVTZSUWSr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 3090 } 3091 return 0; 3092} 3093 3094unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 3095 if ((Subtarget->hasFPARMv8())) { 3096 return fastEmitInst_r(AArch64::FCVTZSUXSr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 3097 } 3098 return 0; 3099} 3100 3101unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3102switch (RetVT.SimpleTy) { 3103 case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(Op0, Op0IsKill); 3104 case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(Op0, Op0IsKill); 3105 default: return 0; 3106} 3107} 3108 3109unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 3110 if ((Subtarget->hasFPARMv8())) { 3111 return fastEmitInst_r(AArch64::FCVTZSUWDr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 3112 } 3113 return 0; 3114} 3115 3116unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 3117 if ((Subtarget->hasFPARMv8())) { 3118 return fastEmitInst_r(AArch64::FCVTZSUXDr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 3119 } 3120 return 0; 3121} 3122 3123unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3124switch (RetVT.SimpleTy) { 3125 case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(Op0, Op0IsKill); 3126 case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(Op0, Op0IsKill); 3127 default: return 0; 3128} 3129} 3130 3131unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3132 if (RetVT.SimpleTy != MVT::v4i16) 3133 return 0; 3134 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3135 return fastEmitInst_r(AArch64::FCVTZSv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3136 } 3137 return 0; 3138} 3139 3140unsigned fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3141 if (RetVT.SimpleTy != MVT::v8i16) 3142 return 0; 3143 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3144 return fastEmitInst_r(AArch64::FCVTZSv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3145 } 3146 return 0; 3147} 3148 3149unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3150 if (RetVT.SimpleTy != MVT::v2i32) 3151 return 0; 3152 if ((Subtarget->hasNEON())) { 3153 return fastEmitInst_r(AArch64::FCVTZSv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3154 } 3155 return 0; 3156} 3157 3158unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3159 if (RetVT.SimpleTy != MVT::v4i32) 3160 return 0; 3161 if ((Subtarget->hasNEON())) { 3162 return fastEmitInst_r(AArch64::FCVTZSv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3163 } 3164 return 0; 3165} 3166 3167unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3168 if (RetVT.SimpleTy != MVT::v2i64) 3169 return 0; 3170 if ((Subtarget->hasNEON())) { 3171 return fastEmitInst_r(AArch64::FCVTZSv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3172 } 3173 return 0; 3174} 3175 3176unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3177 switch (VT.SimpleTy) { 3178 case MVT::f16: return fastEmit_ISD_FP_TO_SINT_MVT_f16_r(RetVT, Op0, Op0IsKill); 3179 case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0, Op0IsKill); 3180 case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0, Op0IsKill); 3181 case MVT::v4f16: return fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 3182 case MVT::v8f16: return fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 3183 case MVT::v2f32: return fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 3184 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 3185 case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 3186 default: return 0; 3187 } 3188} 3189 3190// FastEmit functions for ISD::FP_TO_UINT. 3191 3192unsigned fastEmit_ISD_FP_TO_UINT_MVT_f16_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 3193 if ((Subtarget->hasFullFP16())) { 3194 return fastEmitInst_r(AArch64::FCVTZUUWHr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 3195 } 3196 return 0; 3197} 3198 3199unsigned fastEmit_ISD_FP_TO_UINT_MVT_f16_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 3200 if ((Subtarget->hasFullFP16())) { 3201 return fastEmitInst_r(AArch64::FCVTZUUXHr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 3202 } 3203 return 0; 3204} 3205 3206unsigned fastEmit_ISD_FP_TO_UINT_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3207switch (RetVT.SimpleTy) { 3208 case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f16_MVT_i32_r(Op0, Op0IsKill); 3209 case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f16_MVT_i64_r(Op0, Op0IsKill); 3210 default: return 0; 3211} 3212} 3213 3214unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 3215 if ((Subtarget->hasFPARMv8())) { 3216 return fastEmitInst_r(AArch64::FCVTZUUWSr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 3217 } 3218 return 0; 3219} 3220 3221unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 3222 if ((Subtarget->hasFPARMv8())) { 3223 return fastEmitInst_r(AArch64::FCVTZUUXSr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 3224 } 3225 return 0; 3226} 3227 3228unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3229switch (RetVT.SimpleTy) { 3230 case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(Op0, Op0IsKill); 3231 case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(Op0, Op0IsKill); 3232 default: return 0; 3233} 3234} 3235 3236unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 3237 if ((Subtarget->hasFPARMv8())) { 3238 return fastEmitInst_r(AArch64::FCVTZUUWDr, &AArch64::GPR32RegClass, Op0, Op0IsKill); 3239 } 3240 return 0; 3241} 3242 3243unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 3244 if ((Subtarget->hasFPARMv8())) { 3245 return fastEmitInst_r(AArch64::FCVTZUUXDr, &AArch64::GPR64RegClass, Op0, Op0IsKill); 3246 } 3247 return 0; 3248} 3249 3250unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3251switch (RetVT.SimpleTy) { 3252 case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(Op0, Op0IsKill); 3253 case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(Op0, Op0IsKill); 3254 default: return 0; 3255} 3256} 3257 3258unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3259 if (RetVT.SimpleTy != MVT::v4i16) 3260 return 0; 3261 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3262 return fastEmitInst_r(AArch64::FCVTZUv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3263 } 3264 return 0; 3265} 3266 3267unsigned fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3268 if (RetVT.SimpleTy != MVT::v8i16) 3269 return 0; 3270 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3271 return fastEmitInst_r(AArch64::FCVTZUv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3272 } 3273 return 0; 3274} 3275 3276unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3277 if (RetVT.SimpleTy != MVT::v2i32) 3278 return 0; 3279 if ((Subtarget->hasNEON())) { 3280 return fastEmitInst_r(AArch64::FCVTZUv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3281 } 3282 return 0; 3283} 3284 3285unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3286 if (RetVT.SimpleTy != MVT::v4i32) 3287 return 0; 3288 if ((Subtarget->hasNEON())) { 3289 return fastEmitInst_r(AArch64::FCVTZUv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3290 } 3291 return 0; 3292} 3293 3294unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3295 if (RetVT.SimpleTy != MVT::v2i64) 3296 return 0; 3297 if ((Subtarget->hasNEON())) { 3298 return fastEmitInst_r(AArch64::FCVTZUv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3299 } 3300 return 0; 3301} 3302 3303unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3304 switch (VT.SimpleTy) { 3305 case MVT::f16: return fastEmit_ISD_FP_TO_UINT_MVT_f16_r(RetVT, Op0, Op0IsKill); 3306 case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0, Op0IsKill); 3307 case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0, Op0IsKill); 3308 case MVT::v4f16: return fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 3309 case MVT::v8f16: return fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 3310 case MVT::v2f32: return fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 3311 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 3312 case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 3313 default: return 0; 3314 } 3315} 3316 3317// FastEmit functions for ISD::FRINT. 3318 3319unsigned fastEmit_ISD_FRINT_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3320 if (RetVT.SimpleTy != MVT::f16) 3321 return 0; 3322 if ((Subtarget->hasFullFP16())) { 3323 return fastEmitInst_r(AArch64::FRINTXHr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 3324 } 3325 return 0; 3326} 3327 3328unsigned fastEmit_ISD_FRINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3329 if (RetVT.SimpleTy != MVT::f32) 3330 return 0; 3331 if ((Subtarget->hasFPARMv8())) { 3332 return fastEmitInst_r(AArch64::FRINTXSr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 3333 } 3334 return 0; 3335} 3336 3337unsigned fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3338 if (RetVT.SimpleTy != MVT::f64) 3339 return 0; 3340 if ((Subtarget->hasFPARMv8())) { 3341 return fastEmitInst_r(AArch64::FRINTXDr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3342 } 3343 return 0; 3344} 3345 3346unsigned fastEmit_ISD_FRINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3347 if (RetVT.SimpleTy != MVT::v4f16) 3348 return 0; 3349 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3350 return fastEmitInst_r(AArch64::FRINTXv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3351 } 3352 return 0; 3353} 3354 3355unsigned fastEmit_ISD_FRINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3356 if (RetVT.SimpleTy != MVT::v8f16) 3357 return 0; 3358 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3359 return fastEmitInst_r(AArch64::FRINTXv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3360 } 3361 return 0; 3362} 3363 3364unsigned fastEmit_ISD_FRINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3365 if (RetVT.SimpleTy != MVT::v2f32) 3366 return 0; 3367 if ((Subtarget->hasNEON())) { 3368 return fastEmitInst_r(AArch64::FRINTXv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3369 } 3370 return 0; 3371} 3372 3373unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3374 if (RetVT.SimpleTy != MVT::v4f32) 3375 return 0; 3376 if ((Subtarget->hasNEON())) { 3377 return fastEmitInst_r(AArch64::FRINTXv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3378 } 3379 return 0; 3380} 3381 3382unsigned fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3383 if (RetVT.SimpleTy != MVT::v2f64) 3384 return 0; 3385 if ((Subtarget->hasNEON())) { 3386 return fastEmitInst_r(AArch64::FRINTXv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3387 } 3388 return 0; 3389} 3390 3391unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3392 switch (VT.SimpleTy) { 3393 case MVT::f16: return fastEmit_ISD_FRINT_MVT_f16_r(RetVT, Op0, Op0IsKill); 3394 case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0, Op0IsKill); 3395 case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0, Op0IsKill); 3396 case MVT::v4f16: return fastEmit_ISD_FRINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 3397 case MVT::v8f16: return fastEmit_ISD_FRINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 3398 case MVT::v2f32: return fastEmit_ISD_FRINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 3399 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 3400 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 3401 default: return 0; 3402 } 3403} 3404 3405// FastEmit functions for ISD::FROUND. 3406 3407unsigned fastEmit_ISD_FROUND_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3408 if (RetVT.SimpleTy != MVT::f16) 3409 return 0; 3410 if ((Subtarget->hasFullFP16())) { 3411 return fastEmitInst_r(AArch64::FRINTAHr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 3412 } 3413 return 0; 3414} 3415 3416unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3417 if (RetVT.SimpleTy != MVT::f32) 3418 return 0; 3419 if ((Subtarget->hasFPARMv8())) { 3420 return fastEmitInst_r(AArch64::FRINTASr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 3421 } 3422 return 0; 3423} 3424 3425unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3426 if (RetVT.SimpleTy != MVT::f64) 3427 return 0; 3428 if ((Subtarget->hasFPARMv8())) { 3429 return fastEmitInst_r(AArch64::FRINTADr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3430 } 3431 return 0; 3432} 3433 3434unsigned fastEmit_ISD_FROUND_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3435 if (RetVT.SimpleTy != MVT::v4f16) 3436 return 0; 3437 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3438 return fastEmitInst_r(AArch64::FRINTAv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3439 } 3440 return 0; 3441} 3442 3443unsigned fastEmit_ISD_FROUND_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3444 if (RetVT.SimpleTy != MVT::v8f16) 3445 return 0; 3446 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3447 return fastEmitInst_r(AArch64::FRINTAv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3448 } 3449 return 0; 3450} 3451 3452unsigned fastEmit_ISD_FROUND_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3453 if (RetVT.SimpleTy != MVT::v2f32) 3454 return 0; 3455 if ((Subtarget->hasNEON())) { 3456 return fastEmitInst_r(AArch64::FRINTAv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3457 } 3458 return 0; 3459} 3460 3461unsigned fastEmit_ISD_FROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3462 if (RetVT.SimpleTy != MVT::v4f32) 3463 return 0; 3464 if ((Subtarget->hasNEON())) { 3465 return fastEmitInst_r(AArch64::FRINTAv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3466 } 3467 return 0; 3468} 3469 3470unsigned fastEmit_ISD_FROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3471 if (RetVT.SimpleTy != MVT::v2f64) 3472 return 0; 3473 if ((Subtarget->hasNEON())) { 3474 return fastEmitInst_r(AArch64::FRINTAv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3475 } 3476 return 0; 3477} 3478 3479unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3480 switch (VT.SimpleTy) { 3481 case MVT::f16: return fastEmit_ISD_FROUND_MVT_f16_r(RetVT, Op0, Op0IsKill); 3482 case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0, Op0IsKill); 3483 case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0, Op0IsKill); 3484 case MVT::v4f16: return fastEmit_ISD_FROUND_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 3485 case MVT::v8f16: return fastEmit_ISD_FROUND_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 3486 case MVT::v2f32: return fastEmit_ISD_FROUND_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 3487 case MVT::v4f32: return fastEmit_ISD_FROUND_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 3488 case MVT::v2f64: return fastEmit_ISD_FROUND_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 3489 default: return 0; 3490 } 3491} 3492 3493// FastEmit functions for ISD::FSQRT. 3494 3495unsigned fastEmit_ISD_FSQRT_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3496 if (RetVT.SimpleTy != MVT::f16) 3497 return 0; 3498 if ((Subtarget->hasFullFP16())) { 3499 return fastEmitInst_r(AArch64::FSQRTHr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 3500 } 3501 return 0; 3502} 3503 3504unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3505 if (RetVT.SimpleTy != MVT::f32) 3506 return 0; 3507 if ((Subtarget->hasFPARMv8())) { 3508 return fastEmitInst_r(AArch64::FSQRTSr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 3509 } 3510 return 0; 3511} 3512 3513unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3514 if (RetVT.SimpleTy != MVT::f64) 3515 return 0; 3516 if ((Subtarget->hasFPARMv8())) { 3517 return fastEmitInst_r(AArch64::FSQRTDr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3518 } 3519 return 0; 3520} 3521 3522unsigned fastEmit_ISD_FSQRT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3523 if (RetVT.SimpleTy != MVT::v4f16) 3524 return 0; 3525 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3526 return fastEmitInst_r(AArch64::FSQRTv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3527 } 3528 return 0; 3529} 3530 3531unsigned fastEmit_ISD_FSQRT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3532 if (RetVT.SimpleTy != MVT::v8f16) 3533 return 0; 3534 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3535 return fastEmitInst_r(AArch64::FSQRTv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3536 } 3537 return 0; 3538} 3539 3540unsigned fastEmit_ISD_FSQRT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3541 if (RetVT.SimpleTy != MVT::v2f32) 3542 return 0; 3543 if ((Subtarget->hasNEON())) { 3544 return fastEmitInst_r(AArch64::FSQRTv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3545 } 3546 return 0; 3547} 3548 3549unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3550 if (RetVT.SimpleTy != MVT::v4f32) 3551 return 0; 3552 if ((Subtarget->hasNEON())) { 3553 return fastEmitInst_r(AArch64::FSQRTv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3554 } 3555 return 0; 3556} 3557 3558unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3559 if (RetVT.SimpleTy != MVT::v2f64) 3560 return 0; 3561 if ((Subtarget->hasNEON())) { 3562 return fastEmitInst_r(AArch64::FSQRTv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3563 } 3564 return 0; 3565} 3566 3567unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3568 switch (VT.SimpleTy) { 3569 case MVT::f16: return fastEmit_ISD_FSQRT_MVT_f16_r(RetVT, Op0, Op0IsKill); 3570 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill); 3571 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill); 3572 case MVT::v4f16: return fastEmit_ISD_FSQRT_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 3573 case MVT::v8f16: return fastEmit_ISD_FSQRT_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 3574 case MVT::v2f32: return fastEmit_ISD_FSQRT_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 3575 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 3576 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 3577 default: return 0; 3578 } 3579} 3580 3581// FastEmit functions for ISD::FTRUNC. 3582 3583unsigned fastEmit_ISD_FTRUNC_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3584 if (RetVT.SimpleTy != MVT::f16) 3585 return 0; 3586 if ((Subtarget->hasFullFP16())) { 3587 return fastEmitInst_r(AArch64::FRINTZHr, &AArch64::FPR16RegClass, Op0, Op0IsKill); 3588 } 3589 return 0; 3590} 3591 3592unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3593 if (RetVT.SimpleTy != MVT::f32) 3594 return 0; 3595 if ((Subtarget->hasFPARMv8())) { 3596 return fastEmitInst_r(AArch64::FRINTZSr, &AArch64::FPR32RegClass, Op0, Op0IsKill); 3597 } 3598 return 0; 3599} 3600 3601unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3602 if (RetVT.SimpleTy != MVT::f64) 3603 return 0; 3604 if ((Subtarget->hasFPARMv8())) { 3605 return fastEmitInst_r(AArch64::FRINTZDr, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3606 } 3607 return 0; 3608} 3609 3610unsigned fastEmit_ISD_FTRUNC_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3611 if (RetVT.SimpleTy != MVT::v4f16) 3612 return 0; 3613 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3614 return fastEmitInst_r(AArch64::FRINTZv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3615 } 3616 return 0; 3617} 3618 3619unsigned fastEmit_ISD_FTRUNC_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3620 if (RetVT.SimpleTy != MVT::v8f16) 3621 return 0; 3622 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3623 return fastEmitInst_r(AArch64::FRINTZv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3624 } 3625 return 0; 3626} 3627 3628unsigned fastEmit_ISD_FTRUNC_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3629 if (RetVT.SimpleTy != MVT::v2f32) 3630 return 0; 3631 if ((Subtarget->hasNEON())) { 3632 return fastEmitInst_r(AArch64::FRINTZv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3633 } 3634 return 0; 3635} 3636 3637unsigned fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3638 if (RetVT.SimpleTy != MVT::v4f32) 3639 return 0; 3640 if ((Subtarget->hasNEON())) { 3641 return fastEmitInst_r(AArch64::FRINTZv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3642 } 3643 return 0; 3644} 3645 3646unsigned fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3647 if (RetVT.SimpleTy != MVT::v2f64) 3648 return 0; 3649 if ((Subtarget->hasNEON())) { 3650 return fastEmitInst_r(AArch64::FRINTZv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3651 } 3652 return 0; 3653} 3654 3655unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3656 switch (VT.SimpleTy) { 3657 case MVT::f16: return fastEmit_ISD_FTRUNC_MVT_f16_r(RetVT, Op0, Op0IsKill); 3658 case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill); 3659 case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0, Op0IsKill); 3660 case MVT::v4f16: return fastEmit_ISD_FTRUNC_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 3661 case MVT::v8f16: return fastEmit_ISD_FTRUNC_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 3662 case MVT::v2f32: return fastEmit_ISD_FTRUNC_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 3663 case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 3664 case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 3665 default: return 0; 3666 } 3667} 3668 3669// FastEmit functions for ISD::SINT_TO_FP. 3670 3671unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f16_r(unsigned Op0, bool Op0IsKill) { 3672 if ((Subtarget->hasFullFP16())) { 3673 return fastEmitInst_r(AArch64::SCVTFUWHri, &AArch64::FPR16RegClass, Op0, Op0IsKill); 3674 } 3675 return 0; 3676} 3677 3678unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 3679 if ((Subtarget->hasFPARMv8())) { 3680 return fastEmitInst_r(AArch64::SCVTFUWSri, &AArch64::FPR32RegClass, Op0, Op0IsKill); 3681 } 3682 return 0; 3683} 3684 3685unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 3686 if ((Subtarget->hasFPARMv8())) { 3687 return fastEmitInst_r(AArch64::SCVTFUWDri, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3688 } 3689 return 0; 3690} 3691 3692unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3693switch (RetVT.SimpleTy) { 3694 case MVT::f16: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f16_r(Op0, Op0IsKill); 3695 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill); 3696 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill); 3697 default: return 0; 3698} 3699} 3700 3701unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f16_r(unsigned Op0, bool Op0IsKill) { 3702 if ((Subtarget->hasFullFP16())) { 3703 return fastEmitInst_r(AArch64::SCVTFUXHri, &AArch64::FPR16RegClass, Op0, Op0IsKill); 3704 } 3705 return 0; 3706} 3707 3708unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 3709 if ((Subtarget->hasFPARMv8())) { 3710 return fastEmitInst_r(AArch64::SCVTFUXSri, &AArch64::FPR32RegClass, Op0, Op0IsKill); 3711 } 3712 return 0; 3713} 3714 3715unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 3716 if ((Subtarget->hasFPARMv8())) { 3717 return fastEmitInst_r(AArch64::SCVTFUXDri, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3718 } 3719 return 0; 3720} 3721 3722unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3723switch (RetVT.SimpleTy) { 3724 case MVT::f16: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f16_r(Op0, Op0IsKill); 3725 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Op0, Op0IsKill); 3726 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(Op0, Op0IsKill); 3727 default: return 0; 3728} 3729} 3730 3731unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3732 if (RetVT.SimpleTy != MVT::v4f16) 3733 return 0; 3734 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3735 return fastEmitInst_r(AArch64::SCVTFv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3736 } 3737 return 0; 3738} 3739 3740unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3741 if (RetVT.SimpleTy != MVT::v8f16) 3742 return 0; 3743 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3744 return fastEmitInst_r(AArch64::SCVTFv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3745 } 3746 return 0; 3747} 3748 3749unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3750 if (RetVT.SimpleTy != MVT::v2f32) 3751 return 0; 3752 if ((Subtarget->hasNEON())) { 3753 return fastEmitInst_r(AArch64::SCVTFv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3754 } 3755 return 0; 3756} 3757 3758unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3759 if (RetVT.SimpleTy != MVT::v4f32) 3760 return 0; 3761 if ((Subtarget->hasNEON())) { 3762 return fastEmitInst_r(AArch64::SCVTFv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3763 } 3764 return 0; 3765} 3766 3767unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3768 if (RetVT.SimpleTy != MVT::v2f64) 3769 return 0; 3770 if ((Subtarget->hasNEON())) { 3771 return fastEmitInst_r(AArch64::SCVTFv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3772 } 3773 return 0; 3774} 3775 3776unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3777 switch (VT.SimpleTy) { 3778 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill); 3779 case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0, Op0IsKill); 3780 case MVT::v4i16: return fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 3781 case MVT::v8i16: return fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 3782 case MVT::v2i32: return fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 3783 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 3784 case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 3785 default: return 0; 3786 } 3787} 3788 3789// FastEmit functions for ISD::TRUNCATE. 3790 3791unsigned fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3792 if (RetVT.SimpleTy != MVT::i32) 3793 return 0; 3794 return fastEmitInst_extractsubreg(RetVT, Op0, Op0IsKill, AArch64::sub_32); 3795} 3796 3797unsigned fastEmit_ISD_TRUNCATE_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3798 if (RetVT.SimpleTy != MVT::v8i8) 3799 return 0; 3800 if ((Subtarget->hasNEON())) { 3801 return fastEmitInst_r(AArch64::XTNv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3802 } 3803 return 0; 3804} 3805 3806unsigned fastEmit_ISD_TRUNCATE_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3807 if (RetVT.SimpleTy != MVT::v4i16) 3808 return 0; 3809 if ((Subtarget->hasNEON())) { 3810 return fastEmitInst_r(AArch64::XTNv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3811 } 3812 return 0; 3813} 3814 3815unsigned fastEmit_ISD_TRUNCATE_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3816 if (RetVT.SimpleTy != MVT::v2i32) 3817 return 0; 3818 if ((Subtarget->hasNEON())) { 3819 return fastEmitInst_r(AArch64::XTNv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3820 } 3821 return 0; 3822} 3823 3824unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3825 switch (VT.SimpleTy) { 3826 case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0, Op0IsKill); 3827 case MVT::v8i16: return fastEmit_ISD_TRUNCATE_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 3828 case MVT::v4i32: return fastEmit_ISD_TRUNCATE_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 3829 case MVT::v2i64: return fastEmit_ISD_TRUNCATE_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 3830 default: return 0; 3831 } 3832} 3833 3834// FastEmit functions for ISD::UINT_TO_FP. 3835 3836unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f16_r(unsigned Op0, bool Op0IsKill) { 3837 if ((Subtarget->hasFullFP16())) { 3838 return fastEmitInst_r(AArch64::UCVTFUWHri, &AArch64::FPR16RegClass, Op0, Op0IsKill); 3839 } 3840 return 0; 3841} 3842 3843unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 3844 if ((Subtarget->hasFPARMv8())) { 3845 return fastEmitInst_r(AArch64::UCVTFUWSri, &AArch64::FPR32RegClass, Op0, Op0IsKill); 3846 } 3847 return 0; 3848} 3849 3850unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 3851 if ((Subtarget->hasFPARMv8())) { 3852 return fastEmitInst_r(AArch64::UCVTFUWDri, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3853 } 3854 return 0; 3855} 3856 3857unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3858switch (RetVT.SimpleTy) { 3859 case MVT::f16: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f16_r(Op0, Op0IsKill); 3860 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill); 3861 case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill); 3862 default: return 0; 3863} 3864} 3865 3866unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f16_r(unsigned Op0, bool Op0IsKill) { 3867 if ((Subtarget->hasFullFP16())) { 3868 return fastEmitInst_r(AArch64::UCVTFUXHri, &AArch64::FPR16RegClass, Op0, Op0IsKill); 3869 } 3870 return 0; 3871} 3872 3873unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 3874 if ((Subtarget->hasFPARMv8())) { 3875 return fastEmitInst_r(AArch64::UCVTFUXSri, &AArch64::FPR32RegClass, Op0, Op0IsKill); 3876 } 3877 return 0; 3878} 3879 3880unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 3881 if ((Subtarget->hasFPARMv8())) { 3882 return fastEmitInst_r(AArch64::UCVTFUXDri, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3883 } 3884 return 0; 3885} 3886 3887unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3888switch (RetVT.SimpleTy) { 3889 case MVT::f16: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f16_r(Op0, Op0IsKill); 3890 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(Op0, Op0IsKill); 3891 case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(Op0, Op0IsKill); 3892 default: return 0; 3893} 3894} 3895 3896unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3897 if (RetVT.SimpleTy != MVT::v4f16) 3898 return 0; 3899 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3900 return fastEmitInst_r(AArch64::UCVTFv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3901 } 3902 return 0; 3903} 3904 3905unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3906 if (RetVT.SimpleTy != MVT::v8f16) 3907 return 0; 3908 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3909 return fastEmitInst_r(AArch64::UCVTFv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3910 } 3911 return 0; 3912} 3913 3914unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3915 if (RetVT.SimpleTy != MVT::v2f32) 3916 return 0; 3917 if ((Subtarget->hasNEON())) { 3918 return fastEmitInst_r(AArch64::UCVTFv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill); 3919 } 3920 return 0; 3921} 3922 3923unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3924 if (RetVT.SimpleTy != MVT::v4f32) 3925 return 0; 3926 if ((Subtarget->hasNEON())) { 3927 return fastEmitInst_r(AArch64::UCVTFv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3928 } 3929 return 0; 3930} 3931 3932unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 3933 if (RetVT.SimpleTy != MVT::v2f64) 3934 return 0; 3935 if ((Subtarget->hasNEON())) { 3936 return fastEmitInst_r(AArch64::UCVTFv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill); 3937 } 3938 return 0; 3939} 3940 3941unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 3942 switch (VT.SimpleTy) { 3943 case MVT::i32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill); 3944 case MVT::i64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_r(RetVT, Op0, Op0IsKill); 3945 case MVT::v4i16: return fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 3946 case MVT::v8i16: return fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 3947 case MVT::v2i32: return fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 3948 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 3949 case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 3950 default: return 0; 3951 } 3952} 3953 3954// Top-level FastEmit function. 3955 3956unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override { 3957 switch (Opcode) { 3958 case AArch64ISD::CALL: return fastEmit_AArch64ISD_CALL_r(VT, RetVT, Op0, Op0IsKill); 3959 case AArch64ISD::CMEQz: return fastEmit_AArch64ISD_CMEQz_r(VT, RetVT, Op0, Op0IsKill); 3960 case AArch64ISD::CMGEz: return fastEmit_AArch64ISD_CMGEz_r(VT, RetVT, Op0, Op0IsKill); 3961 case AArch64ISD::CMGTz: return fastEmit_AArch64ISD_CMGTz_r(VT, RetVT, Op0, Op0IsKill); 3962 case AArch64ISD::CMLEz: return fastEmit_AArch64ISD_CMLEz_r(VT, RetVT, Op0, Op0IsKill); 3963 case AArch64ISD::CMLTz: return fastEmit_AArch64ISD_CMLTz_r(VT, RetVT, Op0, Op0IsKill); 3964 case AArch64ISD::DUP: return fastEmit_AArch64ISD_DUP_r(VT, RetVT, Op0, Op0IsKill); 3965 case AArch64ISD::FCMEQz: return fastEmit_AArch64ISD_FCMEQz_r(VT, RetVT, Op0, Op0IsKill); 3966 case AArch64ISD::FCMGEz: return fastEmit_AArch64ISD_FCMGEz_r(VT, RetVT, Op0, Op0IsKill); 3967 case AArch64ISD::FCMGTz: return fastEmit_AArch64ISD_FCMGTz_r(VT, RetVT, Op0, Op0IsKill); 3968 case AArch64ISD::FCMLEz: return fastEmit_AArch64ISD_FCMLEz_r(VT, RetVT, Op0, Op0IsKill); 3969 case AArch64ISD::FCMLTz: return fastEmit_AArch64ISD_FCMLTz_r(VT, RetVT, Op0, Op0IsKill); 3970 case AArch64ISD::FRECPE: return fastEmit_AArch64ISD_FRECPE_r(VT, RetVT, Op0, Op0IsKill); 3971 case AArch64ISD::FRSQRTE: return fastEmit_AArch64ISD_FRSQRTE_r(VT, RetVT, Op0, Op0IsKill); 3972 case AArch64ISD::NEG: return fastEmit_AArch64ISD_NEG_r(VT, RetVT, Op0, Op0IsKill); 3973 case AArch64ISD::NOT: return fastEmit_AArch64ISD_NOT_r(VT, RetVT, Op0, Op0IsKill); 3974 case AArch64ISD::REV16: return fastEmit_AArch64ISD_REV16_r(VT, RetVT, Op0, Op0IsKill); 3975 case AArch64ISD::REV32: return fastEmit_AArch64ISD_REV32_r(VT, RetVT, Op0, Op0IsKill); 3976 case AArch64ISD::REV64: return fastEmit_AArch64ISD_REV64_r(VT, RetVT, Op0, Op0IsKill); 3977 case AArch64ISD::SITOF: return fastEmit_AArch64ISD_SITOF_r(VT, RetVT, Op0, Op0IsKill); 3978 case AArch64ISD::UITOF: return fastEmit_AArch64ISD_UITOF_r(VT, RetVT, Op0, Op0IsKill); 3979 case ISD::ABS: return fastEmit_ISD_ABS_r(VT, RetVT, Op0, Op0IsKill); 3980 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill); 3981 case ISD::BITREVERSE: return fastEmit_ISD_BITREVERSE_r(VT, RetVT, Op0, Op0IsKill); 3982 case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill); 3983 case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0, Op0IsKill); 3984 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill); 3985 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill); 3986 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill); 3987 case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill); 3988 case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill); 3989 case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill); 3990 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill); 3991 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill); 3992 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill); 3993 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill); 3994 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill); 3995 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill); 3996 case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0, Op0IsKill); 3997 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill); 3998 case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill); 3999 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill); 4000 case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0, Op0IsKill); 4001 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill); 4002 default: return 0; 4003 } 4004} 4005 4006// FastEmit functions for AArch64ISD::CMEQ. 4007 4008unsigned fastEmit_AArch64ISD_CMEQ_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4009 if (RetVT.SimpleTy != MVT::v8i8) 4010 return 0; 4011 if ((Subtarget->hasNEON())) { 4012 return fastEmitInst_rr(AArch64::CMEQv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4013 } 4014 return 0; 4015} 4016 4017unsigned fastEmit_AArch64ISD_CMEQ_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4018 if (RetVT.SimpleTy != MVT::v16i8) 4019 return 0; 4020 if ((Subtarget->hasNEON())) { 4021 return fastEmitInst_rr(AArch64::CMEQv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4022 } 4023 return 0; 4024} 4025 4026unsigned fastEmit_AArch64ISD_CMEQ_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4027 if (RetVT.SimpleTy != MVT::v4i16) 4028 return 0; 4029 if ((Subtarget->hasNEON())) { 4030 return fastEmitInst_rr(AArch64::CMEQv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4031 } 4032 return 0; 4033} 4034 4035unsigned fastEmit_AArch64ISD_CMEQ_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4036 if (RetVT.SimpleTy != MVT::v8i16) 4037 return 0; 4038 if ((Subtarget->hasNEON())) { 4039 return fastEmitInst_rr(AArch64::CMEQv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4040 } 4041 return 0; 4042} 4043 4044unsigned fastEmit_AArch64ISD_CMEQ_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4045 if (RetVT.SimpleTy != MVT::v2i32) 4046 return 0; 4047 if ((Subtarget->hasNEON())) { 4048 return fastEmitInst_rr(AArch64::CMEQv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4049 } 4050 return 0; 4051} 4052 4053unsigned fastEmit_AArch64ISD_CMEQ_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4054 if (RetVT.SimpleTy != MVT::v4i32) 4055 return 0; 4056 if ((Subtarget->hasNEON())) { 4057 return fastEmitInst_rr(AArch64::CMEQv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4058 } 4059 return 0; 4060} 4061 4062unsigned fastEmit_AArch64ISD_CMEQ_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4063 if (RetVT.SimpleTy != MVT::v1i64) 4064 return 0; 4065 if ((Subtarget->hasNEON())) { 4066 return fastEmitInst_rr(AArch64::CMEQv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4067 } 4068 return 0; 4069} 4070 4071unsigned fastEmit_AArch64ISD_CMEQ_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4072 if (RetVT.SimpleTy != MVT::v2i64) 4073 return 0; 4074 if ((Subtarget->hasNEON())) { 4075 return fastEmitInst_rr(AArch64::CMEQv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4076 } 4077 return 0; 4078} 4079 4080unsigned fastEmit_AArch64ISD_CMEQ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4081 switch (VT.SimpleTy) { 4082 case MVT::v8i8: return fastEmit_AArch64ISD_CMEQ_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4083 case MVT::v16i8: return fastEmit_AArch64ISD_CMEQ_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4084 case MVT::v4i16: return fastEmit_AArch64ISD_CMEQ_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4085 case MVT::v8i16: return fastEmit_AArch64ISD_CMEQ_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4086 case MVT::v2i32: return fastEmit_AArch64ISD_CMEQ_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4087 case MVT::v4i32: return fastEmit_AArch64ISD_CMEQ_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4088 case MVT::v1i64: return fastEmit_AArch64ISD_CMEQ_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4089 case MVT::v2i64: return fastEmit_AArch64ISD_CMEQ_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4090 default: return 0; 4091 } 4092} 4093 4094// FastEmit functions for AArch64ISD::CMGE. 4095 4096unsigned fastEmit_AArch64ISD_CMGE_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4097 if (RetVT.SimpleTy != MVT::v8i8) 4098 return 0; 4099 if ((Subtarget->hasNEON())) { 4100 return fastEmitInst_rr(AArch64::CMGEv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4101 } 4102 return 0; 4103} 4104 4105unsigned fastEmit_AArch64ISD_CMGE_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4106 if (RetVT.SimpleTy != MVT::v16i8) 4107 return 0; 4108 if ((Subtarget->hasNEON())) { 4109 return fastEmitInst_rr(AArch64::CMGEv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4110 } 4111 return 0; 4112} 4113 4114unsigned fastEmit_AArch64ISD_CMGE_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4115 if (RetVT.SimpleTy != MVT::v4i16) 4116 return 0; 4117 if ((Subtarget->hasNEON())) { 4118 return fastEmitInst_rr(AArch64::CMGEv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4119 } 4120 return 0; 4121} 4122 4123unsigned fastEmit_AArch64ISD_CMGE_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4124 if (RetVT.SimpleTy != MVT::v8i16) 4125 return 0; 4126 if ((Subtarget->hasNEON())) { 4127 return fastEmitInst_rr(AArch64::CMGEv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4128 } 4129 return 0; 4130} 4131 4132unsigned fastEmit_AArch64ISD_CMGE_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4133 if (RetVT.SimpleTy != MVT::v2i32) 4134 return 0; 4135 if ((Subtarget->hasNEON())) { 4136 return fastEmitInst_rr(AArch64::CMGEv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4137 } 4138 return 0; 4139} 4140 4141unsigned fastEmit_AArch64ISD_CMGE_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4142 if (RetVT.SimpleTy != MVT::v4i32) 4143 return 0; 4144 if ((Subtarget->hasNEON())) { 4145 return fastEmitInst_rr(AArch64::CMGEv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4146 } 4147 return 0; 4148} 4149 4150unsigned fastEmit_AArch64ISD_CMGE_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4151 if (RetVT.SimpleTy != MVT::v1i64) 4152 return 0; 4153 if ((Subtarget->hasNEON())) { 4154 return fastEmitInst_rr(AArch64::CMGEv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4155 } 4156 return 0; 4157} 4158 4159unsigned fastEmit_AArch64ISD_CMGE_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4160 if (RetVT.SimpleTy != MVT::v2i64) 4161 return 0; 4162 if ((Subtarget->hasNEON())) { 4163 return fastEmitInst_rr(AArch64::CMGEv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4164 } 4165 return 0; 4166} 4167 4168unsigned fastEmit_AArch64ISD_CMGE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4169 switch (VT.SimpleTy) { 4170 case MVT::v8i8: return fastEmit_AArch64ISD_CMGE_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4171 case MVT::v16i8: return fastEmit_AArch64ISD_CMGE_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4172 case MVT::v4i16: return fastEmit_AArch64ISD_CMGE_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4173 case MVT::v8i16: return fastEmit_AArch64ISD_CMGE_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4174 case MVT::v2i32: return fastEmit_AArch64ISD_CMGE_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4175 case MVT::v4i32: return fastEmit_AArch64ISD_CMGE_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4176 case MVT::v1i64: return fastEmit_AArch64ISD_CMGE_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4177 case MVT::v2i64: return fastEmit_AArch64ISD_CMGE_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4178 default: return 0; 4179 } 4180} 4181 4182// FastEmit functions for AArch64ISD::CMGT. 4183 4184unsigned fastEmit_AArch64ISD_CMGT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4185 if (RetVT.SimpleTy != MVT::v8i8) 4186 return 0; 4187 if ((Subtarget->hasNEON())) { 4188 return fastEmitInst_rr(AArch64::CMGTv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4189 } 4190 return 0; 4191} 4192 4193unsigned fastEmit_AArch64ISD_CMGT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4194 if (RetVT.SimpleTy != MVT::v16i8) 4195 return 0; 4196 if ((Subtarget->hasNEON())) { 4197 return fastEmitInst_rr(AArch64::CMGTv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4198 } 4199 return 0; 4200} 4201 4202unsigned fastEmit_AArch64ISD_CMGT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4203 if (RetVT.SimpleTy != MVT::v4i16) 4204 return 0; 4205 if ((Subtarget->hasNEON())) { 4206 return fastEmitInst_rr(AArch64::CMGTv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4207 } 4208 return 0; 4209} 4210 4211unsigned fastEmit_AArch64ISD_CMGT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4212 if (RetVT.SimpleTy != MVT::v8i16) 4213 return 0; 4214 if ((Subtarget->hasNEON())) { 4215 return fastEmitInst_rr(AArch64::CMGTv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4216 } 4217 return 0; 4218} 4219 4220unsigned fastEmit_AArch64ISD_CMGT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4221 if (RetVT.SimpleTy != MVT::v2i32) 4222 return 0; 4223 if ((Subtarget->hasNEON())) { 4224 return fastEmitInst_rr(AArch64::CMGTv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4225 } 4226 return 0; 4227} 4228 4229unsigned fastEmit_AArch64ISD_CMGT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4230 if (RetVT.SimpleTy != MVT::v4i32) 4231 return 0; 4232 if ((Subtarget->hasNEON())) { 4233 return fastEmitInst_rr(AArch64::CMGTv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4234 } 4235 return 0; 4236} 4237 4238unsigned fastEmit_AArch64ISD_CMGT_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4239 if (RetVT.SimpleTy != MVT::v1i64) 4240 return 0; 4241 if ((Subtarget->hasNEON())) { 4242 return fastEmitInst_rr(AArch64::CMGTv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4243 } 4244 return 0; 4245} 4246 4247unsigned fastEmit_AArch64ISD_CMGT_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4248 if (RetVT.SimpleTy != MVT::v2i64) 4249 return 0; 4250 if ((Subtarget->hasNEON())) { 4251 return fastEmitInst_rr(AArch64::CMGTv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4252 } 4253 return 0; 4254} 4255 4256unsigned fastEmit_AArch64ISD_CMGT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4257 switch (VT.SimpleTy) { 4258 case MVT::v8i8: return fastEmit_AArch64ISD_CMGT_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4259 case MVT::v16i8: return fastEmit_AArch64ISD_CMGT_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4260 case MVT::v4i16: return fastEmit_AArch64ISD_CMGT_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4261 case MVT::v8i16: return fastEmit_AArch64ISD_CMGT_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4262 case MVT::v2i32: return fastEmit_AArch64ISD_CMGT_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4263 case MVT::v4i32: return fastEmit_AArch64ISD_CMGT_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4264 case MVT::v1i64: return fastEmit_AArch64ISD_CMGT_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4265 case MVT::v2i64: return fastEmit_AArch64ISD_CMGT_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4266 default: return 0; 4267 } 4268} 4269 4270// FastEmit functions for AArch64ISD::CMHI. 4271 4272unsigned fastEmit_AArch64ISD_CMHI_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4273 if (RetVT.SimpleTy != MVT::v8i8) 4274 return 0; 4275 if ((Subtarget->hasNEON())) { 4276 return fastEmitInst_rr(AArch64::CMHIv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4277 } 4278 return 0; 4279} 4280 4281unsigned fastEmit_AArch64ISD_CMHI_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4282 if (RetVT.SimpleTy != MVT::v16i8) 4283 return 0; 4284 if ((Subtarget->hasNEON())) { 4285 return fastEmitInst_rr(AArch64::CMHIv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4286 } 4287 return 0; 4288} 4289 4290unsigned fastEmit_AArch64ISD_CMHI_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4291 if (RetVT.SimpleTy != MVT::v4i16) 4292 return 0; 4293 if ((Subtarget->hasNEON())) { 4294 return fastEmitInst_rr(AArch64::CMHIv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4295 } 4296 return 0; 4297} 4298 4299unsigned fastEmit_AArch64ISD_CMHI_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4300 if (RetVT.SimpleTy != MVT::v8i16) 4301 return 0; 4302 if ((Subtarget->hasNEON())) { 4303 return fastEmitInst_rr(AArch64::CMHIv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4304 } 4305 return 0; 4306} 4307 4308unsigned fastEmit_AArch64ISD_CMHI_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4309 if (RetVT.SimpleTy != MVT::v2i32) 4310 return 0; 4311 if ((Subtarget->hasNEON())) { 4312 return fastEmitInst_rr(AArch64::CMHIv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4313 } 4314 return 0; 4315} 4316 4317unsigned fastEmit_AArch64ISD_CMHI_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4318 if (RetVT.SimpleTy != MVT::v4i32) 4319 return 0; 4320 if ((Subtarget->hasNEON())) { 4321 return fastEmitInst_rr(AArch64::CMHIv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4322 } 4323 return 0; 4324} 4325 4326unsigned fastEmit_AArch64ISD_CMHI_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4327 if (RetVT.SimpleTy != MVT::v1i64) 4328 return 0; 4329 if ((Subtarget->hasNEON())) { 4330 return fastEmitInst_rr(AArch64::CMHIv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4331 } 4332 return 0; 4333} 4334 4335unsigned fastEmit_AArch64ISD_CMHI_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4336 if (RetVT.SimpleTy != MVT::v2i64) 4337 return 0; 4338 if ((Subtarget->hasNEON())) { 4339 return fastEmitInst_rr(AArch64::CMHIv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4340 } 4341 return 0; 4342} 4343 4344unsigned fastEmit_AArch64ISD_CMHI_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4345 switch (VT.SimpleTy) { 4346 case MVT::v8i8: return fastEmit_AArch64ISD_CMHI_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4347 case MVT::v16i8: return fastEmit_AArch64ISD_CMHI_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4348 case MVT::v4i16: return fastEmit_AArch64ISD_CMHI_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4349 case MVT::v8i16: return fastEmit_AArch64ISD_CMHI_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4350 case MVT::v2i32: return fastEmit_AArch64ISD_CMHI_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4351 case MVT::v4i32: return fastEmit_AArch64ISD_CMHI_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4352 case MVT::v1i64: return fastEmit_AArch64ISD_CMHI_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4353 case MVT::v2i64: return fastEmit_AArch64ISD_CMHI_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4354 default: return 0; 4355 } 4356} 4357 4358// FastEmit functions for AArch64ISD::CMHS. 4359 4360unsigned fastEmit_AArch64ISD_CMHS_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4361 if (RetVT.SimpleTy != MVT::v8i8) 4362 return 0; 4363 if ((Subtarget->hasNEON())) { 4364 return fastEmitInst_rr(AArch64::CMHSv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4365 } 4366 return 0; 4367} 4368 4369unsigned fastEmit_AArch64ISD_CMHS_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4370 if (RetVT.SimpleTy != MVT::v16i8) 4371 return 0; 4372 if ((Subtarget->hasNEON())) { 4373 return fastEmitInst_rr(AArch64::CMHSv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4374 } 4375 return 0; 4376} 4377 4378unsigned fastEmit_AArch64ISD_CMHS_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4379 if (RetVT.SimpleTy != MVT::v4i16) 4380 return 0; 4381 if ((Subtarget->hasNEON())) { 4382 return fastEmitInst_rr(AArch64::CMHSv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4383 } 4384 return 0; 4385} 4386 4387unsigned fastEmit_AArch64ISD_CMHS_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4388 if (RetVT.SimpleTy != MVT::v8i16) 4389 return 0; 4390 if ((Subtarget->hasNEON())) { 4391 return fastEmitInst_rr(AArch64::CMHSv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4392 } 4393 return 0; 4394} 4395 4396unsigned fastEmit_AArch64ISD_CMHS_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4397 if (RetVT.SimpleTy != MVT::v2i32) 4398 return 0; 4399 if ((Subtarget->hasNEON())) { 4400 return fastEmitInst_rr(AArch64::CMHSv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4401 } 4402 return 0; 4403} 4404 4405unsigned fastEmit_AArch64ISD_CMHS_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4406 if (RetVT.SimpleTy != MVT::v4i32) 4407 return 0; 4408 if ((Subtarget->hasNEON())) { 4409 return fastEmitInst_rr(AArch64::CMHSv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4410 } 4411 return 0; 4412} 4413 4414unsigned fastEmit_AArch64ISD_CMHS_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4415 if (RetVT.SimpleTy != MVT::v1i64) 4416 return 0; 4417 if ((Subtarget->hasNEON())) { 4418 return fastEmitInst_rr(AArch64::CMHSv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4419 } 4420 return 0; 4421} 4422 4423unsigned fastEmit_AArch64ISD_CMHS_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4424 if (RetVT.SimpleTy != MVT::v2i64) 4425 return 0; 4426 if ((Subtarget->hasNEON())) { 4427 return fastEmitInst_rr(AArch64::CMHSv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4428 } 4429 return 0; 4430} 4431 4432unsigned fastEmit_AArch64ISD_CMHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4433 switch (VT.SimpleTy) { 4434 case MVT::v8i8: return fastEmit_AArch64ISD_CMHS_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4435 case MVT::v16i8: return fastEmit_AArch64ISD_CMHS_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4436 case MVT::v4i16: return fastEmit_AArch64ISD_CMHS_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4437 case MVT::v8i16: return fastEmit_AArch64ISD_CMHS_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4438 case MVT::v2i32: return fastEmit_AArch64ISD_CMHS_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4439 case MVT::v4i32: return fastEmit_AArch64ISD_CMHS_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4440 case MVT::v1i64: return fastEmit_AArch64ISD_CMHS_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4441 case MVT::v2i64: return fastEmit_AArch64ISD_CMHS_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4442 default: return 0; 4443 } 4444} 4445 4446// FastEmit functions for AArch64ISD::FCMEQ. 4447 4448unsigned fastEmit_AArch64ISD_FCMEQ_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4449 if (RetVT.SimpleTy != MVT::i32) 4450 return 0; 4451 if ((Subtarget->hasNEON())) { 4452 return fastEmitInst_rr(AArch64::FCMEQ32, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4453 } 4454 return 0; 4455} 4456 4457unsigned fastEmit_AArch64ISD_FCMEQ_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4458 if (RetVT.SimpleTy != MVT::i64) 4459 return 0; 4460 if ((Subtarget->hasNEON())) { 4461 return fastEmitInst_rr(AArch64::FCMEQ64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4462 } 4463 return 0; 4464} 4465 4466unsigned fastEmit_AArch64ISD_FCMEQ_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4467 if (RetVT.SimpleTy != MVT::v4i16) 4468 return 0; 4469 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 4470 return fastEmitInst_rr(AArch64::FCMEQv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4471 } 4472 return 0; 4473} 4474 4475unsigned fastEmit_AArch64ISD_FCMEQ_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4476 if (RetVT.SimpleTy != MVT::v8i16) 4477 return 0; 4478 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 4479 return fastEmitInst_rr(AArch64::FCMEQv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4480 } 4481 return 0; 4482} 4483 4484unsigned fastEmit_AArch64ISD_FCMEQ_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4485 if (RetVT.SimpleTy != MVT::v2i32) 4486 return 0; 4487 if ((Subtarget->hasNEON())) { 4488 return fastEmitInst_rr(AArch64::FCMEQv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4489 } 4490 return 0; 4491} 4492 4493unsigned fastEmit_AArch64ISD_FCMEQ_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4494 if (RetVT.SimpleTy != MVT::v4i32) 4495 return 0; 4496 if ((Subtarget->hasNEON())) { 4497 return fastEmitInst_rr(AArch64::FCMEQv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4498 } 4499 return 0; 4500} 4501 4502unsigned fastEmit_AArch64ISD_FCMEQ_MVT_v1f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4503 if (RetVT.SimpleTy != MVT::v1i64) 4504 return 0; 4505 if ((Subtarget->hasNEON())) { 4506 return fastEmitInst_rr(AArch64::FCMEQ64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4507 } 4508 return 0; 4509} 4510 4511unsigned fastEmit_AArch64ISD_FCMEQ_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4512 if (RetVT.SimpleTy != MVT::v2i64) 4513 return 0; 4514 if ((Subtarget->hasNEON())) { 4515 return fastEmitInst_rr(AArch64::FCMEQv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4516 } 4517 return 0; 4518} 4519 4520unsigned fastEmit_AArch64ISD_FCMEQ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4521 switch (VT.SimpleTy) { 4522 case MVT::f32: return fastEmit_AArch64ISD_FCMEQ_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4523 case MVT::f64: return fastEmit_AArch64ISD_FCMEQ_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4524 case MVT::v4f16: return fastEmit_AArch64ISD_FCMEQ_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4525 case MVT::v8f16: return fastEmit_AArch64ISD_FCMEQ_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4526 case MVT::v2f32: return fastEmit_AArch64ISD_FCMEQ_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4527 case MVT::v4f32: return fastEmit_AArch64ISD_FCMEQ_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4528 case MVT::v1f64: return fastEmit_AArch64ISD_FCMEQ_MVT_v1f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4529 case MVT::v2f64: return fastEmit_AArch64ISD_FCMEQ_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4530 default: return 0; 4531 } 4532} 4533 4534// FastEmit functions for AArch64ISD::FCMGE. 4535 4536unsigned fastEmit_AArch64ISD_FCMGE_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4537 if (RetVT.SimpleTy != MVT::i32) 4538 return 0; 4539 if ((Subtarget->hasNEON())) { 4540 return fastEmitInst_rr(AArch64::FCMGE32, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4541 } 4542 return 0; 4543} 4544 4545unsigned fastEmit_AArch64ISD_FCMGE_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4546 if (RetVT.SimpleTy != MVT::i64) 4547 return 0; 4548 if ((Subtarget->hasNEON())) { 4549 return fastEmitInst_rr(AArch64::FCMGE64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4550 } 4551 return 0; 4552} 4553 4554unsigned fastEmit_AArch64ISD_FCMGE_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4555 if (RetVT.SimpleTy != MVT::v4i16) 4556 return 0; 4557 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 4558 return fastEmitInst_rr(AArch64::FCMGEv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4559 } 4560 return 0; 4561} 4562 4563unsigned fastEmit_AArch64ISD_FCMGE_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4564 if (RetVT.SimpleTy != MVT::v8i16) 4565 return 0; 4566 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 4567 return fastEmitInst_rr(AArch64::FCMGEv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4568 } 4569 return 0; 4570} 4571 4572unsigned fastEmit_AArch64ISD_FCMGE_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4573 if (RetVT.SimpleTy != MVT::v2i32) 4574 return 0; 4575 if ((Subtarget->hasNEON())) { 4576 return fastEmitInst_rr(AArch64::FCMGEv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4577 } 4578 return 0; 4579} 4580 4581unsigned fastEmit_AArch64ISD_FCMGE_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4582 if (RetVT.SimpleTy != MVT::v4i32) 4583 return 0; 4584 if ((Subtarget->hasNEON())) { 4585 return fastEmitInst_rr(AArch64::FCMGEv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4586 } 4587 return 0; 4588} 4589 4590unsigned fastEmit_AArch64ISD_FCMGE_MVT_v1f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4591 if (RetVT.SimpleTy != MVT::v1i64) 4592 return 0; 4593 if ((Subtarget->hasNEON())) { 4594 return fastEmitInst_rr(AArch64::FCMGE64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4595 } 4596 return 0; 4597} 4598 4599unsigned fastEmit_AArch64ISD_FCMGE_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4600 if (RetVT.SimpleTy != MVT::v2i64) 4601 return 0; 4602 if ((Subtarget->hasNEON())) { 4603 return fastEmitInst_rr(AArch64::FCMGEv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4604 } 4605 return 0; 4606} 4607 4608unsigned fastEmit_AArch64ISD_FCMGE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4609 switch (VT.SimpleTy) { 4610 case MVT::f32: return fastEmit_AArch64ISD_FCMGE_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4611 case MVT::f64: return fastEmit_AArch64ISD_FCMGE_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4612 case MVT::v4f16: return fastEmit_AArch64ISD_FCMGE_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4613 case MVT::v8f16: return fastEmit_AArch64ISD_FCMGE_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4614 case MVT::v2f32: return fastEmit_AArch64ISD_FCMGE_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4615 case MVT::v4f32: return fastEmit_AArch64ISD_FCMGE_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4616 case MVT::v1f64: return fastEmit_AArch64ISD_FCMGE_MVT_v1f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4617 case MVT::v2f64: return fastEmit_AArch64ISD_FCMGE_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4618 default: return 0; 4619 } 4620} 4621 4622// FastEmit functions for AArch64ISD::FCMGT. 4623 4624unsigned fastEmit_AArch64ISD_FCMGT_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4625 if (RetVT.SimpleTy != MVT::i32) 4626 return 0; 4627 if ((Subtarget->hasNEON())) { 4628 return fastEmitInst_rr(AArch64::FCMGT32, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4629 } 4630 return 0; 4631} 4632 4633unsigned fastEmit_AArch64ISD_FCMGT_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4634 if (RetVT.SimpleTy != MVT::i64) 4635 return 0; 4636 if ((Subtarget->hasNEON())) { 4637 return fastEmitInst_rr(AArch64::FCMGT64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4638 } 4639 return 0; 4640} 4641 4642unsigned fastEmit_AArch64ISD_FCMGT_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4643 if (RetVT.SimpleTy != MVT::v4i16) 4644 return 0; 4645 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 4646 return fastEmitInst_rr(AArch64::FCMGTv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4647 } 4648 return 0; 4649} 4650 4651unsigned fastEmit_AArch64ISD_FCMGT_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4652 if (RetVT.SimpleTy != MVT::v8i16) 4653 return 0; 4654 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 4655 return fastEmitInst_rr(AArch64::FCMGTv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4656 } 4657 return 0; 4658} 4659 4660unsigned fastEmit_AArch64ISD_FCMGT_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4661 if (RetVT.SimpleTy != MVT::v2i32) 4662 return 0; 4663 if ((Subtarget->hasNEON())) { 4664 return fastEmitInst_rr(AArch64::FCMGTv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4665 } 4666 return 0; 4667} 4668 4669unsigned fastEmit_AArch64ISD_FCMGT_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4670 if (RetVT.SimpleTy != MVT::v4i32) 4671 return 0; 4672 if ((Subtarget->hasNEON())) { 4673 return fastEmitInst_rr(AArch64::FCMGTv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4674 } 4675 return 0; 4676} 4677 4678unsigned fastEmit_AArch64ISD_FCMGT_MVT_v1f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4679 if (RetVT.SimpleTy != MVT::v1i64) 4680 return 0; 4681 if ((Subtarget->hasNEON())) { 4682 return fastEmitInst_rr(AArch64::FCMGT64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4683 } 4684 return 0; 4685} 4686 4687unsigned fastEmit_AArch64ISD_FCMGT_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4688 if (RetVT.SimpleTy != MVT::v2i64) 4689 return 0; 4690 if ((Subtarget->hasNEON())) { 4691 return fastEmitInst_rr(AArch64::FCMGTv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4692 } 4693 return 0; 4694} 4695 4696unsigned fastEmit_AArch64ISD_FCMGT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4697 switch (VT.SimpleTy) { 4698 case MVT::f32: return fastEmit_AArch64ISD_FCMGT_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4699 case MVT::f64: return fastEmit_AArch64ISD_FCMGT_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4700 case MVT::v4f16: return fastEmit_AArch64ISD_FCMGT_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4701 case MVT::v8f16: return fastEmit_AArch64ISD_FCMGT_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4702 case MVT::v2f32: return fastEmit_AArch64ISD_FCMGT_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4703 case MVT::v4f32: return fastEmit_AArch64ISD_FCMGT_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4704 case MVT::v1f64: return fastEmit_AArch64ISD_FCMGT_MVT_v1f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4705 case MVT::v2f64: return fastEmit_AArch64ISD_FCMGT_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4706 default: return 0; 4707 } 4708} 4709 4710// FastEmit functions for AArch64ISD::FCMP. 4711 4712unsigned fastEmit_AArch64ISD_FCMP_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4713 if (RetVT.SimpleTy != MVT::isVoid) 4714 return 0; 4715 if ((Subtarget->hasFullFP16())) { 4716 return fastEmitInst_rr(AArch64::FCMPHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4717 } 4718 return 0; 4719} 4720 4721unsigned fastEmit_AArch64ISD_FCMP_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4722 if (RetVT.SimpleTy != MVT::isVoid) 4723 return 0; 4724 if ((Subtarget->hasFPARMv8())) { 4725 return fastEmitInst_rr(AArch64::FCMPSrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4726 } 4727 return 0; 4728} 4729 4730unsigned fastEmit_AArch64ISD_FCMP_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4731 if (RetVT.SimpleTy != MVT::isVoid) 4732 return 0; 4733 if ((Subtarget->hasFPARMv8())) { 4734 return fastEmitInst_rr(AArch64::FCMPDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4735 } 4736 return 0; 4737} 4738 4739unsigned fastEmit_AArch64ISD_FCMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4740 switch (VT.SimpleTy) { 4741 case MVT::f16: return fastEmit_AArch64ISD_FCMP_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4742 case MVT::f32: return fastEmit_AArch64ISD_FCMP_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4743 case MVT::f64: return fastEmit_AArch64ISD_FCMP_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4744 default: return 0; 4745 } 4746} 4747 4748// FastEmit functions for AArch64ISD::FRECPS. 4749 4750unsigned fastEmit_AArch64ISD_FRECPS_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4751 if (RetVT.SimpleTy != MVT::f32) 4752 return 0; 4753 return fastEmitInst_rr(AArch64::FRECPS32, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4754} 4755 4756unsigned fastEmit_AArch64ISD_FRECPS_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4757 if (RetVT.SimpleTy != MVT::f64) 4758 return 0; 4759 return fastEmitInst_rr(AArch64::FRECPS64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4760} 4761 4762unsigned fastEmit_AArch64ISD_FRECPS_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4763 if (RetVT.SimpleTy != MVT::v2f32) 4764 return 0; 4765 return fastEmitInst_rr(AArch64::FRECPSv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4766} 4767 4768unsigned fastEmit_AArch64ISD_FRECPS_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4769 if (RetVT.SimpleTy != MVT::v4f32) 4770 return 0; 4771 return fastEmitInst_rr(AArch64::FRECPSv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4772} 4773 4774unsigned fastEmit_AArch64ISD_FRECPS_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4775 if (RetVT.SimpleTy != MVT::v2f64) 4776 return 0; 4777 return fastEmitInst_rr(AArch64::FRECPSv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4778} 4779 4780unsigned fastEmit_AArch64ISD_FRECPS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4781 switch (VT.SimpleTy) { 4782 case MVT::f32: return fastEmit_AArch64ISD_FRECPS_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4783 case MVT::f64: return fastEmit_AArch64ISD_FRECPS_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4784 case MVT::v2f32: return fastEmit_AArch64ISD_FRECPS_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4785 case MVT::v4f32: return fastEmit_AArch64ISD_FRECPS_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4786 case MVT::v2f64: return fastEmit_AArch64ISD_FRECPS_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4787 default: return 0; 4788 } 4789} 4790 4791// FastEmit functions for AArch64ISD::FRSQRTS. 4792 4793unsigned fastEmit_AArch64ISD_FRSQRTS_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4794 if (RetVT.SimpleTy != MVT::f32) 4795 return 0; 4796 return fastEmitInst_rr(AArch64::FRSQRTS32, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4797} 4798 4799unsigned fastEmit_AArch64ISD_FRSQRTS_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4800 if (RetVT.SimpleTy != MVT::f64) 4801 return 0; 4802 return fastEmitInst_rr(AArch64::FRSQRTS64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4803} 4804 4805unsigned fastEmit_AArch64ISD_FRSQRTS_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4806 if (RetVT.SimpleTy != MVT::v2f32) 4807 return 0; 4808 return fastEmitInst_rr(AArch64::FRSQRTSv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4809} 4810 4811unsigned fastEmit_AArch64ISD_FRSQRTS_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4812 if (RetVT.SimpleTy != MVT::v4f32) 4813 return 0; 4814 return fastEmitInst_rr(AArch64::FRSQRTSv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4815} 4816 4817unsigned fastEmit_AArch64ISD_FRSQRTS_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4818 if (RetVT.SimpleTy != MVT::v2f64) 4819 return 0; 4820 return fastEmitInst_rr(AArch64::FRSQRTSv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4821} 4822 4823unsigned fastEmit_AArch64ISD_FRSQRTS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4824 switch (VT.SimpleTy) { 4825 case MVT::f32: return fastEmit_AArch64ISD_FRSQRTS_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4826 case MVT::f64: return fastEmit_AArch64ISD_FRSQRTS_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4827 case MVT::v2f32: return fastEmit_AArch64ISD_FRSQRTS_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4828 case MVT::v4f32: return fastEmit_AArch64ISD_FRSQRTS_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4829 case MVT::v2f64: return fastEmit_AArch64ISD_FRSQRTS_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4830 default: return 0; 4831 } 4832} 4833 4834// FastEmit functions for AArch64ISD::SMULL. 4835 4836unsigned fastEmit_AArch64ISD_SMULL_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4837 if (RetVT.SimpleTy != MVT::v8i16) 4838 return 0; 4839 return fastEmitInst_rr(AArch64::SMULLv8i8_v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4840} 4841 4842unsigned fastEmit_AArch64ISD_SMULL_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4843 if (RetVT.SimpleTy != MVT::v4i32) 4844 return 0; 4845 return fastEmitInst_rr(AArch64::SMULLv4i16_v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4846} 4847 4848unsigned fastEmit_AArch64ISD_SMULL_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4849 if (RetVT.SimpleTy != MVT::v2i64) 4850 return 0; 4851 return fastEmitInst_rr(AArch64::SMULLv2i32_v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4852} 4853 4854unsigned fastEmit_AArch64ISD_SMULL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4855 switch (VT.SimpleTy) { 4856 case MVT::v8i8: return fastEmit_AArch64ISD_SMULL_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4857 case MVT::v4i16: return fastEmit_AArch64ISD_SMULL_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4858 case MVT::v2i32: return fastEmit_AArch64ISD_SMULL_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4859 default: return 0; 4860 } 4861} 4862 4863// FastEmit functions for AArch64ISD::TRN1. 4864 4865unsigned fastEmit_AArch64ISD_TRN1_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4866 if (RetVT.SimpleTy != MVT::v8i8) 4867 return 0; 4868 if ((Subtarget->hasNEON())) { 4869 return fastEmitInst_rr(AArch64::TRN1v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4870 } 4871 return 0; 4872} 4873 4874unsigned fastEmit_AArch64ISD_TRN1_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4875 if (RetVT.SimpleTy != MVT::v16i8) 4876 return 0; 4877 if ((Subtarget->hasNEON())) { 4878 return fastEmitInst_rr(AArch64::TRN1v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4879 } 4880 return 0; 4881} 4882 4883unsigned fastEmit_AArch64ISD_TRN1_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4884 if (RetVT.SimpleTy != MVT::v4i16) 4885 return 0; 4886 if ((Subtarget->hasNEON())) { 4887 return fastEmitInst_rr(AArch64::TRN1v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4888 } 4889 return 0; 4890} 4891 4892unsigned fastEmit_AArch64ISD_TRN1_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4893 if (RetVT.SimpleTy != MVT::v8i16) 4894 return 0; 4895 if ((Subtarget->hasNEON())) { 4896 return fastEmitInst_rr(AArch64::TRN1v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4897 } 4898 return 0; 4899} 4900 4901unsigned fastEmit_AArch64ISD_TRN1_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4902 if (RetVT.SimpleTy != MVT::v2i32) 4903 return 0; 4904 if ((Subtarget->hasNEON())) { 4905 return fastEmitInst_rr(AArch64::TRN1v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4906 } 4907 return 0; 4908} 4909 4910unsigned fastEmit_AArch64ISD_TRN1_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4911 if (RetVT.SimpleTy != MVT::v4i32) 4912 return 0; 4913 if ((Subtarget->hasNEON())) { 4914 return fastEmitInst_rr(AArch64::TRN1v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4915 } 4916 return 0; 4917} 4918 4919unsigned fastEmit_AArch64ISD_TRN1_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4920 if (RetVT.SimpleTy != MVT::v2i64) 4921 return 0; 4922 if ((Subtarget->hasNEON())) { 4923 return fastEmitInst_rr(AArch64::TRN1v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4924 } 4925 return 0; 4926} 4927 4928unsigned fastEmit_AArch64ISD_TRN1_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4929 if (RetVT.SimpleTy != MVT::v4f16) 4930 return 0; 4931 if ((Subtarget->hasNEON())) { 4932 return fastEmitInst_rr(AArch64::TRN1v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4933 } 4934 return 0; 4935} 4936 4937unsigned fastEmit_AArch64ISD_TRN1_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4938 if (RetVT.SimpleTy != MVT::v8f16) 4939 return 0; 4940 if ((Subtarget->hasNEON())) { 4941 return fastEmitInst_rr(AArch64::TRN1v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4942 } 4943 return 0; 4944} 4945 4946unsigned fastEmit_AArch64ISD_TRN1_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4947 if (RetVT.SimpleTy != MVT::v2f32) 4948 return 0; 4949 if ((Subtarget->hasNEON())) { 4950 return fastEmitInst_rr(AArch64::TRN1v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4951 } 4952 return 0; 4953} 4954 4955unsigned fastEmit_AArch64ISD_TRN1_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4956 if (RetVT.SimpleTy != MVT::v4f32) 4957 return 0; 4958 if ((Subtarget->hasNEON())) { 4959 return fastEmitInst_rr(AArch64::TRN1v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4960 } 4961 return 0; 4962} 4963 4964unsigned fastEmit_AArch64ISD_TRN1_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4965 if (RetVT.SimpleTy != MVT::v2f64) 4966 return 0; 4967 if ((Subtarget->hasNEON())) { 4968 return fastEmitInst_rr(AArch64::TRN1v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4969 } 4970 return 0; 4971} 4972 4973unsigned fastEmit_AArch64ISD_TRN1_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4974 switch (VT.SimpleTy) { 4975 case MVT::v8i8: return fastEmit_AArch64ISD_TRN1_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4976 case MVT::v16i8: return fastEmit_AArch64ISD_TRN1_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4977 case MVT::v4i16: return fastEmit_AArch64ISD_TRN1_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4978 case MVT::v8i16: return fastEmit_AArch64ISD_TRN1_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4979 case MVT::v2i32: return fastEmit_AArch64ISD_TRN1_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4980 case MVT::v4i32: return fastEmit_AArch64ISD_TRN1_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4981 case MVT::v2i64: return fastEmit_AArch64ISD_TRN1_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4982 case MVT::v4f16: return fastEmit_AArch64ISD_TRN1_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4983 case MVT::v8f16: return fastEmit_AArch64ISD_TRN1_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4984 case MVT::v2f32: return fastEmit_AArch64ISD_TRN1_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4985 case MVT::v4f32: return fastEmit_AArch64ISD_TRN1_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4986 case MVT::v2f64: return fastEmit_AArch64ISD_TRN1_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4987 default: return 0; 4988 } 4989} 4990 4991// FastEmit functions for AArch64ISD::TRN2. 4992 4993unsigned fastEmit_AArch64ISD_TRN2_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4994 if (RetVT.SimpleTy != MVT::v8i8) 4995 return 0; 4996 if ((Subtarget->hasNEON())) { 4997 return fastEmitInst_rr(AArch64::TRN2v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4998 } 4999 return 0; 5000} 5001 5002unsigned fastEmit_AArch64ISD_TRN2_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5003 if (RetVT.SimpleTy != MVT::v16i8) 5004 return 0; 5005 if ((Subtarget->hasNEON())) { 5006 return fastEmitInst_rr(AArch64::TRN2v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5007 } 5008 return 0; 5009} 5010 5011unsigned fastEmit_AArch64ISD_TRN2_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5012 if (RetVT.SimpleTy != MVT::v4i16) 5013 return 0; 5014 if ((Subtarget->hasNEON())) { 5015 return fastEmitInst_rr(AArch64::TRN2v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5016 } 5017 return 0; 5018} 5019 5020unsigned fastEmit_AArch64ISD_TRN2_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5021 if (RetVT.SimpleTy != MVT::v8i16) 5022 return 0; 5023 if ((Subtarget->hasNEON())) { 5024 return fastEmitInst_rr(AArch64::TRN2v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5025 } 5026 return 0; 5027} 5028 5029unsigned fastEmit_AArch64ISD_TRN2_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5030 if (RetVT.SimpleTy != MVT::v2i32) 5031 return 0; 5032 if ((Subtarget->hasNEON())) { 5033 return fastEmitInst_rr(AArch64::TRN2v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5034 } 5035 return 0; 5036} 5037 5038unsigned fastEmit_AArch64ISD_TRN2_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5039 if (RetVT.SimpleTy != MVT::v4i32) 5040 return 0; 5041 if ((Subtarget->hasNEON())) { 5042 return fastEmitInst_rr(AArch64::TRN2v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5043 } 5044 return 0; 5045} 5046 5047unsigned fastEmit_AArch64ISD_TRN2_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5048 if (RetVT.SimpleTy != MVT::v2i64) 5049 return 0; 5050 if ((Subtarget->hasNEON())) { 5051 return fastEmitInst_rr(AArch64::TRN2v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5052 } 5053 return 0; 5054} 5055 5056unsigned fastEmit_AArch64ISD_TRN2_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5057 if (RetVT.SimpleTy != MVT::v4f16) 5058 return 0; 5059 if ((Subtarget->hasNEON())) { 5060 return fastEmitInst_rr(AArch64::TRN2v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5061 } 5062 return 0; 5063} 5064 5065unsigned fastEmit_AArch64ISD_TRN2_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5066 if (RetVT.SimpleTy != MVT::v8f16) 5067 return 0; 5068 if ((Subtarget->hasNEON())) { 5069 return fastEmitInst_rr(AArch64::TRN2v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5070 } 5071 return 0; 5072} 5073 5074unsigned fastEmit_AArch64ISD_TRN2_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5075 if (RetVT.SimpleTy != MVT::v2f32) 5076 return 0; 5077 if ((Subtarget->hasNEON())) { 5078 return fastEmitInst_rr(AArch64::TRN2v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5079 } 5080 return 0; 5081} 5082 5083unsigned fastEmit_AArch64ISD_TRN2_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5084 if (RetVT.SimpleTy != MVT::v4f32) 5085 return 0; 5086 if ((Subtarget->hasNEON())) { 5087 return fastEmitInst_rr(AArch64::TRN2v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5088 } 5089 return 0; 5090} 5091 5092unsigned fastEmit_AArch64ISD_TRN2_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5093 if (RetVT.SimpleTy != MVT::v2f64) 5094 return 0; 5095 if ((Subtarget->hasNEON())) { 5096 return fastEmitInst_rr(AArch64::TRN2v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5097 } 5098 return 0; 5099} 5100 5101unsigned fastEmit_AArch64ISD_TRN2_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5102 switch (VT.SimpleTy) { 5103 case MVT::v8i8: return fastEmit_AArch64ISD_TRN2_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5104 case MVT::v16i8: return fastEmit_AArch64ISD_TRN2_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5105 case MVT::v4i16: return fastEmit_AArch64ISD_TRN2_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5106 case MVT::v8i16: return fastEmit_AArch64ISD_TRN2_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5107 case MVT::v2i32: return fastEmit_AArch64ISD_TRN2_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5108 case MVT::v4i32: return fastEmit_AArch64ISD_TRN2_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5109 case MVT::v2i64: return fastEmit_AArch64ISD_TRN2_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5110 case MVT::v4f16: return fastEmit_AArch64ISD_TRN2_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5111 case MVT::v8f16: return fastEmit_AArch64ISD_TRN2_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5112 case MVT::v2f32: return fastEmit_AArch64ISD_TRN2_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5113 case MVT::v4f32: return fastEmit_AArch64ISD_TRN2_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5114 case MVT::v2f64: return fastEmit_AArch64ISD_TRN2_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5115 default: return 0; 5116 } 5117} 5118 5119// FastEmit functions for AArch64ISD::UMULL. 5120 5121unsigned fastEmit_AArch64ISD_UMULL_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5122 if (RetVT.SimpleTy != MVT::v8i16) 5123 return 0; 5124 return fastEmitInst_rr(AArch64::UMULLv8i8_v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5125} 5126 5127unsigned fastEmit_AArch64ISD_UMULL_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5128 if (RetVT.SimpleTy != MVT::v4i32) 5129 return 0; 5130 return fastEmitInst_rr(AArch64::UMULLv4i16_v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5131} 5132 5133unsigned fastEmit_AArch64ISD_UMULL_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5134 if (RetVT.SimpleTy != MVT::v2i64) 5135 return 0; 5136 return fastEmitInst_rr(AArch64::UMULLv2i32_v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5137} 5138 5139unsigned fastEmit_AArch64ISD_UMULL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5140 switch (VT.SimpleTy) { 5141 case MVT::v8i8: return fastEmit_AArch64ISD_UMULL_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5142 case MVT::v4i16: return fastEmit_AArch64ISD_UMULL_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5143 case MVT::v2i32: return fastEmit_AArch64ISD_UMULL_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5144 default: return 0; 5145 } 5146} 5147 5148// FastEmit functions for AArch64ISD::UZP1. 5149 5150unsigned fastEmit_AArch64ISD_UZP1_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5151 if (RetVT.SimpleTy != MVT::v8i8) 5152 return 0; 5153 if ((Subtarget->hasNEON())) { 5154 return fastEmitInst_rr(AArch64::UZP1v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5155 } 5156 return 0; 5157} 5158 5159unsigned fastEmit_AArch64ISD_UZP1_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5160 if (RetVT.SimpleTy != MVT::v16i8) 5161 return 0; 5162 if ((Subtarget->hasNEON())) { 5163 return fastEmitInst_rr(AArch64::UZP1v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5164 } 5165 return 0; 5166} 5167 5168unsigned fastEmit_AArch64ISD_UZP1_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5169 if (RetVT.SimpleTy != MVT::v4i16) 5170 return 0; 5171 if ((Subtarget->hasNEON())) { 5172 return fastEmitInst_rr(AArch64::UZP1v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5173 } 5174 return 0; 5175} 5176 5177unsigned fastEmit_AArch64ISD_UZP1_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5178 if (RetVT.SimpleTy != MVT::v8i16) 5179 return 0; 5180 if ((Subtarget->hasNEON())) { 5181 return fastEmitInst_rr(AArch64::UZP1v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5182 } 5183 return 0; 5184} 5185 5186unsigned fastEmit_AArch64ISD_UZP1_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5187 if (RetVT.SimpleTy != MVT::v2i32) 5188 return 0; 5189 if ((Subtarget->hasNEON())) { 5190 return fastEmitInst_rr(AArch64::UZP1v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5191 } 5192 return 0; 5193} 5194 5195unsigned fastEmit_AArch64ISD_UZP1_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5196 if (RetVT.SimpleTy != MVT::v4i32) 5197 return 0; 5198 if ((Subtarget->hasNEON())) { 5199 return fastEmitInst_rr(AArch64::UZP1v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5200 } 5201 return 0; 5202} 5203 5204unsigned fastEmit_AArch64ISD_UZP1_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5205 if (RetVT.SimpleTy != MVT::v2i64) 5206 return 0; 5207 if ((Subtarget->hasNEON())) { 5208 return fastEmitInst_rr(AArch64::UZP1v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5209 } 5210 return 0; 5211} 5212 5213unsigned fastEmit_AArch64ISD_UZP1_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5214 if (RetVT.SimpleTy != MVT::v4f16) 5215 return 0; 5216 if ((Subtarget->hasNEON())) { 5217 return fastEmitInst_rr(AArch64::UZP1v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5218 } 5219 return 0; 5220} 5221 5222unsigned fastEmit_AArch64ISD_UZP1_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5223 if (RetVT.SimpleTy != MVT::v8f16) 5224 return 0; 5225 if ((Subtarget->hasNEON())) { 5226 return fastEmitInst_rr(AArch64::UZP1v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5227 } 5228 return 0; 5229} 5230 5231unsigned fastEmit_AArch64ISD_UZP1_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5232 if (RetVT.SimpleTy != MVT::v2f32) 5233 return 0; 5234 if ((Subtarget->hasNEON())) { 5235 return fastEmitInst_rr(AArch64::UZP1v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5236 } 5237 return 0; 5238} 5239 5240unsigned fastEmit_AArch64ISD_UZP1_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5241 if (RetVT.SimpleTy != MVT::v4f32) 5242 return 0; 5243 if ((Subtarget->hasNEON())) { 5244 return fastEmitInst_rr(AArch64::UZP1v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5245 } 5246 return 0; 5247} 5248 5249unsigned fastEmit_AArch64ISD_UZP1_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5250 if (RetVT.SimpleTy != MVT::v2f64) 5251 return 0; 5252 if ((Subtarget->hasNEON())) { 5253 return fastEmitInst_rr(AArch64::UZP1v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5254 } 5255 return 0; 5256} 5257 5258unsigned fastEmit_AArch64ISD_UZP1_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5259 switch (VT.SimpleTy) { 5260 case MVT::v8i8: return fastEmit_AArch64ISD_UZP1_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5261 case MVT::v16i8: return fastEmit_AArch64ISD_UZP1_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5262 case MVT::v4i16: return fastEmit_AArch64ISD_UZP1_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5263 case MVT::v8i16: return fastEmit_AArch64ISD_UZP1_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5264 case MVT::v2i32: return fastEmit_AArch64ISD_UZP1_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5265 case MVT::v4i32: return fastEmit_AArch64ISD_UZP1_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5266 case MVT::v2i64: return fastEmit_AArch64ISD_UZP1_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5267 case MVT::v4f16: return fastEmit_AArch64ISD_UZP1_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5268 case MVT::v8f16: return fastEmit_AArch64ISD_UZP1_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5269 case MVT::v2f32: return fastEmit_AArch64ISD_UZP1_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5270 case MVT::v4f32: return fastEmit_AArch64ISD_UZP1_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5271 case MVT::v2f64: return fastEmit_AArch64ISD_UZP1_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5272 default: return 0; 5273 } 5274} 5275 5276// FastEmit functions for AArch64ISD::UZP2. 5277 5278unsigned fastEmit_AArch64ISD_UZP2_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5279 if (RetVT.SimpleTy != MVT::v8i8) 5280 return 0; 5281 if ((Subtarget->hasNEON())) { 5282 return fastEmitInst_rr(AArch64::UZP2v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5283 } 5284 return 0; 5285} 5286 5287unsigned fastEmit_AArch64ISD_UZP2_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5288 if (RetVT.SimpleTy != MVT::v16i8) 5289 return 0; 5290 if ((Subtarget->hasNEON())) { 5291 return fastEmitInst_rr(AArch64::UZP2v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5292 } 5293 return 0; 5294} 5295 5296unsigned fastEmit_AArch64ISD_UZP2_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5297 if (RetVT.SimpleTy != MVT::v4i16) 5298 return 0; 5299 if ((Subtarget->hasNEON())) { 5300 return fastEmitInst_rr(AArch64::UZP2v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5301 } 5302 return 0; 5303} 5304 5305unsigned fastEmit_AArch64ISD_UZP2_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5306 if (RetVT.SimpleTy != MVT::v8i16) 5307 return 0; 5308 if ((Subtarget->hasNEON())) { 5309 return fastEmitInst_rr(AArch64::UZP2v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5310 } 5311 return 0; 5312} 5313 5314unsigned fastEmit_AArch64ISD_UZP2_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5315 if (RetVT.SimpleTy != MVT::v2i32) 5316 return 0; 5317 if ((Subtarget->hasNEON())) { 5318 return fastEmitInst_rr(AArch64::UZP2v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5319 } 5320 return 0; 5321} 5322 5323unsigned fastEmit_AArch64ISD_UZP2_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5324 if (RetVT.SimpleTy != MVT::v4i32) 5325 return 0; 5326 if ((Subtarget->hasNEON())) { 5327 return fastEmitInst_rr(AArch64::UZP2v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5328 } 5329 return 0; 5330} 5331 5332unsigned fastEmit_AArch64ISD_UZP2_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5333 if (RetVT.SimpleTy != MVT::v2i64) 5334 return 0; 5335 if ((Subtarget->hasNEON())) { 5336 return fastEmitInst_rr(AArch64::UZP2v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5337 } 5338 return 0; 5339} 5340 5341unsigned fastEmit_AArch64ISD_UZP2_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5342 if (RetVT.SimpleTy != MVT::v4f16) 5343 return 0; 5344 if ((Subtarget->hasNEON())) { 5345 return fastEmitInst_rr(AArch64::UZP2v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5346 } 5347 return 0; 5348} 5349 5350unsigned fastEmit_AArch64ISD_UZP2_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5351 if (RetVT.SimpleTy != MVT::v8f16) 5352 return 0; 5353 if ((Subtarget->hasNEON())) { 5354 return fastEmitInst_rr(AArch64::UZP2v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5355 } 5356 return 0; 5357} 5358 5359unsigned fastEmit_AArch64ISD_UZP2_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5360 if (RetVT.SimpleTy != MVT::v2f32) 5361 return 0; 5362 if ((Subtarget->hasNEON())) { 5363 return fastEmitInst_rr(AArch64::UZP2v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5364 } 5365 return 0; 5366} 5367 5368unsigned fastEmit_AArch64ISD_UZP2_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5369 if (RetVT.SimpleTy != MVT::v4f32) 5370 return 0; 5371 if ((Subtarget->hasNEON())) { 5372 return fastEmitInst_rr(AArch64::UZP2v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5373 } 5374 return 0; 5375} 5376 5377unsigned fastEmit_AArch64ISD_UZP2_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5378 if (RetVT.SimpleTy != MVT::v2f64) 5379 return 0; 5380 if ((Subtarget->hasNEON())) { 5381 return fastEmitInst_rr(AArch64::UZP2v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5382 } 5383 return 0; 5384} 5385 5386unsigned fastEmit_AArch64ISD_UZP2_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5387 switch (VT.SimpleTy) { 5388 case MVT::v8i8: return fastEmit_AArch64ISD_UZP2_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5389 case MVT::v16i8: return fastEmit_AArch64ISD_UZP2_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5390 case MVT::v4i16: return fastEmit_AArch64ISD_UZP2_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5391 case MVT::v8i16: return fastEmit_AArch64ISD_UZP2_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5392 case MVT::v2i32: return fastEmit_AArch64ISD_UZP2_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5393 case MVT::v4i32: return fastEmit_AArch64ISD_UZP2_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5394 case MVT::v2i64: return fastEmit_AArch64ISD_UZP2_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5395 case MVT::v4f16: return fastEmit_AArch64ISD_UZP2_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5396 case MVT::v8f16: return fastEmit_AArch64ISD_UZP2_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5397 case MVT::v2f32: return fastEmit_AArch64ISD_UZP2_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5398 case MVT::v4f32: return fastEmit_AArch64ISD_UZP2_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5399 case MVT::v2f64: return fastEmit_AArch64ISD_UZP2_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5400 default: return 0; 5401 } 5402} 5403 5404// FastEmit functions for AArch64ISD::ZIP1. 5405 5406unsigned fastEmit_AArch64ISD_ZIP1_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5407 if (RetVT.SimpleTy != MVT::v8i8) 5408 return 0; 5409 if ((Subtarget->hasNEON())) { 5410 return fastEmitInst_rr(AArch64::ZIP1v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5411 } 5412 return 0; 5413} 5414 5415unsigned fastEmit_AArch64ISD_ZIP1_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5416 if (RetVT.SimpleTy != MVT::v16i8) 5417 return 0; 5418 if ((Subtarget->hasNEON())) { 5419 return fastEmitInst_rr(AArch64::ZIP1v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5420 } 5421 return 0; 5422} 5423 5424unsigned fastEmit_AArch64ISD_ZIP1_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5425 if (RetVT.SimpleTy != MVT::v4i16) 5426 return 0; 5427 if ((Subtarget->hasNEON())) { 5428 return fastEmitInst_rr(AArch64::ZIP1v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5429 } 5430 return 0; 5431} 5432 5433unsigned fastEmit_AArch64ISD_ZIP1_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5434 if (RetVT.SimpleTy != MVT::v8i16) 5435 return 0; 5436 if ((Subtarget->hasNEON())) { 5437 return fastEmitInst_rr(AArch64::ZIP1v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5438 } 5439 return 0; 5440} 5441 5442unsigned fastEmit_AArch64ISD_ZIP1_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5443 if (RetVT.SimpleTy != MVT::v2i32) 5444 return 0; 5445 if ((Subtarget->hasNEON())) { 5446 return fastEmitInst_rr(AArch64::ZIP1v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5447 } 5448 return 0; 5449} 5450 5451unsigned fastEmit_AArch64ISD_ZIP1_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5452 if (RetVT.SimpleTy != MVT::v4i32) 5453 return 0; 5454 if ((Subtarget->hasNEON())) { 5455 return fastEmitInst_rr(AArch64::ZIP1v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5456 } 5457 return 0; 5458} 5459 5460unsigned fastEmit_AArch64ISD_ZIP1_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5461 if (RetVT.SimpleTy != MVT::v2i64) 5462 return 0; 5463 if ((Subtarget->hasNEON())) { 5464 return fastEmitInst_rr(AArch64::ZIP1v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5465 } 5466 return 0; 5467} 5468 5469unsigned fastEmit_AArch64ISD_ZIP1_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5470 if (RetVT.SimpleTy != MVT::v4f16) 5471 return 0; 5472 if ((Subtarget->hasNEON())) { 5473 return fastEmitInst_rr(AArch64::ZIP1v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5474 } 5475 return 0; 5476} 5477 5478unsigned fastEmit_AArch64ISD_ZIP1_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5479 if (RetVT.SimpleTy != MVT::v8f16) 5480 return 0; 5481 if ((Subtarget->hasNEON())) { 5482 return fastEmitInst_rr(AArch64::ZIP1v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5483 } 5484 return 0; 5485} 5486 5487unsigned fastEmit_AArch64ISD_ZIP1_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5488 if (RetVT.SimpleTy != MVT::v2f32) 5489 return 0; 5490 if ((Subtarget->hasNEON())) { 5491 return fastEmitInst_rr(AArch64::ZIP1v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5492 } 5493 return 0; 5494} 5495 5496unsigned fastEmit_AArch64ISD_ZIP1_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5497 if (RetVT.SimpleTy != MVT::v4f32) 5498 return 0; 5499 if ((Subtarget->hasNEON())) { 5500 return fastEmitInst_rr(AArch64::ZIP1v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5501 } 5502 return 0; 5503} 5504 5505unsigned fastEmit_AArch64ISD_ZIP1_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5506 if (RetVT.SimpleTy != MVT::v2f64) 5507 return 0; 5508 if ((Subtarget->hasNEON())) { 5509 return fastEmitInst_rr(AArch64::ZIP1v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5510 } 5511 return 0; 5512} 5513 5514unsigned fastEmit_AArch64ISD_ZIP1_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5515 switch (VT.SimpleTy) { 5516 case MVT::v8i8: return fastEmit_AArch64ISD_ZIP1_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5517 case MVT::v16i8: return fastEmit_AArch64ISD_ZIP1_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5518 case MVT::v4i16: return fastEmit_AArch64ISD_ZIP1_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5519 case MVT::v8i16: return fastEmit_AArch64ISD_ZIP1_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5520 case MVT::v2i32: return fastEmit_AArch64ISD_ZIP1_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5521 case MVT::v4i32: return fastEmit_AArch64ISD_ZIP1_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5522 case MVT::v2i64: return fastEmit_AArch64ISD_ZIP1_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5523 case MVT::v4f16: return fastEmit_AArch64ISD_ZIP1_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5524 case MVT::v8f16: return fastEmit_AArch64ISD_ZIP1_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5525 case MVT::v2f32: return fastEmit_AArch64ISD_ZIP1_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5526 case MVT::v4f32: return fastEmit_AArch64ISD_ZIP1_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5527 case MVT::v2f64: return fastEmit_AArch64ISD_ZIP1_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5528 default: return 0; 5529 } 5530} 5531 5532// FastEmit functions for AArch64ISD::ZIP2. 5533 5534unsigned fastEmit_AArch64ISD_ZIP2_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5535 if (RetVT.SimpleTy != MVT::v8i8) 5536 return 0; 5537 if ((Subtarget->hasNEON())) { 5538 return fastEmitInst_rr(AArch64::ZIP2v8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5539 } 5540 return 0; 5541} 5542 5543unsigned fastEmit_AArch64ISD_ZIP2_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5544 if (RetVT.SimpleTy != MVT::v16i8) 5545 return 0; 5546 if ((Subtarget->hasNEON())) { 5547 return fastEmitInst_rr(AArch64::ZIP2v16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5548 } 5549 return 0; 5550} 5551 5552unsigned fastEmit_AArch64ISD_ZIP2_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5553 if (RetVT.SimpleTy != MVT::v4i16) 5554 return 0; 5555 if ((Subtarget->hasNEON())) { 5556 return fastEmitInst_rr(AArch64::ZIP2v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5557 } 5558 return 0; 5559} 5560 5561unsigned fastEmit_AArch64ISD_ZIP2_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5562 if (RetVT.SimpleTy != MVT::v8i16) 5563 return 0; 5564 if ((Subtarget->hasNEON())) { 5565 return fastEmitInst_rr(AArch64::ZIP2v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5566 } 5567 return 0; 5568} 5569 5570unsigned fastEmit_AArch64ISD_ZIP2_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5571 if (RetVT.SimpleTy != MVT::v2i32) 5572 return 0; 5573 if ((Subtarget->hasNEON())) { 5574 return fastEmitInst_rr(AArch64::ZIP2v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5575 } 5576 return 0; 5577} 5578 5579unsigned fastEmit_AArch64ISD_ZIP2_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5580 if (RetVT.SimpleTy != MVT::v4i32) 5581 return 0; 5582 if ((Subtarget->hasNEON())) { 5583 return fastEmitInst_rr(AArch64::ZIP2v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5584 } 5585 return 0; 5586} 5587 5588unsigned fastEmit_AArch64ISD_ZIP2_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5589 if (RetVT.SimpleTy != MVT::v2i64) 5590 return 0; 5591 if ((Subtarget->hasNEON())) { 5592 return fastEmitInst_rr(AArch64::ZIP2v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5593 } 5594 return 0; 5595} 5596 5597unsigned fastEmit_AArch64ISD_ZIP2_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5598 if (RetVT.SimpleTy != MVT::v4f16) 5599 return 0; 5600 if ((Subtarget->hasNEON())) { 5601 return fastEmitInst_rr(AArch64::ZIP2v4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5602 } 5603 return 0; 5604} 5605 5606unsigned fastEmit_AArch64ISD_ZIP2_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5607 if (RetVT.SimpleTy != MVT::v8f16) 5608 return 0; 5609 if ((Subtarget->hasNEON())) { 5610 return fastEmitInst_rr(AArch64::ZIP2v8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5611 } 5612 return 0; 5613} 5614 5615unsigned fastEmit_AArch64ISD_ZIP2_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5616 if (RetVT.SimpleTy != MVT::v2f32) 5617 return 0; 5618 if ((Subtarget->hasNEON())) { 5619 return fastEmitInst_rr(AArch64::ZIP2v2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5620 } 5621 return 0; 5622} 5623 5624unsigned fastEmit_AArch64ISD_ZIP2_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5625 if (RetVT.SimpleTy != MVT::v4f32) 5626 return 0; 5627 if ((Subtarget->hasNEON())) { 5628 return fastEmitInst_rr(AArch64::ZIP2v4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5629 } 5630 return 0; 5631} 5632 5633unsigned fastEmit_AArch64ISD_ZIP2_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5634 if (RetVT.SimpleTy != MVT::v2f64) 5635 return 0; 5636 if ((Subtarget->hasNEON())) { 5637 return fastEmitInst_rr(AArch64::ZIP2v2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5638 } 5639 return 0; 5640} 5641 5642unsigned fastEmit_AArch64ISD_ZIP2_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5643 switch (VT.SimpleTy) { 5644 case MVT::v8i8: return fastEmit_AArch64ISD_ZIP2_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5645 case MVT::v16i8: return fastEmit_AArch64ISD_ZIP2_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5646 case MVT::v4i16: return fastEmit_AArch64ISD_ZIP2_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5647 case MVT::v8i16: return fastEmit_AArch64ISD_ZIP2_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5648 case MVT::v2i32: return fastEmit_AArch64ISD_ZIP2_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5649 case MVT::v4i32: return fastEmit_AArch64ISD_ZIP2_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5650 case MVT::v2i64: return fastEmit_AArch64ISD_ZIP2_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5651 case MVT::v4f16: return fastEmit_AArch64ISD_ZIP2_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5652 case MVT::v8f16: return fastEmit_AArch64ISD_ZIP2_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5653 case MVT::v2f32: return fastEmit_AArch64ISD_ZIP2_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5654 case MVT::v4f32: return fastEmit_AArch64ISD_ZIP2_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5655 case MVT::v2f64: return fastEmit_AArch64ISD_ZIP2_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5656 default: return 0; 5657 } 5658} 5659 5660// FastEmit functions for ISD::ADD. 5661 5662unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5663 if (RetVT.SimpleTy != MVT::i32) 5664 return 0; 5665 return fastEmitInst_rr(AArch64::ADDWrr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5666} 5667 5668unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5669 if (RetVT.SimpleTy != MVT::i64) 5670 return 0; 5671 return fastEmitInst_rr(AArch64::ADDXrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5672} 5673 5674unsigned fastEmit_ISD_ADD_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5675 if (RetVT.SimpleTy != MVT::v8i8) 5676 return 0; 5677 if ((Subtarget->hasNEON())) { 5678 return fastEmitInst_rr(AArch64::ADDv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5679 } 5680 return 0; 5681} 5682 5683unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5684 if (RetVT.SimpleTy != MVT::v16i8) 5685 return 0; 5686 if ((Subtarget->hasNEON())) { 5687 return fastEmitInst_rr(AArch64::ADDv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5688 } 5689 return 0; 5690} 5691 5692unsigned fastEmit_ISD_ADD_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5693 if (RetVT.SimpleTy != MVT::v4i16) 5694 return 0; 5695 if ((Subtarget->hasNEON())) { 5696 return fastEmitInst_rr(AArch64::ADDv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5697 } 5698 return 0; 5699} 5700 5701unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5702 if (RetVT.SimpleTy != MVT::v8i16) 5703 return 0; 5704 if ((Subtarget->hasNEON())) { 5705 return fastEmitInst_rr(AArch64::ADDv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5706 } 5707 return 0; 5708} 5709 5710unsigned fastEmit_ISD_ADD_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5711 if (RetVT.SimpleTy != MVT::v2i32) 5712 return 0; 5713 if ((Subtarget->hasNEON())) { 5714 return fastEmitInst_rr(AArch64::ADDv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5715 } 5716 return 0; 5717} 5718 5719unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5720 if (RetVT.SimpleTy != MVT::v4i32) 5721 return 0; 5722 if ((Subtarget->hasNEON())) { 5723 return fastEmitInst_rr(AArch64::ADDv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5724 } 5725 return 0; 5726} 5727 5728unsigned fastEmit_ISD_ADD_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5729 if (RetVT.SimpleTy != MVT::v1i64) 5730 return 0; 5731 if ((Subtarget->hasNEON())) { 5732 return fastEmitInst_rr(AArch64::ADDv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5733 } 5734 return 0; 5735} 5736 5737unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5738 if (RetVT.SimpleTy != MVT::v2i64) 5739 return 0; 5740 if ((Subtarget->hasNEON())) { 5741 return fastEmitInst_rr(AArch64::ADDv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5742 } 5743 return 0; 5744} 5745 5746unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5747 switch (VT.SimpleTy) { 5748 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5749 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5750 case MVT::v8i8: return fastEmit_ISD_ADD_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5751 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5752 case MVT::v4i16: return fastEmit_ISD_ADD_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5753 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5754 case MVT::v2i32: return fastEmit_ISD_ADD_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5755 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5756 case MVT::v1i64: return fastEmit_ISD_ADD_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5757 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5758 default: return 0; 5759 } 5760} 5761 5762// FastEmit functions for ISD::AND. 5763 5764unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5765 if (RetVT.SimpleTy != MVT::i32) 5766 return 0; 5767 return fastEmitInst_rr(AArch64::ANDWrr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5768} 5769 5770unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5771 if (RetVT.SimpleTy != MVT::i64) 5772 return 0; 5773 return fastEmitInst_rr(AArch64::ANDXrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5774} 5775 5776unsigned fastEmit_ISD_AND_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5777 if (RetVT.SimpleTy != MVT::v8i8) 5778 return 0; 5779 if ((Subtarget->hasNEON())) { 5780 return fastEmitInst_rr(AArch64::ANDv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5781 } 5782 return 0; 5783} 5784 5785unsigned fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5786 if (RetVT.SimpleTy != MVT::v16i8) 5787 return 0; 5788 if ((Subtarget->hasNEON())) { 5789 return fastEmitInst_rr(AArch64::ANDv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5790 } 5791 return 0; 5792} 5793 5794unsigned fastEmit_ISD_AND_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5795 if (RetVT.SimpleTy != MVT::v4i16) 5796 return 0; 5797 if ((Subtarget->hasNEON())) { 5798 return fastEmitInst_rr(AArch64::ANDv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5799 } 5800 return 0; 5801} 5802 5803unsigned fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5804 if (RetVT.SimpleTy != MVT::v8i16) 5805 return 0; 5806 if ((Subtarget->hasNEON())) { 5807 return fastEmitInst_rr(AArch64::ANDv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5808 } 5809 return 0; 5810} 5811 5812unsigned fastEmit_ISD_AND_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5813 if (RetVT.SimpleTy != MVT::v2i32) 5814 return 0; 5815 if ((Subtarget->hasNEON())) { 5816 return fastEmitInst_rr(AArch64::ANDv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5817 } 5818 return 0; 5819} 5820 5821unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5822 if (RetVT.SimpleTy != MVT::v4i32) 5823 return 0; 5824 if ((Subtarget->hasNEON())) { 5825 return fastEmitInst_rr(AArch64::ANDv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5826 } 5827 return 0; 5828} 5829 5830unsigned fastEmit_ISD_AND_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5831 if (RetVT.SimpleTy != MVT::v1i64) 5832 return 0; 5833 if ((Subtarget->hasNEON())) { 5834 return fastEmitInst_rr(AArch64::ANDv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5835 } 5836 return 0; 5837} 5838 5839unsigned fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5840 if (RetVT.SimpleTy != MVT::v2i64) 5841 return 0; 5842 if ((Subtarget->hasNEON())) { 5843 return fastEmitInst_rr(AArch64::ANDv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5844 } 5845 return 0; 5846} 5847 5848unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5849 switch (VT.SimpleTy) { 5850 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5851 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5852 case MVT::v8i8: return fastEmit_ISD_AND_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5853 case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5854 case MVT::v4i16: return fastEmit_ISD_AND_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5855 case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5856 case MVT::v2i32: return fastEmit_ISD_AND_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5857 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5858 case MVT::v1i64: return fastEmit_ISD_AND_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5859 case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5860 default: return 0; 5861 } 5862} 5863 5864// FastEmit functions for ISD::FADD. 5865 5866unsigned fastEmit_ISD_FADD_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5867 if (RetVT.SimpleTy != MVT::f16) 5868 return 0; 5869 if ((Subtarget->hasFullFP16())) { 5870 return fastEmitInst_rr(AArch64::FADDHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5871 } 5872 return 0; 5873} 5874 5875unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5876 if (RetVT.SimpleTy != MVT::f32) 5877 return 0; 5878 if ((Subtarget->hasFPARMv8())) { 5879 return fastEmitInst_rr(AArch64::FADDSrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5880 } 5881 return 0; 5882} 5883 5884unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5885 if (RetVT.SimpleTy != MVT::f64) 5886 return 0; 5887 if ((Subtarget->hasFPARMv8())) { 5888 return fastEmitInst_rr(AArch64::FADDDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5889 } 5890 return 0; 5891} 5892 5893unsigned fastEmit_ISD_FADD_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5894 if (RetVT.SimpleTy != MVT::v4f16) 5895 return 0; 5896 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 5897 return fastEmitInst_rr(AArch64::FADDv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5898 } 5899 return 0; 5900} 5901 5902unsigned fastEmit_ISD_FADD_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5903 if (RetVT.SimpleTy != MVT::v8f16) 5904 return 0; 5905 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 5906 return fastEmitInst_rr(AArch64::FADDv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5907 } 5908 return 0; 5909} 5910 5911unsigned fastEmit_ISD_FADD_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5912 if (RetVT.SimpleTy != MVT::v2f32) 5913 return 0; 5914 if ((Subtarget->hasNEON())) { 5915 return fastEmitInst_rr(AArch64::FADDv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5916 } 5917 return 0; 5918} 5919 5920unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5921 if (RetVT.SimpleTy != MVT::v4f32) 5922 return 0; 5923 if ((Subtarget->hasNEON())) { 5924 return fastEmitInst_rr(AArch64::FADDv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5925 } 5926 return 0; 5927} 5928 5929unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5930 if (RetVT.SimpleTy != MVT::v2f64) 5931 return 0; 5932 if ((Subtarget->hasNEON())) { 5933 return fastEmitInst_rr(AArch64::FADDv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5934 } 5935 return 0; 5936} 5937 5938unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5939 switch (VT.SimpleTy) { 5940 case MVT::f16: return fastEmit_ISD_FADD_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5941 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5942 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5943 case MVT::v4f16: return fastEmit_ISD_FADD_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5944 case MVT::v8f16: return fastEmit_ISD_FADD_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5945 case MVT::v2f32: return fastEmit_ISD_FADD_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5946 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5947 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5948 default: return 0; 5949 } 5950} 5951 5952// FastEmit functions for ISD::FDIV. 5953 5954unsigned fastEmit_ISD_FDIV_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5955 if (RetVT.SimpleTy != MVT::f16) 5956 return 0; 5957 if ((Subtarget->hasFullFP16())) { 5958 return fastEmitInst_rr(AArch64::FDIVHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5959 } 5960 return 0; 5961} 5962 5963unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5964 if (RetVT.SimpleTy != MVT::f32) 5965 return 0; 5966 if ((Subtarget->hasFPARMv8())) { 5967 return fastEmitInst_rr(AArch64::FDIVSrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5968 } 5969 return 0; 5970} 5971 5972unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5973 if (RetVT.SimpleTy != MVT::f64) 5974 return 0; 5975 if ((Subtarget->hasFPARMv8())) { 5976 return fastEmitInst_rr(AArch64::FDIVDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5977 } 5978 return 0; 5979} 5980 5981unsigned fastEmit_ISD_FDIV_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5982 if (RetVT.SimpleTy != MVT::v4f16) 5983 return 0; 5984 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 5985 return fastEmitInst_rr(AArch64::FDIVv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5986 } 5987 return 0; 5988} 5989 5990unsigned fastEmit_ISD_FDIV_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5991 if (RetVT.SimpleTy != MVT::v8f16) 5992 return 0; 5993 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 5994 return fastEmitInst_rr(AArch64::FDIVv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5995 } 5996 return 0; 5997} 5998 5999unsigned fastEmit_ISD_FDIV_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6000 if (RetVT.SimpleTy != MVT::v2f32) 6001 return 0; 6002 if ((Subtarget->hasNEON())) { 6003 return fastEmitInst_rr(AArch64::FDIVv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6004 } 6005 return 0; 6006} 6007 6008unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6009 if (RetVT.SimpleTy != MVT::v4f32) 6010 return 0; 6011 if ((Subtarget->hasNEON())) { 6012 return fastEmitInst_rr(AArch64::FDIVv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6013 } 6014 return 0; 6015} 6016 6017unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6018 if (RetVT.SimpleTy != MVT::v2f64) 6019 return 0; 6020 if ((Subtarget->hasNEON())) { 6021 return fastEmitInst_rr(AArch64::FDIVv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6022 } 6023 return 0; 6024} 6025 6026unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6027 switch (VT.SimpleTy) { 6028 case MVT::f16: return fastEmit_ISD_FDIV_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6029 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6030 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6031 case MVT::v4f16: return fastEmit_ISD_FDIV_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6032 case MVT::v8f16: return fastEmit_ISD_FDIV_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6033 case MVT::v2f32: return fastEmit_ISD_FDIV_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6034 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6035 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6036 default: return 0; 6037 } 6038} 6039 6040// FastEmit functions for ISD::FMAXNAN. 6041 6042unsigned fastEmit_ISD_FMAXNAN_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6043 if (RetVT.SimpleTy != MVT::f16) 6044 return 0; 6045 if ((Subtarget->hasFullFP16())) { 6046 return fastEmitInst_rr(AArch64::FMAXHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6047 } 6048 return 0; 6049} 6050 6051unsigned fastEmit_ISD_FMAXNAN_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6052 if (RetVT.SimpleTy != MVT::f32) 6053 return 0; 6054 if ((Subtarget->hasFPARMv8())) { 6055 return fastEmitInst_rr(AArch64::FMAXSrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6056 } 6057 return 0; 6058} 6059 6060unsigned fastEmit_ISD_FMAXNAN_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6061 if (RetVT.SimpleTy != MVT::f64) 6062 return 0; 6063 if ((Subtarget->hasFPARMv8())) { 6064 return fastEmitInst_rr(AArch64::FMAXDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6065 } 6066 return 0; 6067} 6068 6069unsigned fastEmit_ISD_FMAXNAN_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6070 if (RetVT.SimpleTy != MVT::v4f16) 6071 return 0; 6072 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 6073 return fastEmitInst_rr(AArch64::FMAXv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6074 } 6075 return 0; 6076} 6077 6078unsigned fastEmit_ISD_FMAXNAN_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6079 if (RetVT.SimpleTy != MVT::v8f16) 6080 return 0; 6081 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 6082 return fastEmitInst_rr(AArch64::FMAXv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6083 } 6084 return 0; 6085} 6086 6087unsigned fastEmit_ISD_FMAXNAN_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6088 if (RetVT.SimpleTy != MVT::v2f32) 6089 return 0; 6090 if ((Subtarget->hasNEON())) { 6091 return fastEmitInst_rr(AArch64::FMAXv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6092 } 6093 return 0; 6094} 6095 6096unsigned fastEmit_ISD_FMAXNAN_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6097 if (RetVT.SimpleTy != MVT::v4f32) 6098 return 0; 6099 if ((Subtarget->hasNEON())) { 6100 return fastEmitInst_rr(AArch64::FMAXv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6101 } 6102 return 0; 6103} 6104 6105unsigned fastEmit_ISD_FMAXNAN_MVT_v1f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6106 if (RetVT.SimpleTy != MVT::v1f64) 6107 return 0; 6108 return fastEmitInst_rr(AArch64::FMAXDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6109} 6110 6111unsigned fastEmit_ISD_FMAXNAN_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6112 if (RetVT.SimpleTy != MVT::v2f64) 6113 return 0; 6114 if ((Subtarget->hasNEON())) { 6115 return fastEmitInst_rr(AArch64::FMAXv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6116 } 6117 return 0; 6118} 6119 6120unsigned fastEmit_ISD_FMAXNAN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6121 switch (VT.SimpleTy) { 6122 case MVT::f16: return fastEmit_ISD_FMAXNAN_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6123 case MVT::f32: return fastEmit_ISD_FMAXNAN_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6124 case MVT::f64: return fastEmit_ISD_FMAXNAN_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6125 case MVT::v4f16: return fastEmit_ISD_FMAXNAN_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6126 case MVT::v8f16: return fastEmit_ISD_FMAXNAN_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6127 case MVT::v2f32: return fastEmit_ISD_FMAXNAN_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6128 case MVT::v4f32: return fastEmit_ISD_FMAXNAN_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6129 case MVT::v1f64: return fastEmit_ISD_FMAXNAN_MVT_v1f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6130 case MVT::v2f64: return fastEmit_ISD_FMAXNAN_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6131 default: return 0; 6132 } 6133} 6134 6135// FastEmit functions for ISD::FMAXNUM. 6136 6137unsigned fastEmit_ISD_FMAXNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6138 if (RetVT.SimpleTy != MVT::f16) 6139 return 0; 6140 if ((Subtarget->hasFullFP16())) { 6141 return fastEmitInst_rr(AArch64::FMAXNMHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6142 } 6143 return 0; 6144} 6145 6146unsigned fastEmit_ISD_FMAXNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6147 if (RetVT.SimpleTy != MVT::f32) 6148 return 0; 6149 if ((Subtarget->hasFPARMv8())) { 6150 return fastEmitInst_rr(AArch64::FMAXNMSrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6151 } 6152 return 0; 6153} 6154 6155unsigned fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6156 if (RetVT.SimpleTy != MVT::f64) 6157 return 0; 6158 if ((Subtarget->hasFPARMv8())) { 6159 return fastEmitInst_rr(AArch64::FMAXNMDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6160 } 6161 return 0; 6162} 6163 6164unsigned fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6165 if (RetVT.SimpleTy != MVT::v4f16) 6166 return 0; 6167 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 6168 return fastEmitInst_rr(AArch64::FMAXNMv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6169 } 6170 return 0; 6171} 6172 6173unsigned fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6174 if (RetVT.SimpleTy != MVT::v8f16) 6175 return 0; 6176 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 6177 return fastEmitInst_rr(AArch64::FMAXNMv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6178 } 6179 return 0; 6180} 6181 6182unsigned fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6183 if (RetVT.SimpleTy != MVT::v2f32) 6184 return 0; 6185 if ((Subtarget->hasNEON())) { 6186 return fastEmitInst_rr(AArch64::FMAXNMv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6187 } 6188 return 0; 6189} 6190 6191unsigned fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6192 if (RetVT.SimpleTy != MVT::v4f32) 6193 return 0; 6194 if ((Subtarget->hasNEON())) { 6195 return fastEmitInst_rr(AArch64::FMAXNMv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6196 } 6197 return 0; 6198} 6199 6200unsigned fastEmit_ISD_FMAXNUM_MVT_v1f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6201 if (RetVT.SimpleTy != MVT::v1f64) 6202 return 0; 6203 return fastEmitInst_rr(AArch64::FMAXNMDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6204} 6205 6206unsigned fastEmit_ISD_FMAXNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6207 if (RetVT.SimpleTy != MVT::v2f64) 6208 return 0; 6209 if ((Subtarget->hasNEON())) { 6210 return fastEmitInst_rr(AArch64::FMAXNMv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6211 } 6212 return 0; 6213} 6214 6215unsigned fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6216 switch (VT.SimpleTy) { 6217 case MVT::f16: return fastEmit_ISD_FMAXNUM_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6218 case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6219 case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6220 case MVT::v4f16: return fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6221 case MVT::v8f16: return fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6222 case MVT::v2f32: return fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6223 case MVT::v4f32: return fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6224 case MVT::v1f64: return fastEmit_ISD_FMAXNUM_MVT_v1f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6225 case MVT::v2f64: return fastEmit_ISD_FMAXNUM_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6226 default: return 0; 6227 } 6228} 6229 6230// FastEmit functions for ISD::FMINNAN. 6231 6232unsigned fastEmit_ISD_FMINNAN_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6233 if (RetVT.SimpleTy != MVT::f16) 6234 return 0; 6235 if ((Subtarget->hasFullFP16())) { 6236 return fastEmitInst_rr(AArch64::FMINHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6237 } 6238 return 0; 6239} 6240 6241unsigned fastEmit_ISD_FMINNAN_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6242 if (RetVT.SimpleTy != MVT::f32) 6243 return 0; 6244 if ((Subtarget->hasFPARMv8())) { 6245 return fastEmitInst_rr(AArch64::FMINSrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6246 } 6247 return 0; 6248} 6249 6250unsigned fastEmit_ISD_FMINNAN_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6251 if (RetVT.SimpleTy != MVT::f64) 6252 return 0; 6253 if ((Subtarget->hasFPARMv8())) { 6254 return fastEmitInst_rr(AArch64::FMINDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6255 } 6256 return 0; 6257} 6258 6259unsigned fastEmit_ISD_FMINNAN_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6260 if (RetVT.SimpleTy != MVT::v4f16) 6261 return 0; 6262 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 6263 return fastEmitInst_rr(AArch64::FMINv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6264 } 6265 return 0; 6266} 6267 6268unsigned fastEmit_ISD_FMINNAN_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6269 if (RetVT.SimpleTy != MVT::v8f16) 6270 return 0; 6271 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 6272 return fastEmitInst_rr(AArch64::FMINv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6273 } 6274 return 0; 6275} 6276 6277unsigned fastEmit_ISD_FMINNAN_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6278 if (RetVT.SimpleTy != MVT::v2f32) 6279 return 0; 6280 if ((Subtarget->hasNEON())) { 6281 return fastEmitInst_rr(AArch64::FMINv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6282 } 6283 return 0; 6284} 6285 6286unsigned fastEmit_ISD_FMINNAN_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6287 if (RetVT.SimpleTy != MVT::v4f32) 6288 return 0; 6289 if ((Subtarget->hasNEON())) { 6290 return fastEmitInst_rr(AArch64::FMINv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6291 } 6292 return 0; 6293} 6294 6295unsigned fastEmit_ISD_FMINNAN_MVT_v1f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6296 if (RetVT.SimpleTy != MVT::v1f64) 6297 return 0; 6298 return fastEmitInst_rr(AArch64::FMINDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6299} 6300 6301unsigned fastEmit_ISD_FMINNAN_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6302 if (RetVT.SimpleTy != MVT::v2f64) 6303 return 0; 6304 if ((Subtarget->hasNEON())) { 6305 return fastEmitInst_rr(AArch64::FMINv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6306 } 6307 return 0; 6308} 6309 6310unsigned fastEmit_ISD_FMINNAN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6311 switch (VT.SimpleTy) { 6312 case MVT::f16: return fastEmit_ISD_FMINNAN_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6313 case MVT::f32: return fastEmit_ISD_FMINNAN_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6314 case MVT::f64: return fastEmit_ISD_FMINNAN_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6315 case MVT::v4f16: return fastEmit_ISD_FMINNAN_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6316 case MVT::v8f16: return fastEmit_ISD_FMINNAN_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6317 case MVT::v2f32: return fastEmit_ISD_FMINNAN_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6318 case MVT::v4f32: return fastEmit_ISD_FMINNAN_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6319 case MVT::v1f64: return fastEmit_ISD_FMINNAN_MVT_v1f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6320 case MVT::v2f64: return fastEmit_ISD_FMINNAN_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6321 default: return 0; 6322 } 6323} 6324 6325// FastEmit functions for ISD::FMINNUM. 6326 6327unsigned fastEmit_ISD_FMINNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6328 if (RetVT.SimpleTy != MVT::f16) 6329 return 0; 6330 if ((Subtarget->hasFullFP16())) { 6331 return fastEmitInst_rr(AArch64::FMINNMHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6332 } 6333 return 0; 6334} 6335 6336unsigned fastEmit_ISD_FMINNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6337 if (RetVT.SimpleTy != MVT::f32) 6338 return 0; 6339 if ((Subtarget->hasFPARMv8())) { 6340 return fastEmitInst_rr(AArch64::FMINNMSrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6341 } 6342 return 0; 6343} 6344 6345unsigned fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6346 if (RetVT.SimpleTy != MVT::f64) 6347 return 0; 6348 if ((Subtarget->hasFPARMv8())) { 6349 return fastEmitInst_rr(AArch64::FMINNMDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6350 } 6351 return 0; 6352} 6353 6354unsigned fastEmit_ISD_FMINNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6355 if (RetVT.SimpleTy != MVT::v4f16) 6356 return 0; 6357 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 6358 return fastEmitInst_rr(AArch64::FMINNMv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6359 } 6360 return 0; 6361} 6362 6363unsigned fastEmit_ISD_FMINNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6364 if (RetVT.SimpleTy != MVT::v8f16) 6365 return 0; 6366 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 6367 return fastEmitInst_rr(AArch64::FMINNMv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6368 } 6369 return 0; 6370} 6371 6372unsigned fastEmit_ISD_FMINNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6373 if (RetVT.SimpleTy != MVT::v2f32) 6374 return 0; 6375 if ((Subtarget->hasNEON())) { 6376 return fastEmitInst_rr(AArch64::FMINNMv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6377 } 6378 return 0; 6379} 6380 6381unsigned fastEmit_ISD_FMINNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6382 if (RetVT.SimpleTy != MVT::v4f32) 6383 return 0; 6384 if ((Subtarget->hasNEON())) { 6385 return fastEmitInst_rr(AArch64::FMINNMv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6386 } 6387 return 0; 6388} 6389 6390unsigned fastEmit_ISD_FMINNUM_MVT_v1f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6391 if (RetVT.SimpleTy != MVT::v1f64) 6392 return 0; 6393 return fastEmitInst_rr(AArch64::FMINNMDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6394} 6395 6396unsigned fastEmit_ISD_FMINNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6397 if (RetVT.SimpleTy != MVT::v2f64) 6398 return 0; 6399 if ((Subtarget->hasNEON())) { 6400 return fastEmitInst_rr(AArch64::FMINNMv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6401 } 6402 return 0; 6403} 6404 6405unsigned fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6406 switch (VT.SimpleTy) { 6407 case MVT::f16: return fastEmit_ISD_FMINNUM_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6408 case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6409 case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6410 case MVT::v4f16: return fastEmit_ISD_FMINNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6411 case MVT::v8f16: return fastEmit_ISD_FMINNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6412 case MVT::v2f32: return fastEmit_ISD_FMINNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6413 case MVT::v4f32: return fastEmit_ISD_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6414 case MVT::v1f64: return fastEmit_ISD_FMINNUM_MVT_v1f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6415 case MVT::v2f64: return fastEmit_ISD_FMINNUM_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6416 default: return 0; 6417 } 6418} 6419 6420// FastEmit functions for ISD::FMUL. 6421 6422unsigned fastEmit_ISD_FMUL_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6423 if (RetVT.SimpleTy != MVT::f16) 6424 return 0; 6425 if ((Subtarget->hasFullFP16())) { 6426 return fastEmitInst_rr(AArch64::FMULHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6427 } 6428 return 0; 6429} 6430 6431unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6432 if (RetVT.SimpleTy != MVT::f32) 6433 return 0; 6434 if ((Subtarget->hasFPARMv8())) { 6435 return fastEmitInst_rr(AArch64::FMULSrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6436 } 6437 return 0; 6438} 6439 6440unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6441 if (RetVT.SimpleTy != MVT::f64) 6442 return 0; 6443 if ((Subtarget->hasFPARMv8())) { 6444 return fastEmitInst_rr(AArch64::FMULDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6445 } 6446 return 0; 6447} 6448 6449unsigned fastEmit_ISD_FMUL_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6450 if (RetVT.SimpleTy != MVT::v4f16) 6451 return 0; 6452 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 6453 return fastEmitInst_rr(AArch64::FMULv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6454 } 6455 return 0; 6456} 6457 6458unsigned fastEmit_ISD_FMUL_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6459 if (RetVT.SimpleTy != MVT::v8f16) 6460 return 0; 6461 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 6462 return fastEmitInst_rr(AArch64::FMULv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6463 } 6464 return 0; 6465} 6466 6467unsigned fastEmit_ISD_FMUL_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6468 if (RetVT.SimpleTy != MVT::v2f32) 6469 return 0; 6470 if ((Subtarget->hasNEON())) { 6471 return fastEmitInst_rr(AArch64::FMULv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6472 } 6473 return 0; 6474} 6475 6476unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6477 if (RetVT.SimpleTy != MVT::v4f32) 6478 return 0; 6479 if ((Subtarget->hasNEON())) { 6480 return fastEmitInst_rr(AArch64::FMULv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6481 } 6482 return 0; 6483} 6484 6485unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6486 if (RetVT.SimpleTy != MVT::v2f64) 6487 return 0; 6488 if ((Subtarget->hasNEON())) { 6489 return fastEmitInst_rr(AArch64::FMULv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6490 } 6491 return 0; 6492} 6493 6494unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6495 switch (VT.SimpleTy) { 6496 case MVT::f16: return fastEmit_ISD_FMUL_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6497 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6498 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6499 case MVT::v4f16: return fastEmit_ISD_FMUL_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6500 case MVT::v8f16: return fastEmit_ISD_FMUL_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6501 case MVT::v2f32: return fastEmit_ISD_FMUL_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6502 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6503 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6504 default: return 0; 6505 } 6506} 6507 6508// FastEmit functions for ISD::FSUB. 6509 6510unsigned fastEmit_ISD_FSUB_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6511 if (RetVT.SimpleTy != MVT::f16) 6512 return 0; 6513 if ((Subtarget->hasFullFP16())) { 6514 return fastEmitInst_rr(AArch64::FSUBHrr, &AArch64::FPR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6515 } 6516 return 0; 6517} 6518 6519unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6520 if (RetVT.SimpleTy != MVT::f32) 6521 return 0; 6522 if ((Subtarget->hasFPARMv8())) { 6523 return fastEmitInst_rr(AArch64::FSUBSrr, &AArch64::FPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6524 } 6525 return 0; 6526} 6527 6528unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6529 if (RetVT.SimpleTy != MVT::f64) 6530 return 0; 6531 if ((Subtarget->hasFPARMv8())) { 6532 return fastEmitInst_rr(AArch64::FSUBDrr, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6533 } 6534 return 0; 6535} 6536 6537unsigned fastEmit_ISD_FSUB_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6538 if (RetVT.SimpleTy != MVT::v4f16) 6539 return 0; 6540 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 6541 return fastEmitInst_rr(AArch64::FSUBv4f16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6542 } 6543 return 0; 6544} 6545 6546unsigned fastEmit_ISD_FSUB_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6547 if (RetVT.SimpleTy != MVT::v8f16) 6548 return 0; 6549 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 6550 return fastEmitInst_rr(AArch64::FSUBv8f16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6551 } 6552 return 0; 6553} 6554 6555unsigned fastEmit_ISD_FSUB_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6556 if (RetVT.SimpleTy != MVT::v2f32) 6557 return 0; 6558 if ((Subtarget->hasNEON())) { 6559 return fastEmitInst_rr(AArch64::FSUBv2f32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6560 } 6561 return 0; 6562} 6563 6564unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6565 if (RetVT.SimpleTy != MVT::v4f32) 6566 return 0; 6567 if ((Subtarget->hasNEON())) { 6568 return fastEmitInst_rr(AArch64::FSUBv4f32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6569 } 6570 return 0; 6571} 6572 6573unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6574 if (RetVT.SimpleTy != MVT::v2f64) 6575 return 0; 6576 if ((Subtarget->hasNEON())) { 6577 return fastEmitInst_rr(AArch64::FSUBv2f64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6578 } 6579 return 0; 6580} 6581 6582unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6583 switch (VT.SimpleTy) { 6584 case MVT::f16: return fastEmit_ISD_FSUB_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6585 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6586 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6587 case MVT::v4f16: return fastEmit_ISD_FSUB_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6588 case MVT::v8f16: return fastEmit_ISD_FSUB_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6589 case MVT::v2f32: return fastEmit_ISD_FSUB_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6590 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6591 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6592 default: return 0; 6593 } 6594} 6595 6596// FastEmit functions for ISD::MUL. 6597 6598unsigned fastEmit_ISD_MUL_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6599 if (RetVT.SimpleTy != MVT::v8i8) 6600 return 0; 6601 if ((Subtarget->hasNEON())) { 6602 return fastEmitInst_rr(AArch64::MULv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6603 } 6604 return 0; 6605} 6606 6607unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6608 if (RetVT.SimpleTy != MVT::v16i8) 6609 return 0; 6610 if ((Subtarget->hasNEON())) { 6611 return fastEmitInst_rr(AArch64::MULv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6612 } 6613 return 0; 6614} 6615 6616unsigned fastEmit_ISD_MUL_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6617 if (RetVT.SimpleTy != MVT::v4i16) 6618 return 0; 6619 if ((Subtarget->hasNEON())) { 6620 return fastEmitInst_rr(AArch64::MULv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6621 } 6622 return 0; 6623} 6624 6625unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6626 if (RetVT.SimpleTy != MVT::v8i16) 6627 return 0; 6628 if ((Subtarget->hasNEON())) { 6629 return fastEmitInst_rr(AArch64::MULv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6630 } 6631 return 0; 6632} 6633 6634unsigned fastEmit_ISD_MUL_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6635 if (RetVT.SimpleTy != MVT::v2i32) 6636 return 0; 6637 if ((Subtarget->hasNEON())) { 6638 return fastEmitInst_rr(AArch64::MULv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6639 } 6640 return 0; 6641} 6642 6643unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6644 if (RetVT.SimpleTy != MVT::v4i32) 6645 return 0; 6646 if ((Subtarget->hasNEON())) { 6647 return fastEmitInst_rr(AArch64::MULv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6648 } 6649 return 0; 6650} 6651 6652unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6653 switch (VT.SimpleTy) { 6654 case MVT::v8i8: return fastEmit_ISD_MUL_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6655 case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6656 case MVT::v4i16: return fastEmit_ISD_MUL_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6657 case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6658 case MVT::v2i32: return fastEmit_ISD_MUL_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6659 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6660 default: return 0; 6661 } 6662} 6663 6664// FastEmit functions for ISD::MULHS. 6665 6666unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6667 if (RetVT.SimpleTy != MVT::i64) 6668 return 0; 6669 return fastEmitInst_rr(AArch64::SMULHrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6670} 6671 6672unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6673 switch (VT.SimpleTy) { 6674 case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6675 default: return 0; 6676 } 6677} 6678 6679// FastEmit functions for ISD::MULHU. 6680 6681unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6682 if (RetVT.SimpleTy != MVT::i64) 6683 return 0; 6684 return fastEmitInst_rr(AArch64::UMULHrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6685} 6686 6687unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6688 switch (VT.SimpleTy) { 6689 case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6690 default: return 0; 6691 } 6692} 6693 6694// FastEmit functions for ISD::OR. 6695 6696unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6697 if (RetVT.SimpleTy != MVT::i32) 6698 return 0; 6699 return fastEmitInst_rr(AArch64::ORRWrr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6700} 6701 6702unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6703 if (RetVT.SimpleTy != MVT::i64) 6704 return 0; 6705 return fastEmitInst_rr(AArch64::ORRXrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6706} 6707 6708unsigned fastEmit_ISD_OR_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6709 if (RetVT.SimpleTy != MVT::v8i8) 6710 return 0; 6711 if ((Subtarget->hasNEON())) { 6712 return fastEmitInst_rr(AArch64::ORRv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6713 } 6714 return 0; 6715} 6716 6717unsigned fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6718 if (RetVT.SimpleTy != MVT::v16i8) 6719 return 0; 6720 if ((Subtarget->hasNEON())) { 6721 return fastEmitInst_rr(AArch64::ORRv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6722 } 6723 return 0; 6724} 6725 6726unsigned fastEmit_ISD_OR_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6727 if (RetVT.SimpleTy != MVT::v4i16) 6728 return 0; 6729 if ((Subtarget->hasNEON())) { 6730 return fastEmitInst_rr(AArch64::ORRv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6731 } 6732 return 0; 6733} 6734 6735unsigned fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6736 if (RetVT.SimpleTy != MVT::v8i16) 6737 return 0; 6738 if ((Subtarget->hasNEON())) { 6739 return fastEmitInst_rr(AArch64::ORRv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6740 } 6741 return 0; 6742} 6743 6744unsigned fastEmit_ISD_OR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6745 if (RetVT.SimpleTy != MVT::v2i32) 6746 return 0; 6747 if ((Subtarget->hasNEON())) { 6748 return fastEmitInst_rr(AArch64::ORRv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6749 } 6750 return 0; 6751} 6752 6753unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6754 if (RetVT.SimpleTy != MVT::v4i32) 6755 return 0; 6756 if ((Subtarget->hasNEON())) { 6757 return fastEmitInst_rr(AArch64::ORRv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6758 } 6759 return 0; 6760} 6761 6762unsigned fastEmit_ISD_OR_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6763 if (RetVT.SimpleTy != MVT::v1i64) 6764 return 0; 6765 if ((Subtarget->hasNEON())) { 6766 return fastEmitInst_rr(AArch64::ORRv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6767 } 6768 return 0; 6769} 6770 6771unsigned fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6772 if (RetVT.SimpleTy != MVT::v2i64) 6773 return 0; 6774 if ((Subtarget->hasNEON())) { 6775 return fastEmitInst_rr(AArch64::ORRv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6776 } 6777 return 0; 6778} 6779 6780unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6781 switch (VT.SimpleTy) { 6782 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6783 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6784 case MVT::v8i8: return fastEmit_ISD_OR_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6785 case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6786 case MVT::v4i16: return fastEmit_ISD_OR_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6787 case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6788 case MVT::v2i32: return fastEmit_ISD_OR_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6789 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6790 case MVT::v1i64: return fastEmit_ISD_OR_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6791 case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6792 default: return 0; 6793 } 6794} 6795 6796// FastEmit functions for ISD::ROTR. 6797 6798unsigned fastEmit_ISD_ROTR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6799 if (RetVT.SimpleTy != MVT::i64) 6800 return 0; 6801 return fastEmitInst_rr(AArch64::RORVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6802} 6803 6804unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6805 switch (VT.SimpleTy) { 6806 case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6807 default: return 0; 6808 } 6809} 6810 6811// FastEmit functions for ISD::SDIV. 6812 6813unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6814 if (RetVT.SimpleTy != MVT::i32) 6815 return 0; 6816 return fastEmitInst_rr(AArch64::SDIVWr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6817} 6818 6819unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6820 if (RetVT.SimpleTy != MVT::i64) 6821 return 0; 6822 return fastEmitInst_rr(AArch64::SDIVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6823} 6824 6825unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6826 switch (VT.SimpleTy) { 6827 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6828 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6829 default: return 0; 6830 } 6831} 6832 6833// FastEmit functions for ISD::SHL. 6834 6835unsigned fastEmit_ISD_SHL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6836 if (RetVT.SimpleTy != MVT::i64) 6837 return 0; 6838 return fastEmitInst_rr(AArch64::LSLVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6839} 6840 6841unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6842 switch (VT.SimpleTy) { 6843 case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6844 default: return 0; 6845 } 6846} 6847 6848// FastEmit functions for ISD::SMAX. 6849 6850unsigned fastEmit_ISD_SMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6851 if (RetVT.SimpleTy != MVT::v8i8) 6852 return 0; 6853 if ((Subtarget->hasNEON())) { 6854 return fastEmitInst_rr(AArch64::SMAXv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6855 } 6856 return 0; 6857} 6858 6859unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6860 if (RetVT.SimpleTy != MVT::v16i8) 6861 return 0; 6862 if ((Subtarget->hasNEON())) { 6863 return fastEmitInst_rr(AArch64::SMAXv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6864 } 6865 return 0; 6866} 6867 6868unsigned fastEmit_ISD_SMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6869 if (RetVT.SimpleTy != MVT::v4i16) 6870 return 0; 6871 if ((Subtarget->hasNEON())) { 6872 return fastEmitInst_rr(AArch64::SMAXv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6873 } 6874 return 0; 6875} 6876 6877unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6878 if (RetVT.SimpleTy != MVT::v8i16) 6879 return 0; 6880 if ((Subtarget->hasNEON())) { 6881 return fastEmitInst_rr(AArch64::SMAXv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6882 } 6883 return 0; 6884} 6885 6886unsigned fastEmit_ISD_SMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6887 if (RetVT.SimpleTy != MVT::v2i32) 6888 return 0; 6889 if ((Subtarget->hasNEON())) { 6890 return fastEmitInst_rr(AArch64::SMAXv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6891 } 6892 return 0; 6893} 6894 6895unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6896 if (RetVT.SimpleTy != MVT::v4i32) 6897 return 0; 6898 if ((Subtarget->hasNEON())) { 6899 return fastEmitInst_rr(AArch64::SMAXv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6900 } 6901 return 0; 6902} 6903 6904unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6905 switch (VT.SimpleTy) { 6906 case MVT::v8i8: return fastEmit_ISD_SMAX_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6907 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6908 case MVT::v4i16: return fastEmit_ISD_SMAX_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6909 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6910 case MVT::v2i32: return fastEmit_ISD_SMAX_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6911 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6912 default: return 0; 6913 } 6914} 6915 6916// FastEmit functions for ISD::SMIN. 6917 6918unsigned fastEmit_ISD_SMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6919 if (RetVT.SimpleTy != MVT::v8i8) 6920 return 0; 6921 if ((Subtarget->hasNEON())) { 6922 return fastEmitInst_rr(AArch64::SMINv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6923 } 6924 return 0; 6925} 6926 6927unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6928 if (RetVT.SimpleTy != MVT::v16i8) 6929 return 0; 6930 if ((Subtarget->hasNEON())) { 6931 return fastEmitInst_rr(AArch64::SMINv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6932 } 6933 return 0; 6934} 6935 6936unsigned fastEmit_ISD_SMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6937 if (RetVT.SimpleTy != MVT::v4i16) 6938 return 0; 6939 if ((Subtarget->hasNEON())) { 6940 return fastEmitInst_rr(AArch64::SMINv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6941 } 6942 return 0; 6943} 6944 6945unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6946 if (RetVT.SimpleTy != MVT::v8i16) 6947 return 0; 6948 if ((Subtarget->hasNEON())) { 6949 return fastEmitInst_rr(AArch64::SMINv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6950 } 6951 return 0; 6952} 6953 6954unsigned fastEmit_ISD_SMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6955 if (RetVT.SimpleTy != MVT::v2i32) 6956 return 0; 6957 if ((Subtarget->hasNEON())) { 6958 return fastEmitInst_rr(AArch64::SMINv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6959 } 6960 return 0; 6961} 6962 6963unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6964 if (RetVT.SimpleTy != MVT::v4i32) 6965 return 0; 6966 if ((Subtarget->hasNEON())) { 6967 return fastEmitInst_rr(AArch64::SMINv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6968 } 6969 return 0; 6970} 6971 6972unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6973 switch (VT.SimpleTy) { 6974 case MVT::v8i8: return fastEmit_ISD_SMIN_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6975 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6976 case MVT::v4i16: return fastEmit_ISD_SMIN_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6977 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6978 case MVT::v2i32: return fastEmit_ISD_SMIN_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6979 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6980 default: return 0; 6981 } 6982} 6983 6984// FastEmit functions for ISD::SRA. 6985 6986unsigned fastEmit_ISD_SRA_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6987 if (RetVT.SimpleTy != MVT::i64) 6988 return 0; 6989 return fastEmitInst_rr(AArch64::ASRVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 6990} 6991 6992unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 6993 switch (VT.SimpleTy) { 6994 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 6995 default: return 0; 6996 } 6997} 6998 6999// FastEmit functions for ISD::SRL. 7000 7001unsigned fastEmit_ISD_SRL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7002 if (RetVT.SimpleTy != MVT::i64) 7003 return 0; 7004 return fastEmitInst_rr(AArch64::LSRVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7005} 7006 7007unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7008 switch (VT.SimpleTy) { 7009 case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7010 default: return 0; 7011 } 7012} 7013 7014// FastEmit functions for ISD::SUB. 7015 7016unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7017 if (RetVT.SimpleTy != MVT::i32) 7018 return 0; 7019 return fastEmitInst_rr(AArch64::SUBSWrr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7020} 7021 7022unsigned fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7023 if (RetVT.SimpleTy != MVT::i64) 7024 return 0; 7025 return fastEmitInst_rr(AArch64::SUBSXrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7026} 7027 7028unsigned fastEmit_ISD_SUB_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7029 if (RetVT.SimpleTy != MVT::v8i8) 7030 return 0; 7031 if ((Subtarget->hasNEON())) { 7032 return fastEmitInst_rr(AArch64::SUBv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7033 } 7034 return 0; 7035} 7036 7037unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7038 if (RetVT.SimpleTy != MVT::v16i8) 7039 return 0; 7040 if ((Subtarget->hasNEON())) { 7041 return fastEmitInst_rr(AArch64::SUBv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7042 } 7043 return 0; 7044} 7045 7046unsigned fastEmit_ISD_SUB_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7047 if (RetVT.SimpleTy != MVT::v4i16) 7048 return 0; 7049 if ((Subtarget->hasNEON())) { 7050 return fastEmitInst_rr(AArch64::SUBv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7051 } 7052 return 0; 7053} 7054 7055unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7056 if (RetVT.SimpleTy != MVT::v8i16) 7057 return 0; 7058 if ((Subtarget->hasNEON())) { 7059 return fastEmitInst_rr(AArch64::SUBv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7060 } 7061 return 0; 7062} 7063 7064unsigned fastEmit_ISD_SUB_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7065 if (RetVT.SimpleTy != MVT::v2i32) 7066 return 0; 7067 if ((Subtarget->hasNEON())) { 7068 return fastEmitInst_rr(AArch64::SUBv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7069 } 7070 return 0; 7071} 7072 7073unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7074 if (RetVT.SimpleTy != MVT::v4i32) 7075 return 0; 7076 if ((Subtarget->hasNEON())) { 7077 return fastEmitInst_rr(AArch64::SUBv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7078 } 7079 return 0; 7080} 7081 7082unsigned fastEmit_ISD_SUB_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7083 if (RetVT.SimpleTy != MVT::v1i64) 7084 return 0; 7085 if ((Subtarget->hasNEON())) { 7086 return fastEmitInst_rr(AArch64::SUBv1i64, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7087 } 7088 return 0; 7089} 7090 7091unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7092 if (RetVT.SimpleTy != MVT::v2i64) 7093 return 0; 7094 if ((Subtarget->hasNEON())) { 7095 return fastEmitInst_rr(AArch64::SUBv2i64, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7096 } 7097 return 0; 7098} 7099 7100unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7101 switch (VT.SimpleTy) { 7102 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7103 case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7104 case MVT::v8i8: return fastEmit_ISD_SUB_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7105 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7106 case MVT::v4i16: return fastEmit_ISD_SUB_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7107 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7108 case MVT::v2i32: return fastEmit_ISD_SUB_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7109 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7110 case MVT::v1i64: return fastEmit_ISD_SUB_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7111 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7112 default: return 0; 7113 } 7114} 7115 7116// FastEmit functions for ISD::UDIV. 7117 7118unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7119 if (RetVT.SimpleTy != MVT::i32) 7120 return 0; 7121 return fastEmitInst_rr(AArch64::UDIVWr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7122} 7123 7124unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7125 if (RetVT.SimpleTy != MVT::i64) 7126 return 0; 7127 return fastEmitInst_rr(AArch64::UDIVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7128} 7129 7130unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7131 switch (VT.SimpleTy) { 7132 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7133 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7134 default: return 0; 7135 } 7136} 7137 7138// FastEmit functions for ISD::UMAX. 7139 7140unsigned fastEmit_ISD_UMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7141 if (RetVT.SimpleTy != MVT::v8i8) 7142 return 0; 7143 if ((Subtarget->hasNEON())) { 7144 return fastEmitInst_rr(AArch64::UMAXv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7145 } 7146 return 0; 7147} 7148 7149unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7150 if (RetVT.SimpleTy != MVT::v16i8) 7151 return 0; 7152 if ((Subtarget->hasNEON())) { 7153 return fastEmitInst_rr(AArch64::UMAXv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7154 } 7155 return 0; 7156} 7157 7158unsigned fastEmit_ISD_UMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7159 if (RetVT.SimpleTy != MVT::v4i16) 7160 return 0; 7161 if ((Subtarget->hasNEON())) { 7162 return fastEmitInst_rr(AArch64::UMAXv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7163 } 7164 return 0; 7165} 7166 7167unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7168 if (RetVT.SimpleTy != MVT::v8i16) 7169 return 0; 7170 if ((Subtarget->hasNEON())) { 7171 return fastEmitInst_rr(AArch64::UMAXv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7172 } 7173 return 0; 7174} 7175 7176unsigned fastEmit_ISD_UMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7177 if (RetVT.SimpleTy != MVT::v2i32) 7178 return 0; 7179 if ((Subtarget->hasNEON())) { 7180 return fastEmitInst_rr(AArch64::UMAXv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7181 } 7182 return 0; 7183} 7184 7185unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7186 if (RetVT.SimpleTy != MVT::v4i32) 7187 return 0; 7188 if ((Subtarget->hasNEON())) { 7189 return fastEmitInst_rr(AArch64::UMAXv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7190 } 7191 return 0; 7192} 7193 7194unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7195 switch (VT.SimpleTy) { 7196 case MVT::v8i8: return fastEmit_ISD_UMAX_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7197 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7198 case MVT::v4i16: return fastEmit_ISD_UMAX_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7199 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7200 case MVT::v2i32: return fastEmit_ISD_UMAX_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7201 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7202 default: return 0; 7203 } 7204} 7205 7206// FastEmit functions for ISD::UMIN. 7207 7208unsigned fastEmit_ISD_UMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7209 if (RetVT.SimpleTy != MVT::v8i8) 7210 return 0; 7211 if ((Subtarget->hasNEON())) { 7212 return fastEmitInst_rr(AArch64::UMINv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7213 } 7214 return 0; 7215} 7216 7217unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7218 if (RetVT.SimpleTy != MVT::v16i8) 7219 return 0; 7220 if ((Subtarget->hasNEON())) { 7221 return fastEmitInst_rr(AArch64::UMINv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7222 } 7223 return 0; 7224} 7225 7226unsigned fastEmit_ISD_UMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7227 if (RetVT.SimpleTy != MVT::v4i16) 7228 return 0; 7229 if ((Subtarget->hasNEON())) { 7230 return fastEmitInst_rr(AArch64::UMINv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7231 } 7232 return 0; 7233} 7234 7235unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7236 if (RetVT.SimpleTy != MVT::v8i16) 7237 return 0; 7238 if ((Subtarget->hasNEON())) { 7239 return fastEmitInst_rr(AArch64::UMINv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7240 } 7241 return 0; 7242} 7243 7244unsigned fastEmit_ISD_UMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7245 if (RetVT.SimpleTy != MVT::v2i32) 7246 return 0; 7247 if ((Subtarget->hasNEON())) { 7248 return fastEmitInst_rr(AArch64::UMINv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7249 } 7250 return 0; 7251} 7252 7253unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7254 if (RetVT.SimpleTy != MVT::v4i32) 7255 return 0; 7256 if ((Subtarget->hasNEON())) { 7257 return fastEmitInst_rr(AArch64::UMINv4i32, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7258 } 7259 return 0; 7260} 7261 7262unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7263 switch (VT.SimpleTy) { 7264 case MVT::v8i8: return fastEmit_ISD_UMIN_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7265 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7266 case MVT::v4i16: return fastEmit_ISD_UMIN_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7267 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7268 case MVT::v2i32: return fastEmit_ISD_UMIN_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7269 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7270 default: return 0; 7271 } 7272} 7273 7274// FastEmit functions for ISD::XOR. 7275 7276unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7277 if (RetVT.SimpleTy != MVT::i32) 7278 return 0; 7279 return fastEmitInst_rr(AArch64::EORWrr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7280} 7281 7282unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7283 if (RetVT.SimpleTy != MVT::i64) 7284 return 0; 7285 return fastEmitInst_rr(AArch64::EORXrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7286} 7287 7288unsigned fastEmit_ISD_XOR_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7289 if (RetVT.SimpleTy != MVT::v8i8) 7290 return 0; 7291 if ((Subtarget->hasNEON())) { 7292 return fastEmitInst_rr(AArch64::EORv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7293 } 7294 return 0; 7295} 7296 7297unsigned fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7298 if (RetVT.SimpleTy != MVT::v16i8) 7299 return 0; 7300 if ((Subtarget->hasNEON())) { 7301 return fastEmitInst_rr(AArch64::EORv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7302 } 7303 return 0; 7304} 7305 7306unsigned fastEmit_ISD_XOR_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7307 if (RetVT.SimpleTy != MVT::v4i16) 7308 return 0; 7309 if ((Subtarget->hasNEON())) { 7310 return fastEmitInst_rr(AArch64::EORv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7311 } 7312 return 0; 7313} 7314 7315unsigned fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7316 if (RetVT.SimpleTy != MVT::v8i16) 7317 return 0; 7318 if ((Subtarget->hasNEON())) { 7319 return fastEmitInst_rr(AArch64::EORv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7320 } 7321 return 0; 7322} 7323 7324unsigned fastEmit_ISD_XOR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7325 if (RetVT.SimpleTy != MVT::v2i32) 7326 return 0; 7327 if ((Subtarget->hasNEON())) { 7328 return fastEmitInst_rr(AArch64::EORv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7329 } 7330 return 0; 7331} 7332 7333unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7334 if (RetVT.SimpleTy != MVT::v4i32) 7335 return 0; 7336 if ((Subtarget->hasNEON())) { 7337 return fastEmitInst_rr(AArch64::EORv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7338 } 7339 return 0; 7340} 7341 7342unsigned fastEmit_ISD_XOR_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7343 if (RetVT.SimpleTy != MVT::v1i64) 7344 return 0; 7345 if ((Subtarget->hasNEON())) { 7346 return fastEmitInst_rr(AArch64::EORv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7347 } 7348 return 0; 7349} 7350 7351unsigned fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7352 if (RetVT.SimpleTy != MVT::v2i64) 7353 return 0; 7354 if ((Subtarget->hasNEON())) { 7355 return fastEmitInst_rr(AArch64::EORv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 7356 } 7357 return 0; 7358} 7359 7360unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 7361 switch (VT.SimpleTy) { 7362 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7363 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7364 case MVT::v8i8: return fastEmit_ISD_XOR_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7365 case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7366 case MVT::v4i16: return fastEmit_ISD_XOR_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7367 case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7368 case MVT::v2i32: return fastEmit_ISD_XOR_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7369 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7370 case MVT::v1i64: return fastEmit_ISD_XOR_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7371 case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7372 default: return 0; 7373 } 7374} 7375 7376// Top-level FastEmit function. 7377 7378unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override { 7379 switch (Opcode) { 7380 case AArch64ISD::CMEQ: return fastEmit_AArch64ISD_CMEQ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7381 case AArch64ISD::CMGE: return fastEmit_AArch64ISD_CMGE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7382 case AArch64ISD::CMGT: return fastEmit_AArch64ISD_CMGT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7383 case AArch64ISD::CMHI: return fastEmit_AArch64ISD_CMHI_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7384 case AArch64ISD::CMHS: return fastEmit_AArch64ISD_CMHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7385 case AArch64ISD::FCMEQ: return fastEmit_AArch64ISD_FCMEQ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7386 case AArch64ISD::FCMGE: return fastEmit_AArch64ISD_FCMGE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7387 case AArch64ISD::FCMGT: return fastEmit_AArch64ISD_FCMGT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7388 case AArch64ISD::FCMP: return fastEmit_AArch64ISD_FCMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7389 case AArch64ISD::FRECPS: return fastEmit_AArch64ISD_FRECPS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7390 case AArch64ISD::FRSQRTS: return fastEmit_AArch64ISD_FRSQRTS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7391 case AArch64ISD::SMULL: return fastEmit_AArch64ISD_SMULL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7392 case AArch64ISD::TRN1: return fastEmit_AArch64ISD_TRN1_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7393 case AArch64ISD::TRN2: return fastEmit_AArch64ISD_TRN2_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7394 case AArch64ISD::UMULL: return fastEmit_AArch64ISD_UMULL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7395 case AArch64ISD::UZP1: return fastEmit_AArch64ISD_UZP1_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7396 case AArch64ISD::UZP2: return fastEmit_AArch64ISD_UZP2_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7397 case AArch64ISD::ZIP1: return fastEmit_AArch64ISD_ZIP1_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7398 case AArch64ISD::ZIP2: return fastEmit_AArch64ISD_ZIP2_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7399 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7400 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7401 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7402 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7403 case ISD::FMAXNAN: return fastEmit_ISD_FMAXNAN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7404 case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7405 case ISD::FMINNAN: return fastEmit_ISD_FMINNAN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7406 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7407 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7408 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7409 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7410 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7411 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7412 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7413 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7414 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7415 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7416 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7417 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7418 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7419 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7420 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7421 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7422 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7423 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7424 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 7425 default: return 0; 7426 } 7427} 7428 7429// FastEmit functions for AArch64ISD::DUPLANE64. 7430 7431unsigned fastEmit_AArch64ISD_DUPLANE64_MVT_v2i64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7432 if (RetVT.SimpleTy != MVT::v2i64) 7433 return 0; 7434 if ((Subtarget->hasNEON())) { 7435 return fastEmitInst_ri(AArch64::DUPv2i64lane, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 7436 } 7437 return 0; 7438} 7439 7440unsigned fastEmit_AArch64ISD_DUPLANE64_MVT_v2f64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7441 if (RetVT.SimpleTy != MVT::v2f64) 7442 return 0; 7443 return fastEmitInst_ri(AArch64::DUPv2i64lane, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 7444} 7445 7446unsigned fastEmit_AArch64ISD_DUPLANE64_ri_Predicate_VectorIndexD(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7447 switch (VT.SimpleTy) { 7448 case MVT::v2i64: return fastEmit_AArch64ISD_DUPLANE64_MVT_v2i64_ri_Predicate_VectorIndexD(RetVT, Op0, Op0IsKill, imm1); 7449 case MVT::v2f64: return fastEmit_AArch64ISD_DUPLANE64_MVT_v2f64_ri_Predicate_VectorIndexD(RetVT, Op0, Op0IsKill, imm1); 7450 default: return 0; 7451 } 7452} 7453 7454// FastEmit functions for ISD::EXTRACT_VECTOR_ELT. 7455 7456unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7457 if (RetVT.SimpleTy != MVT::i64) 7458 return 0; 7459 if ((Subtarget->hasNEON())) { 7460 return fastEmitInst_ri(AArch64::UMOVvi64, &AArch64::GPR64RegClass, Op0, Op0IsKill, imm1); 7461 } 7462 return 0; 7463} 7464 7465unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7466 if (RetVT.SimpleTy != MVT::f64) 7467 return 0; 7468 return fastEmitInst_ri(AArch64::CPYi64, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 7469} 7470 7471unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexD(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7472 switch (VT.SimpleTy) { 7473 case MVT::v2i64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_VectorIndexD(RetVT, Op0, Op0IsKill, imm1); 7474 case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_VectorIndexD(RetVT, Op0, Op0IsKill, imm1); 7475 default: return 0; 7476 } 7477} 7478 7479// Top-level FastEmit function. 7480 7481unsigned fastEmit_ri_Predicate_VectorIndexD(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7482 switch (Opcode) { 7483 case AArch64ISD::DUPLANE64: return fastEmit_AArch64ISD_DUPLANE64_ri_Predicate_VectorIndexD(VT, RetVT, Op0, Op0IsKill, imm1); 7484 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexD(VT, RetVT, Op0, Op0IsKill, imm1); 7485 default: return 0; 7486 } 7487} 7488 7489// FastEmit functions for AArch64ISD::DUPLANE32. 7490 7491unsigned fastEmit_AArch64ISD_DUPLANE32_MVT_v4i32_MVT_v2i32_ri_Predicate_VectorIndexS(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7492 if ((Subtarget->hasNEON())) { 7493 return fastEmitInst_ri(AArch64::DUPv2i32lane, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 7494 } 7495 return 0; 7496} 7497 7498unsigned fastEmit_AArch64ISD_DUPLANE32_MVT_v4i32_MVT_v4i32_ri_Predicate_VectorIndexS(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7499 if ((Subtarget->hasNEON())) { 7500 return fastEmitInst_ri(AArch64::DUPv4i32lane, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 7501 } 7502 return 0; 7503} 7504 7505unsigned fastEmit_AArch64ISD_DUPLANE32_MVT_v4i32_ri_Predicate_VectorIndexS(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7506switch (RetVT.SimpleTy) { 7507 case MVT::v2i32: return fastEmit_AArch64ISD_DUPLANE32_MVT_v4i32_MVT_v2i32_ri_Predicate_VectorIndexS(Op0, Op0IsKill, imm1); 7508 case MVT::v4i32: return fastEmit_AArch64ISD_DUPLANE32_MVT_v4i32_MVT_v4i32_ri_Predicate_VectorIndexS(Op0, Op0IsKill, imm1); 7509 default: return 0; 7510} 7511} 7512 7513unsigned fastEmit_AArch64ISD_DUPLANE32_MVT_v4f32_MVT_v2f32_ri_Predicate_VectorIndexS(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7514 return fastEmitInst_ri(AArch64::DUPv2i32lane, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 7515} 7516 7517unsigned fastEmit_AArch64ISD_DUPLANE32_MVT_v4f32_MVT_v4f32_ri_Predicate_VectorIndexS(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7518 return fastEmitInst_ri(AArch64::DUPv4i32lane, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 7519} 7520 7521unsigned fastEmit_AArch64ISD_DUPLANE32_MVT_v4f32_ri_Predicate_VectorIndexS(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7522switch (RetVT.SimpleTy) { 7523 case MVT::v2f32: return fastEmit_AArch64ISD_DUPLANE32_MVT_v4f32_MVT_v2f32_ri_Predicate_VectorIndexS(Op0, Op0IsKill, imm1); 7524 case MVT::v4f32: return fastEmit_AArch64ISD_DUPLANE32_MVT_v4f32_MVT_v4f32_ri_Predicate_VectorIndexS(Op0, Op0IsKill, imm1); 7525 default: return 0; 7526} 7527} 7528 7529unsigned fastEmit_AArch64ISD_DUPLANE32_ri_Predicate_VectorIndexS(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7530 switch (VT.SimpleTy) { 7531 case MVT::v4i32: return fastEmit_AArch64ISD_DUPLANE32_MVT_v4i32_ri_Predicate_VectorIndexS(RetVT, Op0, Op0IsKill, imm1); 7532 case MVT::v4f32: return fastEmit_AArch64ISD_DUPLANE32_MVT_v4f32_ri_Predicate_VectorIndexS(RetVT, Op0, Op0IsKill, imm1); 7533 default: return 0; 7534 } 7535} 7536 7537// FastEmit functions for ISD::EXTRACT_VECTOR_ELT. 7538 7539unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_VectorIndexS(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7540 if (RetVT.SimpleTy != MVT::i32) 7541 return 0; 7542 if ((Subtarget->hasNEON())) { 7543 return fastEmitInst_ri(AArch64::UMOVvi32, &AArch64::GPR32RegClass, Op0, Op0IsKill, imm1); 7544 } 7545 return 0; 7546} 7547 7548unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_VectorIndexS(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7549 if (RetVT.SimpleTy != MVT::f32) 7550 return 0; 7551 return fastEmitInst_ri(AArch64::CPYi32, &AArch64::FPR32RegClass, Op0, Op0IsKill, imm1); 7552} 7553 7554unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexS(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7555 switch (VT.SimpleTy) { 7556 case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_VectorIndexS(RetVT, Op0, Op0IsKill, imm1); 7557 case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_VectorIndexS(RetVT, Op0, Op0IsKill, imm1); 7558 default: return 0; 7559 } 7560} 7561 7562// Top-level FastEmit function. 7563 7564unsigned fastEmit_ri_Predicate_VectorIndexS(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7565 switch (Opcode) { 7566 case AArch64ISD::DUPLANE32: return fastEmit_AArch64ISD_DUPLANE32_ri_Predicate_VectorIndexS(VT, RetVT, Op0, Op0IsKill, imm1); 7567 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexS(VT, RetVT, Op0, Op0IsKill, imm1); 7568 default: return 0; 7569 } 7570} 7571 7572// FastEmit functions for AArch64ISD::DUPLANE16. 7573 7574unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8i16_MVT_v4i16_ri_Predicate_VectorIndexH(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7575 if ((Subtarget->hasNEON())) { 7576 return fastEmitInst_ri(AArch64::DUPv4i16lane, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 7577 } 7578 return 0; 7579} 7580 7581unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8i16_MVT_v8i16_ri_Predicate_VectorIndexH(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7582 if ((Subtarget->hasNEON())) { 7583 return fastEmitInst_ri(AArch64::DUPv8i16lane, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 7584 } 7585 return 0; 7586} 7587 7588unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8i16_ri_Predicate_VectorIndexH(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7589switch (RetVT.SimpleTy) { 7590 case MVT::v4i16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8i16_MVT_v4i16_ri_Predicate_VectorIndexH(Op0, Op0IsKill, imm1); 7591 case MVT::v8i16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8i16_MVT_v8i16_ri_Predicate_VectorIndexH(Op0, Op0IsKill, imm1); 7592 default: return 0; 7593} 7594} 7595 7596unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8f16_MVT_v4f16_ri_Predicate_VectorIndexH(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7597 return fastEmitInst_ri(AArch64::DUPv4i16lane, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 7598} 7599 7600unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8f16_MVT_v8f16_ri_Predicate_VectorIndexH(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7601 return fastEmitInst_ri(AArch64::DUPv8i16lane, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 7602} 7603 7604unsigned fastEmit_AArch64ISD_DUPLANE16_MVT_v8f16_ri_Predicate_VectorIndexH(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7605switch (RetVT.SimpleTy) { 7606 case MVT::v4f16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8f16_MVT_v4f16_ri_Predicate_VectorIndexH(Op0, Op0IsKill, imm1); 7607 case MVT::v8f16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8f16_MVT_v8f16_ri_Predicate_VectorIndexH(Op0, Op0IsKill, imm1); 7608 default: return 0; 7609} 7610} 7611 7612unsigned fastEmit_AArch64ISD_DUPLANE16_ri_Predicate_VectorIndexH(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7613 switch (VT.SimpleTy) { 7614 case MVT::v8i16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8i16_ri_Predicate_VectorIndexH(RetVT, Op0, Op0IsKill, imm1); 7615 case MVT::v8f16: return fastEmit_AArch64ISD_DUPLANE16_MVT_v8f16_ri_Predicate_VectorIndexH(RetVT, Op0, Op0IsKill, imm1); 7616 default: return 0; 7617 } 7618} 7619 7620// FastEmit functions for ISD::EXTRACT_VECTOR_ELT. 7621 7622unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_VectorIndexH(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7623 if (RetVT.SimpleTy != MVT::i32) 7624 return 0; 7625 if ((Subtarget->hasNEON())) { 7626 return fastEmitInst_ri(AArch64::UMOVvi16, &AArch64::GPR32RegClass, Op0, Op0IsKill, imm1); 7627 } 7628 return 0; 7629} 7630 7631unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8f16_ri_Predicate_VectorIndexH(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7632 if (RetVT.SimpleTy != MVT::f16) 7633 return 0; 7634 return fastEmitInst_ri(AArch64::CPYi16, &AArch64::FPR16RegClass, Op0, Op0IsKill, imm1); 7635} 7636 7637unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexH(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7638 switch (VT.SimpleTy) { 7639 case MVT::v8i16: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_VectorIndexH(RetVT, Op0, Op0IsKill, imm1); 7640 case MVT::v8f16: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8f16_ri_Predicate_VectorIndexH(RetVT, Op0, Op0IsKill, imm1); 7641 default: return 0; 7642 } 7643} 7644 7645// Top-level FastEmit function. 7646 7647unsigned fastEmit_ri_Predicate_VectorIndexH(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7648 switch (Opcode) { 7649 case AArch64ISD::DUPLANE16: return fastEmit_AArch64ISD_DUPLANE16_ri_Predicate_VectorIndexH(VT, RetVT, Op0, Op0IsKill, imm1); 7650 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexH(VT, RetVT, Op0, Op0IsKill, imm1); 7651 default: return 0; 7652 } 7653} 7654 7655// FastEmit functions for AArch64ISD::DUPLANE8. 7656 7657unsigned fastEmit_AArch64ISD_DUPLANE8_MVT_v16i8_MVT_v8i8_ri_Predicate_VectorIndexB(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7658 if ((Subtarget->hasNEON())) { 7659 return fastEmitInst_ri(AArch64::DUPv8i8lane, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 7660 } 7661 return 0; 7662} 7663 7664unsigned fastEmit_AArch64ISD_DUPLANE8_MVT_v16i8_MVT_v16i8_ri_Predicate_VectorIndexB(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7665 if ((Subtarget->hasNEON())) { 7666 return fastEmitInst_ri(AArch64::DUPv16i8lane, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 7667 } 7668 return 0; 7669} 7670 7671unsigned fastEmit_AArch64ISD_DUPLANE8_MVT_v16i8_ri_Predicate_VectorIndexB(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7672switch (RetVT.SimpleTy) { 7673 case MVT::v8i8: return fastEmit_AArch64ISD_DUPLANE8_MVT_v16i8_MVT_v8i8_ri_Predicate_VectorIndexB(Op0, Op0IsKill, imm1); 7674 case MVT::v16i8: return fastEmit_AArch64ISD_DUPLANE8_MVT_v16i8_MVT_v16i8_ri_Predicate_VectorIndexB(Op0, Op0IsKill, imm1); 7675 default: return 0; 7676} 7677} 7678 7679unsigned fastEmit_AArch64ISD_DUPLANE8_ri_Predicate_VectorIndexB(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7680 switch (VT.SimpleTy) { 7681 case MVT::v16i8: return fastEmit_AArch64ISD_DUPLANE8_MVT_v16i8_ri_Predicate_VectorIndexB(RetVT, Op0, Op0IsKill, imm1); 7682 default: return 0; 7683 } 7684} 7685 7686// FastEmit functions for ISD::EXTRACT_VECTOR_ELT. 7687 7688unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_VectorIndexB(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7689 if (RetVT.SimpleTy != MVT::i32) 7690 return 0; 7691 if ((Subtarget->hasNEON())) { 7692 return fastEmitInst_ri(AArch64::UMOVvi8, &AArch64::GPR32RegClass, Op0, Op0IsKill, imm1); 7693 } 7694 return 0; 7695} 7696 7697unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexB(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7698 switch (VT.SimpleTy) { 7699 case MVT::v16i8: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_VectorIndexB(RetVT, Op0, Op0IsKill, imm1); 7700 default: return 0; 7701 } 7702} 7703 7704// Top-level FastEmit function. 7705 7706unsigned fastEmit_ri_Predicate_VectorIndexB(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7707 switch (Opcode) { 7708 case AArch64ISD::DUPLANE8: return fastEmit_AArch64ISD_DUPLANE8_ri_Predicate_VectorIndexB(VT, RetVT, Op0, Op0IsKill, imm1); 7709 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_VectorIndexB(VT, RetVT, Op0, Op0IsKill, imm1); 7710 default: return 0; 7711 } 7712} 7713 7714// FastEmit functions for AArch64ISD::SQSHLU_I. 7715 7716unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7717 if (RetVT.SimpleTy != MVT::i64) 7718 return 0; 7719 if ((Subtarget->hasNEON())) { 7720 return fastEmitInst_ri(AArch64::SQSHLUd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 7721 } 7722 return 0; 7723} 7724 7725unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v1i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7726 if (RetVT.SimpleTy != MVT::v1i64) 7727 return 0; 7728 if ((Subtarget->hasNEON())) { 7729 return fastEmitInst_ri(AArch64::SQSHLUd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 7730 } 7731 return 0; 7732} 7733 7734unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v2i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7735 if (RetVT.SimpleTy != MVT::v2i64) 7736 return 0; 7737 if ((Subtarget->hasNEON())) { 7738 return fastEmitInst_ri(AArch64::SQSHLUv2i64_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 7739 } 7740 return 0; 7741} 7742 7743unsigned fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL64(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7744 switch (VT.SimpleTy) { 7745 case MVT::i64: return fastEmit_AArch64ISD_SQSHLU_I_MVT_i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 7746 case MVT::v1i64: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v1i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 7747 case MVT::v2i64: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v2i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 7748 default: return 0; 7749 } 7750} 7751 7752// FastEmit functions for AArch64ISD::SQSHL_I. 7753 7754unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7755 if (RetVT.SimpleTy != MVT::i64) 7756 return 0; 7757 if ((Subtarget->hasNEON())) { 7758 return fastEmitInst_ri(AArch64::SQSHLd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 7759 } 7760 return 0; 7761} 7762 7763unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v1i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7764 if (RetVT.SimpleTy != MVT::v1i64) 7765 return 0; 7766 if ((Subtarget->hasNEON())) { 7767 return fastEmitInst_ri(AArch64::SQSHLd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 7768 } 7769 return 0; 7770} 7771 7772unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v2i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7773 if (RetVT.SimpleTy != MVT::v2i64) 7774 return 0; 7775 if ((Subtarget->hasNEON())) { 7776 return fastEmitInst_ri(AArch64::SQSHLv2i64_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 7777 } 7778 return 0; 7779} 7780 7781unsigned fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL64(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7782 switch (VT.SimpleTy) { 7783 case MVT::i64: return fastEmit_AArch64ISD_SQSHL_I_MVT_i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 7784 case MVT::v1i64: return fastEmit_AArch64ISD_SQSHL_I_MVT_v1i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 7785 case MVT::v2i64: return fastEmit_AArch64ISD_SQSHL_I_MVT_v2i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 7786 default: return 0; 7787 } 7788} 7789 7790// FastEmit functions for AArch64ISD::UQSHL_I. 7791 7792unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7793 if (RetVT.SimpleTy != MVT::i64) 7794 return 0; 7795 if ((Subtarget->hasNEON())) { 7796 return fastEmitInst_ri(AArch64::UQSHLd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 7797 } 7798 return 0; 7799} 7800 7801unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v1i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7802 if (RetVT.SimpleTy != MVT::v1i64) 7803 return 0; 7804 if ((Subtarget->hasNEON())) { 7805 return fastEmitInst_ri(AArch64::UQSHLd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 7806 } 7807 return 0; 7808} 7809 7810unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v2i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7811 if (RetVT.SimpleTy != MVT::v2i64) 7812 return 0; 7813 if ((Subtarget->hasNEON())) { 7814 return fastEmitInst_ri(AArch64::UQSHLv2i64_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 7815 } 7816 return 0; 7817} 7818 7819unsigned fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL64(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7820 switch (VT.SimpleTy) { 7821 case MVT::i64: return fastEmit_AArch64ISD_UQSHL_I_MVT_i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 7822 case MVT::v1i64: return fastEmit_AArch64ISD_UQSHL_I_MVT_v1i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 7823 case MVT::v2i64: return fastEmit_AArch64ISD_UQSHL_I_MVT_v2i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 7824 default: return 0; 7825 } 7826} 7827 7828// FastEmit functions for AArch64ISD::VSHL. 7829 7830unsigned fastEmit_AArch64ISD_VSHL_MVT_v1i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7831 if (RetVT.SimpleTy != MVT::v1i64) 7832 return 0; 7833 if ((Subtarget->hasNEON())) { 7834 return fastEmitInst_ri(AArch64::SHLd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 7835 } 7836 return 0; 7837} 7838 7839unsigned fastEmit_AArch64ISD_VSHL_MVT_v2i64_ri_Predicate_vecshiftL64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7840 if (RetVT.SimpleTy != MVT::v2i64) 7841 return 0; 7842 if ((Subtarget->hasNEON())) { 7843 return fastEmitInst_ri(AArch64::SHLv2i64_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 7844 } 7845 return 0; 7846} 7847 7848unsigned fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL64(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7849 switch (VT.SimpleTy) { 7850 case MVT::v1i64: return fastEmit_AArch64ISD_VSHL_MVT_v1i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 7851 case MVT::v2i64: return fastEmit_AArch64ISD_VSHL_MVT_v2i64_ri_Predicate_vecshiftL64(RetVT, Op0, Op0IsKill, imm1); 7852 default: return 0; 7853 } 7854} 7855 7856// Top-level FastEmit function. 7857 7858unsigned fastEmit_ri_Predicate_vecshiftL64(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7859 switch (Opcode) { 7860 case AArch64ISD::SQSHLU_I: return fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL64(VT, RetVT, Op0, Op0IsKill, imm1); 7861 case AArch64ISD::SQSHL_I: return fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL64(VT, RetVT, Op0, Op0IsKill, imm1); 7862 case AArch64ISD::UQSHL_I: return fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL64(VT, RetVT, Op0, Op0IsKill, imm1); 7863 case AArch64ISD::VSHL: return fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL64(VT, RetVT, Op0, Op0IsKill, imm1); 7864 default: return 0; 7865 } 7866} 7867 7868// FastEmit functions for AArch64ISD::SQSHLU_I. 7869 7870unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7871 if (RetVT.SimpleTy != MVT::i32) 7872 return 0; 7873 if ((Subtarget->hasNEON())) { 7874 return fastEmitInst_ri(AArch64::SQSHLUs, &AArch64::FPR32RegClass, Op0, Op0IsKill, imm1); 7875 } 7876 return 0; 7877} 7878 7879unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v2i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7880 if (RetVT.SimpleTy != MVT::v2i32) 7881 return 0; 7882 if ((Subtarget->hasNEON())) { 7883 return fastEmitInst_ri(AArch64::SQSHLUv2i32_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 7884 } 7885 return 0; 7886} 7887 7888unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v4i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7889 if (RetVT.SimpleTy != MVT::v4i32) 7890 return 0; 7891 if ((Subtarget->hasNEON())) { 7892 return fastEmitInst_ri(AArch64::SQSHLUv4i32_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 7893 } 7894 return 0; 7895} 7896 7897unsigned fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7898 switch (VT.SimpleTy) { 7899 case MVT::i32: return fastEmit_AArch64ISD_SQSHLU_I_MVT_i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 7900 case MVT::v2i32: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v2i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 7901 case MVT::v4i32: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v4i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 7902 default: return 0; 7903 } 7904} 7905 7906// FastEmit functions for AArch64ISD::SQSHL_I. 7907 7908unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7909 if (RetVT.SimpleTy != MVT::i32) 7910 return 0; 7911 if ((Subtarget->hasNEON())) { 7912 return fastEmitInst_ri(AArch64::SQSHLs, &AArch64::FPR32RegClass, Op0, Op0IsKill, imm1); 7913 } 7914 return 0; 7915} 7916 7917unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v2i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7918 if (RetVT.SimpleTy != MVT::v2i32) 7919 return 0; 7920 if ((Subtarget->hasNEON())) { 7921 return fastEmitInst_ri(AArch64::SQSHLv2i32_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 7922 } 7923 return 0; 7924} 7925 7926unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v4i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7927 if (RetVT.SimpleTy != MVT::v4i32) 7928 return 0; 7929 if ((Subtarget->hasNEON())) { 7930 return fastEmitInst_ri(AArch64::SQSHLv4i32_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 7931 } 7932 return 0; 7933} 7934 7935unsigned fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7936 switch (VT.SimpleTy) { 7937 case MVT::i32: return fastEmit_AArch64ISD_SQSHL_I_MVT_i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 7938 case MVT::v2i32: return fastEmit_AArch64ISD_SQSHL_I_MVT_v2i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 7939 case MVT::v4i32: return fastEmit_AArch64ISD_SQSHL_I_MVT_v4i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 7940 default: return 0; 7941 } 7942} 7943 7944// FastEmit functions for AArch64ISD::UQSHL_I. 7945 7946unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7947 if (RetVT.SimpleTy != MVT::i32) 7948 return 0; 7949 if ((Subtarget->hasNEON())) { 7950 return fastEmitInst_ri(AArch64::UQSHLs, &AArch64::FPR32RegClass, Op0, Op0IsKill, imm1); 7951 } 7952 return 0; 7953} 7954 7955unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v2i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7956 if (RetVT.SimpleTy != MVT::v2i32) 7957 return 0; 7958 if ((Subtarget->hasNEON())) { 7959 return fastEmitInst_ri(AArch64::UQSHLv2i32_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 7960 } 7961 return 0; 7962} 7963 7964unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v4i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7965 if (RetVT.SimpleTy != MVT::v4i32) 7966 return 0; 7967 if ((Subtarget->hasNEON())) { 7968 return fastEmitInst_ri(AArch64::UQSHLv4i32_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 7969 } 7970 return 0; 7971} 7972 7973unsigned fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7974 switch (VT.SimpleTy) { 7975 case MVT::i32: return fastEmit_AArch64ISD_UQSHL_I_MVT_i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 7976 case MVT::v2i32: return fastEmit_AArch64ISD_UQSHL_I_MVT_v2i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 7977 case MVT::v4i32: return fastEmit_AArch64ISD_UQSHL_I_MVT_v4i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 7978 default: return 0; 7979 } 7980} 7981 7982// FastEmit functions for AArch64ISD::VSHL. 7983 7984unsigned fastEmit_AArch64ISD_VSHL_MVT_v2i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7985 if (RetVT.SimpleTy != MVT::v2i32) 7986 return 0; 7987 if ((Subtarget->hasNEON())) { 7988 return fastEmitInst_ri(AArch64::SHLv2i32_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 7989 } 7990 return 0; 7991} 7992 7993unsigned fastEmit_AArch64ISD_VSHL_MVT_v4i32_ri_Predicate_vecshiftL32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7994 if (RetVT.SimpleTy != MVT::v4i32) 7995 return 0; 7996 if ((Subtarget->hasNEON())) { 7997 return fastEmitInst_ri(AArch64::SHLv4i32_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 7998 } 7999 return 0; 8000} 8001 8002unsigned fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8003 switch (VT.SimpleTy) { 8004 case MVT::v2i32: return fastEmit_AArch64ISD_VSHL_MVT_v2i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 8005 case MVT::v4i32: return fastEmit_AArch64ISD_VSHL_MVT_v4i32_ri_Predicate_vecshiftL32(RetVT, Op0, Op0IsKill, imm1); 8006 default: return 0; 8007 } 8008} 8009 8010// Top-level FastEmit function. 8011 8012unsigned fastEmit_ri_Predicate_vecshiftL32(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8013 switch (Opcode) { 8014 case AArch64ISD::SQSHLU_I: return fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL32(VT, RetVT, Op0, Op0IsKill, imm1); 8015 case AArch64ISD::SQSHL_I: return fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL32(VT, RetVT, Op0, Op0IsKill, imm1); 8016 case AArch64ISD::UQSHL_I: return fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL32(VT, RetVT, Op0, Op0IsKill, imm1); 8017 case AArch64ISD::VSHL: return fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL32(VT, RetVT, Op0, Op0IsKill, imm1); 8018 default: return 0; 8019 } 8020} 8021 8022// FastEmit functions for AArch64ISD::SRSHR_I. 8023 8024unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8025 if (RetVT.SimpleTy != MVT::i64) 8026 return 0; 8027 if ((Subtarget->hasNEON())) { 8028 return fastEmitInst_ri(AArch64::SRSHRd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8029 } 8030 return 0; 8031} 8032 8033unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v1i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8034 if (RetVT.SimpleTy != MVT::v1i64) 8035 return 0; 8036 if ((Subtarget->hasNEON())) { 8037 return fastEmitInst_ri(AArch64::SRSHRd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8038 } 8039 return 0; 8040} 8041 8042unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v2i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8043 if (RetVT.SimpleTy != MVT::v2i64) 8044 return 0; 8045 if ((Subtarget->hasNEON())) { 8046 return fastEmitInst_ri(AArch64::SRSHRv2i64_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8047 } 8048 return 0; 8049} 8050 8051unsigned fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR64(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8052 switch (VT.SimpleTy) { 8053 case MVT::i64: return fastEmit_AArch64ISD_SRSHR_I_MVT_i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 8054 case MVT::v1i64: return fastEmit_AArch64ISD_SRSHR_I_MVT_v1i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 8055 case MVT::v2i64: return fastEmit_AArch64ISD_SRSHR_I_MVT_v2i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 8056 default: return 0; 8057 } 8058} 8059 8060// FastEmit functions for AArch64ISD::URSHR_I. 8061 8062unsigned fastEmit_AArch64ISD_URSHR_I_MVT_i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8063 if (RetVT.SimpleTy != MVT::i64) 8064 return 0; 8065 if ((Subtarget->hasNEON())) { 8066 return fastEmitInst_ri(AArch64::URSHRd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8067 } 8068 return 0; 8069} 8070 8071unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v1i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8072 if (RetVT.SimpleTy != MVT::v1i64) 8073 return 0; 8074 if ((Subtarget->hasNEON())) { 8075 return fastEmitInst_ri(AArch64::URSHRd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8076 } 8077 return 0; 8078} 8079 8080unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v2i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8081 if (RetVT.SimpleTy != MVT::v2i64) 8082 return 0; 8083 if ((Subtarget->hasNEON())) { 8084 return fastEmitInst_ri(AArch64::URSHRv2i64_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8085 } 8086 return 0; 8087} 8088 8089unsigned fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR64(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8090 switch (VT.SimpleTy) { 8091 case MVT::i64: return fastEmit_AArch64ISD_URSHR_I_MVT_i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 8092 case MVT::v1i64: return fastEmit_AArch64ISD_URSHR_I_MVT_v1i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 8093 case MVT::v2i64: return fastEmit_AArch64ISD_URSHR_I_MVT_v2i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 8094 default: return 0; 8095 } 8096} 8097 8098// FastEmit functions for AArch64ISD::VASHR. 8099 8100unsigned fastEmit_AArch64ISD_VASHR_MVT_i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8101 if (RetVT.SimpleTy != MVT::i64) 8102 return 0; 8103 if ((Subtarget->hasNEON())) { 8104 return fastEmitInst_ri(AArch64::SSHRd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8105 } 8106 return 0; 8107} 8108 8109unsigned fastEmit_AArch64ISD_VASHR_MVT_v1i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8110 if (RetVT.SimpleTy != MVT::v1i64) 8111 return 0; 8112 if ((Subtarget->hasNEON())) { 8113 return fastEmitInst_ri(AArch64::SSHRd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8114 } 8115 return 0; 8116} 8117 8118unsigned fastEmit_AArch64ISD_VASHR_MVT_v2i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8119 if (RetVT.SimpleTy != MVT::v2i64) 8120 return 0; 8121 if ((Subtarget->hasNEON())) { 8122 return fastEmitInst_ri(AArch64::SSHRv2i64_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8123 } 8124 return 0; 8125} 8126 8127unsigned fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR64(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8128 switch (VT.SimpleTy) { 8129 case MVT::i64: return fastEmit_AArch64ISD_VASHR_MVT_i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 8130 case MVT::v1i64: return fastEmit_AArch64ISD_VASHR_MVT_v1i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 8131 case MVT::v2i64: return fastEmit_AArch64ISD_VASHR_MVT_v2i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 8132 default: return 0; 8133 } 8134} 8135 8136// FastEmit functions for AArch64ISD::VLSHR. 8137 8138unsigned fastEmit_AArch64ISD_VLSHR_MVT_i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8139 if (RetVT.SimpleTy != MVT::i64) 8140 return 0; 8141 if ((Subtarget->hasNEON())) { 8142 return fastEmitInst_ri(AArch64::USHRd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8143 } 8144 return 0; 8145} 8146 8147unsigned fastEmit_AArch64ISD_VLSHR_MVT_v1i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8148 if (RetVT.SimpleTy != MVT::v1i64) 8149 return 0; 8150 if ((Subtarget->hasNEON())) { 8151 return fastEmitInst_ri(AArch64::USHRd, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8152 } 8153 return 0; 8154} 8155 8156unsigned fastEmit_AArch64ISD_VLSHR_MVT_v2i64_ri_Predicate_vecshiftR64(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8157 if (RetVT.SimpleTy != MVT::v2i64) 8158 return 0; 8159 if ((Subtarget->hasNEON())) { 8160 return fastEmitInst_ri(AArch64::USHRv2i64_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8161 } 8162 return 0; 8163} 8164 8165unsigned fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR64(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8166 switch (VT.SimpleTy) { 8167 case MVT::i64: return fastEmit_AArch64ISD_VLSHR_MVT_i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 8168 case MVT::v1i64: return fastEmit_AArch64ISD_VLSHR_MVT_v1i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 8169 case MVT::v2i64: return fastEmit_AArch64ISD_VLSHR_MVT_v2i64_ri_Predicate_vecshiftR64(RetVT, Op0, Op0IsKill, imm1); 8170 default: return 0; 8171 } 8172} 8173 8174// Top-level FastEmit function. 8175 8176unsigned fastEmit_ri_Predicate_vecshiftR64(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8177 switch (Opcode) { 8178 case AArch64ISD::SRSHR_I: return fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR64(VT, RetVT, Op0, Op0IsKill, imm1); 8179 case AArch64ISD::URSHR_I: return fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR64(VT, RetVT, Op0, Op0IsKill, imm1); 8180 case AArch64ISD::VASHR: return fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR64(VT, RetVT, Op0, Op0IsKill, imm1); 8181 case AArch64ISD::VLSHR: return fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR64(VT, RetVT, Op0, Op0IsKill, imm1); 8182 default: return 0; 8183 } 8184} 8185 8186// FastEmit functions for AArch64ISD::SQSHLU_I. 8187 8188unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v8i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8189 if (RetVT.SimpleTy != MVT::v8i8) 8190 return 0; 8191 if ((Subtarget->hasNEON())) { 8192 return fastEmitInst_ri(AArch64::SQSHLUv8i8_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8193 } 8194 return 0; 8195} 8196 8197unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v16i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8198 if (RetVT.SimpleTy != MVT::v16i8) 8199 return 0; 8200 if ((Subtarget->hasNEON())) { 8201 return fastEmitInst_ri(AArch64::SQSHLUv16i8_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8202 } 8203 return 0; 8204} 8205 8206unsigned fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8207 switch (VT.SimpleTy) { 8208 case MVT::v8i8: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v8i8_ri_Predicate_vecshiftL8(RetVT, Op0, Op0IsKill, imm1); 8209 case MVT::v16i8: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v16i8_ri_Predicate_vecshiftL8(RetVT, Op0, Op0IsKill, imm1); 8210 default: return 0; 8211 } 8212} 8213 8214// FastEmit functions for AArch64ISD::SQSHL_I. 8215 8216unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v8i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8217 if (RetVT.SimpleTy != MVT::v8i8) 8218 return 0; 8219 if ((Subtarget->hasNEON())) { 8220 return fastEmitInst_ri(AArch64::SQSHLv8i8_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8221 } 8222 return 0; 8223} 8224 8225unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v16i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8226 if (RetVT.SimpleTy != MVT::v16i8) 8227 return 0; 8228 if ((Subtarget->hasNEON())) { 8229 return fastEmitInst_ri(AArch64::SQSHLv16i8_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8230 } 8231 return 0; 8232} 8233 8234unsigned fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8235 switch (VT.SimpleTy) { 8236 case MVT::v8i8: return fastEmit_AArch64ISD_SQSHL_I_MVT_v8i8_ri_Predicate_vecshiftL8(RetVT, Op0, Op0IsKill, imm1); 8237 case MVT::v16i8: return fastEmit_AArch64ISD_SQSHL_I_MVT_v16i8_ri_Predicate_vecshiftL8(RetVT, Op0, Op0IsKill, imm1); 8238 default: return 0; 8239 } 8240} 8241 8242// FastEmit functions for AArch64ISD::UQSHL_I. 8243 8244unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v8i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8245 if (RetVT.SimpleTy != MVT::v8i8) 8246 return 0; 8247 if ((Subtarget->hasNEON())) { 8248 return fastEmitInst_ri(AArch64::UQSHLv8i8_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8249 } 8250 return 0; 8251} 8252 8253unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v16i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8254 if (RetVT.SimpleTy != MVT::v16i8) 8255 return 0; 8256 if ((Subtarget->hasNEON())) { 8257 return fastEmitInst_ri(AArch64::UQSHLv16i8_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8258 } 8259 return 0; 8260} 8261 8262unsigned fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8263 switch (VT.SimpleTy) { 8264 case MVT::v8i8: return fastEmit_AArch64ISD_UQSHL_I_MVT_v8i8_ri_Predicate_vecshiftL8(RetVT, Op0, Op0IsKill, imm1); 8265 case MVT::v16i8: return fastEmit_AArch64ISD_UQSHL_I_MVT_v16i8_ri_Predicate_vecshiftL8(RetVT, Op0, Op0IsKill, imm1); 8266 default: return 0; 8267 } 8268} 8269 8270// FastEmit functions for AArch64ISD::VSHL. 8271 8272unsigned fastEmit_AArch64ISD_VSHL_MVT_v8i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8273 if (RetVT.SimpleTy != MVT::v8i8) 8274 return 0; 8275 if ((Subtarget->hasNEON())) { 8276 return fastEmitInst_ri(AArch64::SHLv8i8_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8277 } 8278 return 0; 8279} 8280 8281unsigned fastEmit_AArch64ISD_VSHL_MVT_v16i8_ri_Predicate_vecshiftL8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8282 if (RetVT.SimpleTy != MVT::v16i8) 8283 return 0; 8284 if ((Subtarget->hasNEON())) { 8285 return fastEmitInst_ri(AArch64::SHLv16i8_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8286 } 8287 return 0; 8288} 8289 8290unsigned fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8291 switch (VT.SimpleTy) { 8292 case MVT::v8i8: return fastEmit_AArch64ISD_VSHL_MVT_v8i8_ri_Predicate_vecshiftL8(RetVT, Op0, Op0IsKill, imm1); 8293 case MVT::v16i8: return fastEmit_AArch64ISD_VSHL_MVT_v16i8_ri_Predicate_vecshiftL8(RetVT, Op0, Op0IsKill, imm1); 8294 default: return 0; 8295 } 8296} 8297 8298// Top-level FastEmit function. 8299 8300unsigned fastEmit_ri_Predicate_vecshiftL8(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8301 switch (Opcode) { 8302 case AArch64ISD::SQSHLU_I: return fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL8(VT, RetVT, Op0, Op0IsKill, imm1); 8303 case AArch64ISD::SQSHL_I: return fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL8(VT, RetVT, Op0, Op0IsKill, imm1); 8304 case AArch64ISD::UQSHL_I: return fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL8(VT, RetVT, Op0, Op0IsKill, imm1); 8305 case AArch64ISD::VSHL: return fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL8(VT, RetVT, Op0, Op0IsKill, imm1); 8306 default: return 0; 8307 } 8308} 8309 8310// FastEmit functions for AArch64ISD::SQSHLU_I. 8311 8312unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v4i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8313 if (RetVT.SimpleTy != MVT::v4i16) 8314 return 0; 8315 if ((Subtarget->hasNEON())) { 8316 return fastEmitInst_ri(AArch64::SQSHLUv4i16_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8317 } 8318 return 0; 8319} 8320 8321unsigned fastEmit_AArch64ISD_SQSHLU_I_MVT_v8i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8322 if (RetVT.SimpleTy != MVT::v8i16) 8323 return 0; 8324 if ((Subtarget->hasNEON())) { 8325 return fastEmitInst_ri(AArch64::SQSHLUv8i16_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8326 } 8327 return 0; 8328} 8329 8330unsigned fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8331 switch (VT.SimpleTy) { 8332 case MVT::v4i16: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v4i16_ri_Predicate_vecshiftL16(RetVT, Op0, Op0IsKill, imm1); 8333 case MVT::v8i16: return fastEmit_AArch64ISD_SQSHLU_I_MVT_v8i16_ri_Predicate_vecshiftL16(RetVT, Op0, Op0IsKill, imm1); 8334 default: return 0; 8335 } 8336} 8337 8338// FastEmit functions for AArch64ISD::SQSHL_I. 8339 8340unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v4i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8341 if (RetVT.SimpleTy != MVT::v4i16) 8342 return 0; 8343 if ((Subtarget->hasNEON())) { 8344 return fastEmitInst_ri(AArch64::SQSHLv4i16_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8345 } 8346 return 0; 8347} 8348 8349unsigned fastEmit_AArch64ISD_SQSHL_I_MVT_v8i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8350 if (RetVT.SimpleTy != MVT::v8i16) 8351 return 0; 8352 if ((Subtarget->hasNEON())) { 8353 return fastEmitInst_ri(AArch64::SQSHLv8i16_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8354 } 8355 return 0; 8356} 8357 8358unsigned fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8359 switch (VT.SimpleTy) { 8360 case MVT::v4i16: return fastEmit_AArch64ISD_SQSHL_I_MVT_v4i16_ri_Predicate_vecshiftL16(RetVT, Op0, Op0IsKill, imm1); 8361 case MVT::v8i16: return fastEmit_AArch64ISD_SQSHL_I_MVT_v8i16_ri_Predicate_vecshiftL16(RetVT, Op0, Op0IsKill, imm1); 8362 default: return 0; 8363 } 8364} 8365 8366// FastEmit functions for AArch64ISD::UQSHL_I. 8367 8368unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v4i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8369 if (RetVT.SimpleTy != MVT::v4i16) 8370 return 0; 8371 if ((Subtarget->hasNEON())) { 8372 return fastEmitInst_ri(AArch64::UQSHLv4i16_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8373 } 8374 return 0; 8375} 8376 8377unsigned fastEmit_AArch64ISD_UQSHL_I_MVT_v8i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8378 if (RetVT.SimpleTy != MVT::v8i16) 8379 return 0; 8380 if ((Subtarget->hasNEON())) { 8381 return fastEmitInst_ri(AArch64::UQSHLv8i16_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8382 } 8383 return 0; 8384} 8385 8386unsigned fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8387 switch (VT.SimpleTy) { 8388 case MVT::v4i16: return fastEmit_AArch64ISD_UQSHL_I_MVT_v4i16_ri_Predicate_vecshiftL16(RetVT, Op0, Op0IsKill, imm1); 8389 case MVT::v8i16: return fastEmit_AArch64ISD_UQSHL_I_MVT_v8i16_ri_Predicate_vecshiftL16(RetVT, Op0, Op0IsKill, imm1); 8390 default: return 0; 8391 } 8392} 8393 8394// FastEmit functions for AArch64ISD::VSHL. 8395 8396unsigned fastEmit_AArch64ISD_VSHL_MVT_v4i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8397 if (RetVT.SimpleTy != MVT::v4i16) 8398 return 0; 8399 if ((Subtarget->hasNEON())) { 8400 return fastEmitInst_ri(AArch64::SHLv4i16_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8401 } 8402 return 0; 8403} 8404 8405unsigned fastEmit_AArch64ISD_VSHL_MVT_v8i16_ri_Predicate_vecshiftL16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8406 if (RetVT.SimpleTy != MVT::v8i16) 8407 return 0; 8408 if ((Subtarget->hasNEON())) { 8409 return fastEmitInst_ri(AArch64::SHLv8i16_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8410 } 8411 return 0; 8412} 8413 8414unsigned fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8415 switch (VT.SimpleTy) { 8416 case MVT::v4i16: return fastEmit_AArch64ISD_VSHL_MVT_v4i16_ri_Predicate_vecshiftL16(RetVT, Op0, Op0IsKill, imm1); 8417 case MVT::v8i16: return fastEmit_AArch64ISD_VSHL_MVT_v8i16_ri_Predicate_vecshiftL16(RetVT, Op0, Op0IsKill, imm1); 8418 default: return 0; 8419 } 8420} 8421 8422// Top-level FastEmit function. 8423 8424unsigned fastEmit_ri_Predicate_vecshiftL16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8425 switch (Opcode) { 8426 case AArch64ISD::SQSHLU_I: return fastEmit_AArch64ISD_SQSHLU_I_ri_Predicate_vecshiftL16(VT, RetVT, Op0, Op0IsKill, imm1); 8427 case AArch64ISD::SQSHL_I: return fastEmit_AArch64ISD_SQSHL_I_ri_Predicate_vecshiftL16(VT, RetVT, Op0, Op0IsKill, imm1); 8428 case AArch64ISD::UQSHL_I: return fastEmit_AArch64ISD_UQSHL_I_ri_Predicate_vecshiftL16(VT, RetVT, Op0, Op0IsKill, imm1); 8429 case AArch64ISD::VSHL: return fastEmit_AArch64ISD_VSHL_ri_Predicate_vecshiftL16(VT, RetVT, Op0, Op0IsKill, imm1); 8430 default: return 0; 8431 } 8432} 8433 8434// FastEmit functions for AArch64ISD::SRSHR_I. 8435 8436unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v8i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8437 if (RetVT.SimpleTy != MVT::v8i8) 8438 return 0; 8439 if ((Subtarget->hasNEON())) { 8440 return fastEmitInst_ri(AArch64::SRSHRv8i8_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8441 } 8442 return 0; 8443} 8444 8445unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v16i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8446 if (RetVT.SimpleTy != MVT::v16i8) 8447 return 0; 8448 if ((Subtarget->hasNEON())) { 8449 return fastEmitInst_ri(AArch64::SRSHRv16i8_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8450 } 8451 return 0; 8452} 8453 8454unsigned fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8455 switch (VT.SimpleTy) { 8456 case MVT::v8i8: return fastEmit_AArch64ISD_SRSHR_I_MVT_v8i8_ri_Predicate_vecshiftR8(RetVT, Op0, Op0IsKill, imm1); 8457 case MVT::v16i8: return fastEmit_AArch64ISD_SRSHR_I_MVT_v16i8_ri_Predicate_vecshiftR8(RetVT, Op0, Op0IsKill, imm1); 8458 default: return 0; 8459 } 8460} 8461 8462// FastEmit functions for AArch64ISD::URSHR_I. 8463 8464unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v8i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8465 if (RetVT.SimpleTy != MVT::v8i8) 8466 return 0; 8467 if ((Subtarget->hasNEON())) { 8468 return fastEmitInst_ri(AArch64::URSHRv8i8_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8469 } 8470 return 0; 8471} 8472 8473unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v16i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8474 if (RetVT.SimpleTy != MVT::v16i8) 8475 return 0; 8476 if ((Subtarget->hasNEON())) { 8477 return fastEmitInst_ri(AArch64::URSHRv16i8_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8478 } 8479 return 0; 8480} 8481 8482unsigned fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8483 switch (VT.SimpleTy) { 8484 case MVT::v8i8: return fastEmit_AArch64ISD_URSHR_I_MVT_v8i8_ri_Predicate_vecshiftR8(RetVT, Op0, Op0IsKill, imm1); 8485 case MVT::v16i8: return fastEmit_AArch64ISD_URSHR_I_MVT_v16i8_ri_Predicate_vecshiftR8(RetVT, Op0, Op0IsKill, imm1); 8486 default: return 0; 8487 } 8488} 8489 8490// FastEmit functions for AArch64ISD::VASHR. 8491 8492unsigned fastEmit_AArch64ISD_VASHR_MVT_v8i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8493 if (RetVT.SimpleTy != MVT::v8i8) 8494 return 0; 8495 if ((Subtarget->hasNEON())) { 8496 return fastEmitInst_ri(AArch64::SSHRv8i8_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8497 } 8498 return 0; 8499} 8500 8501unsigned fastEmit_AArch64ISD_VASHR_MVT_v16i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8502 if (RetVT.SimpleTy != MVT::v16i8) 8503 return 0; 8504 if ((Subtarget->hasNEON())) { 8505 return fastEmitInst_ri(AArch64::SSHRv16i8_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8506 } 8507 return 0; 8508} 8509 8510unsigned fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8511 switch (VT.SimpleTy) { 8512 case MVT::v8i8: return fastEmit_AArch64ISD_VASHR_MVT_v8i8_ri_Predicate_vecshiftR8(RetVT, Op0, Op0IsKill, imm1); 8513 case MVT::v16i8: return fastEmit_AArch64ISD_VASHR_MVT_v16i8_ri_Predicate_vecshiftR8(RetVT, Op0, Op0IsKill, imm1); 8514 default: return 0; 8515 } 8516} 8517 8518// FastEmit functions for AArch64ISD::VLSHR. 8519 8520unsigned fastEmit_AArch64ISD_VLSHR_MVT_v8i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8521 if (RetVT.SimpleTy != MVT::v8i8) 8522 return 0; 8523 if ((Subtarget->hasNEON())) { 8524 return fastEmitInst_ri(AArch64::USHRv8i8_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8525 } 8526 return 0; 8527} 8528 8529unsigned fastEmit_AArch64ISD_VLSHR_MVT_v16i8_ri_Predicate_vecshiftR8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8530 if (RetVT.SimpleTy != MVT::v16i8) 8531 return 0; 8532 if ((Subtarget->hasNEON())) { 8533 return fastEmitInst_ri(AArch64::USHRv16i8_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8534 } 8535 return 0; 8536} 8537 8538unsigned fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8539 switch (VT.SimpleTy) { 8540 case MVT::v8i8: return fastEmit_AArch64ISD_VLSHR_MVT_v8i8_ri_Predicate_vecshiftR8(RetVT, Op0, Op0IsKill, imm1); 8541 case MVT::v16i8: return fastEmit_AArch64ISD_VLSHR_MVT_v16i8_ri_Predicate_vecshiftR8(RetVT, Op0, Op0IsKill, imm1); 8542 default: return 0; 8543 } 8544} 8545 8546// Top-level FastEmit function. 8547 8548unsigned fastEmit_ri_Predicate_vecshiftR8(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8549 switch (Opcode) { 8550 case AArch64ISD::SRSHR_I: return fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR8(VT, RetVT, Op0, Op0IsKill, imm1); 8551 case AArch64ISD::URSHR_I: return fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR8(VT, RetVT, Op0, Op0IsKill, imm1); 8552 case AArch64ISD::VASHR: return fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR8(VT, RetVT, Op0, Op0IsKill, imm1); 8553 case AArch64ISD::VLSHR: return fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR8(VT, RetVT, Op0, Op0IsKill, imm1); 8554 default: return 0; 8555 } 8556} 8557 8558// FastEmit functions for AArch64ISD::SRSHR_I. 8559 8560unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v4i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8561 if (RetVT.SimpleTy != MVT::v4i16) 8562 return 0; 8563 if ((Subtarget->hasNEON())) { 8564 return fastEmitInst_ri(AArch64::SRSHRv4i16_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8565 } 8566 return 0; 8567} 8568 8569unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v8i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8570 if (RetVT.SimpleTy != MVT::v8i16) 8571 return 0; 8572 if ((Subtarget->hasNEON())) { 8573 return fastEmitInst_ri(AArch64::SRSHRv8i16_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8574 } 8575 return 0; 8576} 8577 8578unsigned fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8579 switch (VT.SimpleTy) { 8580 case MVT::v4i16: return fastEmit_AArch64ISD_SRSHR_I_MVT_v4i16_ri_Predicate_vecshiftR16(RetVT, Op0, Op0IsKill, imm1); 8581 case MVT::v8i16: return fastEmit_AArch64ISD_SRSHR_I_MVT_v8i16_ri_Predicate_vecshiftR16(RetVT, Op0, Op0IsKill, imm1); 8582 default: return 0; 8583 } 8584} 8585 8586// FastEmit functions for AArch64ISD::URSHR_I. 8587 8588unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v4i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8589 if (RetVT.SimpleTy != MVT::v4i16) 8590 return 0; 8591 if ((Subtarget->hasNEON())) { 8592 return fastEmitInst_ri(AArch64::URSHRv4i16_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8593 } 8594 return 0; 8595} 8596 8597unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v8i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8598 if (RetVT.SimpleTy != MVT::v8i16) 8599 return 0; 8600 if ((Subtarget->hasNEON())) { 8601 return fastEmitInst_ri(AArch64::URSHRv8i16_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8602 } 8603 return 0; 8604} 8605 8606unsigned fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8607 switch (VT.SimpleTy) { 8608 case MVT::v4i16: return fastEmit_AArch64ISD_URSHR_I_MVT_v4i16_ri_Predicate_vecshiftR16(RetVT, Op0, Op0IsKill, imm1); 8609 case MVT::v8i16: return fastEmit_AArch64ISD_URSHR_I_MVT_v8i16_ri_Predicate_vecshiftR16(RetVT, Op0, Op0IsKill, imm1); 8610 default: return 0; 8611 } 8612} 8613 8614// FastEmit functions for AArch64ISD::VASHR. 8615 8616unsigned fastEmit_AArch64ISD_VASHR_MVT_v4i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8617 if (RetVT.SimpleTy != MVT::v4i16) 8618 return 0; 8619 if ((Subtarget->hasNEON())) { 8620 return fastEmitInst_ri(AArch64::SSHRv4i16_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8621 } 8622 return 0; 8623} 8624 8625unsigned fastEmit_AArch64ISD_VASHR_MVT_v8i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8626 if (RetVT.SimpleTy != MVT::v8i16) 8627 return 0; 8628 if ((Subtarget->hasNEON())) { 8629 return fastEmitInst_ri(AArch64::SSHRv8i16_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8630 } 8631 return 0; 8632} 8633 8634unsigned fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8635 switch (VT.SimpleTy) { 8636 case MVT::v4i16: return fastEmit_AArch64ISD_VASHR_MVT_v4i16_ri_Predicate_vecshiftR16(RetVT, Op0, Op0IsKill, imm1); 8637 case MVT::v8i16: return fastEmit_AArch64ISD_VASHR_MVT_v8i16_ri_Predicate_vecshiftR16(RetVT, Op0, Op0IsKill, imm1); 8638 default: return 0; 8639 } 8640} 8641 8642// FastEmit functions for AArch64ISD::VLSHR. 8643 8644unsigned fastEmit_AArch64ISD_VLSHR_MVT_v4i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8645 if (RetVT.SimpleTy != MVT::v4i16) 8646 return 0; 8647 if ((Subtarget->hasNEON())) { 8648 return fastEmitInst_ri(AArch64::USHRv4i16_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8649 } 8650 return 0; 8651} 8652 8653unsigned fastEmit_AArch64ISD_VLSHR_MVT_v8i16_ri_Predicate_vecshiftR16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8654 if (RetVT.SimpleTy != MVT::v8i16) 8655 return 0; 8656 if ((Subtarget->hasNEON())) { 8657 return fastEmitInst_ri(AArch64::USHRv8i16_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8658 } 8659 return 0; 8660} 8661 8662unsigned fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8663 switch (VT.SimpleTy) { 8664 case MVT::v4i16: return fastEmit_AArch64ISD_VLSHR_MVT_v4i16_ri_Predicate_vecshiftR16(RetVT, Op0, Op0IsKill, imm1); 8665 case MVT::v8i16: return fastEmit_AArch64ISD_VLSHR_MVT_v8i16_ri_Predicate_vecshiftR16(RetVT, Op0, Op0IsKill, imm1); 8666 default: return 0; 8667 } 8668} 8669 8670// Top-level FastEmit function. 8671 8672unsigned fastEmit_ri_Predicate_vecshiftR16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8673 switch (Opcode) { 8674 case AArch64ISD::SRSHR_I: return fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR16(VT, RetVT, Op0, Op0IsKill, imm1); 8675 case AArch64ISD::URSHR_I: return fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR16(VT, RetVT, Op0, Op0IsKill, imm1); 8676 case AArch64ISD::VASHR: return fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR16(VT, RetVT, Op0, Op0IsKill, imm1); 8677 case AArch64ISD::VLSHR: return fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR16(VT, RetVT, Op0, Op0IsKill, imm1); 8678 default: return 0; 8679 } 8680} 8681 8682// FastEmit functions for AArch64ISD::SRSHR_I. 8683 8684unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v2i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8685 if (RetVT.SimpleTy != MVT::v2i32) 8686 return 0; 8687 if ((Subtarget->hasNEON())) { 8688 return fastEmitInst_ri(AArch64::SRSHRv2i32_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8689 } 8690 return 0; 8691} 8692 8693unsigned fastEmit_AArch64ISD_SRSHR_I_MVT_v4i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8694 if (RetVT.SimpleTy != MVT::v4i32) 8695 return 0; 8696 if ((Subtarget->hasNEON())) { 8697 return fastEmitInst_ri(AArch64::SRSHRv4i32_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8698 } 8699 return 0; 8700} 8701 8702unsigned fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8703 switch (VT.SimpleTy) { 8704 case MVT::v2i32: return fastEmit_AArch64ISD_SRSHR_I_MVT_v2i32_ri_Predicate_vecshiftR32(RetVT, Op0, Op0IsKill, imm1); 8705 case MVT::v4i32: return fastEmit_AArch64ISD_SRSHR_I_MVT_v4i32_ri_Predicate_vecshiftR32(RetVT, Op0, Op0IsKill, imm1); 8706 default: return 0; 8707 } 8708} 8709 8710// FastEmit functions for AArch64ISD::URSHR_I. 8711 8712unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v2i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8713 if (RetVT.SimpleTy != MVT::v2i32) 8714 return 0; 8715 if ((Subtarget->hasNEON())) { 8716 return fastEmitInst_ri(AArch64::URSHRv2i32_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8717 } 8718 return 0; 8719} 8720 8721unsigned fastEmit_AArch64ISD_URSHR_I_MVT_v4i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8722 if (RetVT.SimpleTy != MVT::v4i32) 8723 return 0; 8724 if ((Subtarget->hasNEON())) { 8725 return fastEmitInst_ri(AArch64::URSHRv4i32_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8726 } 8727 return 0; 8728} 8729 8730unsigned fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8731 switch (VT.SimpleTy) { 8732 case MVT::v2i32: return fastEmit_AArch64ISD_URSHR_I_MVT_v2i32_ri_Predicate_vecshiftR32(RetVT, Op0, Op0IsKill, imm1); 8733 case MVT::v4i32: return fastEmit_AArch64ISD_URSHR_I_MVT_v4i32_ri_Predicate_vecshiftR32(RetVT, Op0, Op0IsKill, imm1); 8734 default: return 0; 8735 } 8736} 8737 8738// FastEmit functions for AArch64ISD::VASHR. 8739 8740unsigned fastEmit_AArch64ISD_VASHR_MVT_v2i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8741 if (RetVT.SimpleTy != MVT::v2i32) 8742 return 0; 8743 if ((Subtarget->hasNEON())) { 8744 return fastEmitInst_ri(AArch64::SSHRv2i32_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8745 } 8746 return 0; 8747} 8748 8749unsigned fastEmit_AArch64ISD_VASHR_MVT_v4i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8750 if (RetVT.SimpleTy != MVT::v4i32) 8751 return 0; 8752 if ((Subtarget->hasNEON())) { 8753 return fastEmitInst_ri(AArch64::SSHRv4i32_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8754 } 8755 return 0; 8756} 8757 8758unsigned fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8759 switch (VT.SimpleTy) { 8760 case MVT::v2i32: return fastEmit_AArch64ISD_VASHR_MVT_v2i32_ri_Predicate_vecshiftR32(RetVT, Op0, Op0IsKill, imm1); 8761 case MVT::v4i32: return fastEmit_AArch64ISD_VASHR_MVT_v4i32_ri_Predicate_vecshiftR32(RetVT, Op0, Op0IsKill, imm1); 8762 default: return 0; 8763 } 8764} 8765 8766// FastEmit functions for AArch64ISD::VLSHR. 8767 8768unsigned fastEmit_AArch64ISD_VLSHR_MVT_v2i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8769 if (RetVT.SimpleTy != MVT::v2i32) 8770 return 0; 8771 if ((Subtarget->hasNEON())) { 8772 return fastEmitInst_ri(AArch64::USHRv2i32_shift, &AArch64::FPR64RegClass, Op0, Op0IsKill, imm1); 8773 } 8774 return 0; 8775} 8776 8777unsigned fastEmit_AArch64ISD_VLSHR_MVT_v4i32_ri_Predicate_vecshiftR32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8778 if (RetVT.SimpleTy != MVT::v4i32) 8779 return 0; 8780 if ((Subtarget->hasNEON())) { 8781 return fastEmitInst_ri(AArch64::USHRv4i32_shift, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1); 8782 } 8783 return 0; 8784} 8785 8786unsigned fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8787 switch (VT.SimpleTy) { 8788 case MVT::v2i32: return fastEmit_AArch64ISD_VLSHR_MVT_v2i32_ri_Predicate_vecshiftR32(RetVT, Op0, Op0IsKill, imm1); 8789 case MVT::v4i32: return fastEmit_AArch64ISD_VLSHR_MVT_v4i32_ri_Predicate_vecshiftR32(RetVT, Op0, Op0IsKill, imm1); 8790 default: return 0; 8791 } 8792} 8793 8794// Top-level FastEmit function. 8795 8796unsigned fastEmit_ri_Predicate_vecshiftR32(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 8797 switch (Opcode) { 8798 case AArch64ISD::SRSHR_I: return fastEmit_AArch64ISD_SRSHR_I_ri_Predicate_vecshiftR32(VT, RetVT, Op0, Op0IsKill, imm1); 8799 case AArch64ISD::URSHR_I: return fastEmit_AArch64ISD_URSHR_I_ri_Predicate_vecshiftR32(VT, RetVT, Op0, Op0IsKill, imm1); 8800 case AArch64ISD::VASHR: return fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR32(VT, RetVT, Op0, Op0IsKill, imm1); 8801 case AArch64ISD::VLSHR: return fastEmit_AArch64ISD_VLSHR_ri_Predicate_vecshiftR32(VT, RetVT, Op0, Op0IsKill, imm1); 8802 default: return 0; 8803 } 8804} 8805 8806// FastEmit functions for ISD::Constant. 8807 8808unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) { 8809 if (RetVT.SimpleTy != MVT::i32) 8810 return 0; 8811 return fastEmitInst_i(AArch64::MOVi32imm, &AArch64::GPR32RegClass, imm0); 8812} 8813 8814unsigned fastEmit_ISD_Constant_MVT_i64_i(MVT RetVT, uint64_t imm0) { 8815 if (RetVT.SimpleTy != MVT::i64) 8816 return 0; 8817 return fastEmitInst_i(AArch64::MOVi64imm, &AArch64::GPR64RegClass, imm0); 8818} 8819 8820unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) { 8821 switch (VT.SimpleTy) { 8822 case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0); 8823 case MVT::i64: return fastEmit_ISD_Constant_MVT_i64_i(RetVT, imm0); 8824 default: return 0; 8825 } 8826} 8827 8828// Top-level FastEmit function. 8829 8830unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override { 8831 if (VT == MVT::i32 && Predicate_imm0_255(imm0)) 8832 if (unsigned Reg = fastEmit_i_Predicate_imm0_255(VT, RetVT, Opcode, imm0)) 8833 return Reg; 8834 8835 switch (Opcode) { 8836 case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0); 8837 default: return 0; 8838 } 8839} 8840 8841// FastEmit functions for AArch64ISD::FMOV. 8842 8843unsigned fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v4f16_i_Predicate_imm0_255(uint64_t imm0) { 8844 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 8845 return fastEmitInst_i(AArch64::FMOVv4f16_ns, &AArch64::FPR64RegClass, imm0); 8846 } 8847 return 0; 8848} 8849 8850unsigned fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v8f16_i_Predicate_imm0_255(uint64_t imm0) { 8851 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 8852 return fastEmitInst_i(AArch64::FMOVv8f16_ns, &AArch64::FPR128RegClass, imm0); 8853 } 8854 return 0; 8855} 8856 8857unsigned fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v2f32_i_Predicate_imm0_255(uint64_t imm0) { 8858 if ((Subtarget->hasNEON())) { 8859 return fastEmitInst_i(AArch64::FMOVv2f32_ns, &AArch64::FPR64RegClass, imm0); 8860 } 8861 return 0; 8862} 8863 8864unsigned fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v4f32_i_Predicate_imm0_255(uint64_t imm0) { 8865 if ((Subtarget->hasNEON())) { 8866 return fastEmitInst_i(AArch64::FMOVv4f32_ns, &AArch64::FPR128RegClass, imm0); 8867 } 8868 return 0; 8869} 8870 8871unsigned fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v2f64_i_Predicate_imm0_255(uint64_t imm0) { 8872 if ((Subtarget->hasNEON())) { 8873 return fastEmitInst_i(AArch64::FMOVv2f64_ns, &AArch64::FPR128RegClass, imm0); 8874 } 8875 return 0; 8876} 8877 8878unsigned fastEmit_AArch64ISD_FMOV_MVT_i32_i_Predicate_imm0_255(MVT RetVT, uint64_t imm0) { 8879switch (RetVT.SimpleTy) { 8880 case MVT::v4f16: return fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v4f16_i_Predicate_imm0_255(imm0); 8881 case MVT::v8f16: return fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v8f16_i_Predicate_imm0_255(imm0); 8882 case MVT::v2f32: return fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v2f32_i_Predicate_imm0_255(imm0); 8883 case MVT::v4f32: return fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v4f32_i_Predicate_imm0_255(imm0); 8884 case MVT::v2f64: return fastEmit_AArch64ISD_FMOV_MVT_i32_MVT_v2f64_i_Predicate_imm0_255(imm0); 8885 default: return 0; 8886} 8887} 8888 8889unsigned fastEmit_AArch64ISD_FMOV_i_Predicate_imm0_255(MVT VT, MVT RetVT, uint64_t imm0) { 8890 switch (VT.SimpleTy) { 8891 case MVT::i32: return fastEmit_AArch64ISD_FMOV_MVT_i32_i_Predicate_imm0_255(RetVT, imm0); 8892 default: return 0; 8893 } 8894} 8895 8896// FastEmit functions for AArch64ISD::MOVI. 8897 8898unsigned fastEmit_AArch64ISD_MOVI_MVT_i32_MVT_v8i8_i_Predicate_imm0_255(uint64_t imm0) { 8899 if ((Subtarget->hasNEON())) { 8900 return fastEmitInst_i(AArch64::MOVIv8b_ns, &AArch64::FPR64RegClass, imm0); 8901 } 8902 return 0; 8903} 8904 8905unsigned fastEmit_AArch64ISD_MOVI_MVT_i32_MVT_v16i8_i_Predicate_imm0_255(uint64_t imm0) { 8906 if ((Subtarget->hasNEON())) { 8907 return fastEmitInst_i(AArch64::MOVIv16b_ns, &AArch64::FPR128RegClass, imm0); 8908 } 8909 return 0; 8910} 8911 8912unsigned fastEmit_AArch64ISD_MOVI_MVT_i32_i_Predicate_imm0_255(MVT RetVT, uint64_t imm0) { 8913switch (RetVT.SimpleTy) { 8914 case MVT::v8i8: return fastEmit_AArch64ISD_MOVI_MVT_i32_MVT_v8i8_i_Predicate_imm0_255(imm0); 8915 case MVT::v16i8: return fastEmit_AArch64ISD_MOVI_MVT_i32_MVT_v16i8_i_Predicate_imm0_255(imm0); 8916 default: return 0; 8917} 8918} 8919 8920unsigned fastEmit_AArch64ISD_MOVI_i_Predicate_imm0_255(MVT VT, MVT RetVT, uint64_t imm0) { 8921 switch (VT.SimpleTy) { 8922 case MVT::i32: return fastEmit_AArch64ISD_MOVI_MVT_i32_i_Predicate_imm0_255(RetVT, imm0); 8923 default: return 0; 8924 } 8925} 8926 8927// FastEmit functions for AArch64ISD::MOVIedit. 8928 8929unsigned fastEmit_AArch64ISD_MOVIedit_MVT_i32_MVT_f64_i_Predicate_imm0_255(uint64_t imm0) { 8930 return fastEmitInst_i(AArch64::MOVID, &AArch64::FPR64RegClass, imm0); 8931} 8932 8933unsigned fastEmit_AArch64ISD_MOVIedit_MVT_i32_MVT_v2i64_i_Predicate_imm0_255(uint64_t imm0) { 8934 if ((Subtarget->hasNEON())) { 8935 return fastEmitInst_i(AArch64::MOVIv2d_ns, &AArch64::FPR128RegClass, imm0); 8936 } 8937 return 0; 8938} 8939 8940unsigned fastEmit_AArch64ISD_MOVIedit_MVT_i32_i_Predicate_imm0_255(MVT RetVT, uint64_t imm0) { 8941switch (RetVT.SimpleTy) { 8942 case MVT::f64: return fastEmit_AArch64ISD_MOVIedit_MVT_i32_MVT_f64_i_Predicate_imm0_255(imm0); 8943 case MVT::v2i64: return fastEmit_AArch64ISD_MOVIedit_MVT_i32_MVT_v2i64_i_Predicate_imm0_255(imm0); 8944 default: return 0; 8945} 8946} 8947 8948unsigned fastEmit_AArch64ISD_MOVIedit_i_Predicate_imm0_255(MVT VT, MVT RetVT, uint64_t imm0) { 8949 switch (VT.SimpleTy) { 8950 case MVT::i32: return fastEmit_AArch64ISD_MOVIedit_MVT_i32_i_Predicate_imm0_255(RetVT, imm0); 8951 default: return 0; 8952 } 8953} 8954 8955// Top-level FastEmit function. 8956 8957unsigned fastEmit_i_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) { 8958 switch (Opcode) { 8959 case AArch64ISD::FMOV: return fastEmit_AArch64ISD_FMOV_i_Predicate_imm0_255(VT, RetVT, imm0); 8960 case AArch64ISD::MOVI: return fastEmit_AArch64ISD_MOVI_i_Predicate_imm0_255(VT, RetVT, imm0); 8961 case AArch64ISD::MOVIedit: return fastEmit_AArch64ISD_MOVIedit_i_Predicate_imm0_255(VT, RetVT, imm0); 8962 default: return 0; 8963 } 8964} 8965 8966