1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Global Instruction Selector for the AArch64 target *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9#ifdef GET_GLOBALISEL_PREDICATE_BITSET 10const unsigned MAX_SUBTARGET_PREDICATES = 16; 11using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>; 12#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET 13 14#ifdef GET_GLOBALISEL_TEMPORARIES_DECL 15 mutable MatcherState State; 16 typedef ComplexRendererFns(AArch64InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; 17 typedef void(AArch64InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const; 18 const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo; 19 static AArch64InstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; 20 static AArch64InstructionSelector::CustomRendererFn CustomRenderers[]; 21 bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; 22 bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; 23 bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; 24 const int64_t *getMatchTable() const override; 25 bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override; 26#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL 27 28#ifdef GET_GLOBALISEL_TEMPORARIES_INIT 29, State(1), 30ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) 31#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT 32 33#ifdef GET_GLOBALISEL_IMPL 34// Bits for subtarget features that participate in instruction matching. 35enum SubtargetFeatureBits : uint8_t { 36 Feature_HasFPARMv8Bit = 3, 37 Feature_HasNEONBit = 4, 38 Feature_HasSHA2Bit = 7, 39 Feature_HasAESBit = 6, 40 Feature_HasDotProdBit = 0, 41 Feature_HasCRCBit = 1, 42 Feature_HasLSEBit = 8, 43 Feature_HasRDMBit = 5, 44 Feature_HasPerfMonBit = 9, 45 Feature_HasFullFP16Bit = 2, 46 Feature_HasFuseAESBit = 14, 47 Feature_IsLEBit = 10, 48 Feature_IsBEBit = 15, 49 Feature_UseAlternateSExtLoadCVTF32Bit = 13, 50 Feature_NotForCodeSizeBit = 12, 51 Feature_UseSTRQroBit = 11, 52}; 53 54PredicateBitset AArch64InstructionSelector:: 55computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const { 56 PredicateBitset Features; 57 if (Subtarget->hasFPARMv8()) 58 Features[Feature_HasFPARMv8Bit] = 1; 59 if (Subtarget->hasNEON()) 60 Features[Feature_HasNEONBit] = 1; 61 if (Subtarget->hasSHA2()) 62 Features[Feature_HasSHA2Bit] = 1; 63 if (Subtarget->hasAES()) 64 Features[Feature_HasAESBit] = 1; 65 if (Subtarget->hasDotProd()) 66 Features[Feature_HasDotProdBit] = 1; 67 if (Subtarget->hasCRC()) 68 Features[Feature_HasCRCBit] = 1; 69 if (Subtarget->hasLSE()) 70 Features[Feature_HasLSEBit] = 1; 71 if (Subtarget->hasRDM()) 72 Features[Feature_HasRDMBit] = 1; 73 if (Subtarget->hasPerfMon()) 74 Features[Feature_HasPerfMonBit] = 1; 75 if (Subtarget->hasFullFP16()) 76 Features[Feature_HasFullFP16Bit] = 1; 77 if (Subtarget->hasFuseAES()) 78 Features[Feature_HasFuseAESBit] = 1; 79 if (Subtarget->isLittleEndian()) 80 Features[Feature_IsLEBit] = 1; 81 if (!Subtarget->isLittleEndian()) 82 Features[Feature_IsBEBit] = 1; 83 if (Subtarget->useAlternateSExtLoadCVTF32Pattern()) 84 Features[Feature_UseAlternateSExtLoadCVTF32Bit] = 1; 85 return Features; 86} 87 88PredicateBitset AArch64InstructionSelector:: 89computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget, const MachineFunction *MF) const { 90 PredicateBitset Features; 91 if (!MF->getFunction().optForSize()) 92 Features[Feature_NotForCodeSizeBit] = 1; 93 if (!Subtarget->isSTRQroSlow() || MF->getFunction().optForSize()) 94 Features[Feature_UseSTRQroBit] = 1; 95 return Features; 96} 97 98// LLT Objects. 99enum { 100 GILLT_s16, 101 GILLT_s32, 102 GILLT_s64, 103 GILLT_s128, 104 GILLT_v2s32, 105 GILLT_v2s64, 106 GILLT_v4s16, 107 GILLT_v4s32, 108 GILLT_v8s8, 109 GILLT_v8s16, 110 GILLT_v16s8, 111}; 112const static size_t NumTypeObjects = 11; 113const static LLT TypeObjects[] = { 114 LLT::scalar(16), 115 LLT::scalar(32), 116 LLT::scalar(64), 117 LLT::scalar(128), 118 LLT::vector(2, 32), 119 LLT::vector(2, 64), 120 LLT::vector(4, 16), 121 LLT::vector(4, 32), 122 LLT::vector(8, 8), 123 LLT::vector(8, 16), 124 LLT::vector(16, 8), 125}; 126 127// Feature bitsets. 128enum { 129 GIFBS_Invalid, 130 GIFBS_HasAES, 131 GIFBS_HasCRC, 132 GIFBS_HasDotProd, 133 GIFBS_HasFPARMv8, 134 GIFBS_HasFullFP16, 135 GIFBS_HasFuseAES, 136 GIFBS_HasLSE, 137 GIFBS_HasNEON, 138 GIFBS_HasRDM, 139 GIFBS_HasSHA2, 140 GIFBS_IsBE, 141 GIFBS_IsLE, 142 GIFBS_HasFullFP16_HasNEON, 143 GIFBS_HasNEON_HasRDM, 144}; 145const static PredicateBitset FeatureBitsets[] { 146 {}, // GIFBS_Invalid 147 {Feature_HasAESBit, }, 148 {Feature_HasCRCBit, }, 149 {Feature_HasDotProdBit, }, 150 {Feature_HasFPARMv8Bit, }, 151 {Feature_HasFullFP16Bit, }, 152 {Feature_HasFuseAESBit, }, 153 {Feature_HasLSEBit, }, 154 {Feature_HasNEONBit, }, 155 {Feature_HasRDMBit, }, 156 {Feature_HasSHA2Bit, }, 157 {Feature_IsBEBit, }, 158 {Feature_IsLEBit, }, 159 {Feature_HasFullFP16Bit, Feature_HasNEONBit, }, 160 {Feature_HasNEONBit, Feature_HasRDMBit, }, 161}; 162 163// ComplexPattern predicates. 164enum { 165 GICP_Invalid, 166 GICP_gi_addsub_shifted_imm32, 167 GICP_gi_addsub_shifted_imm64, 168 GICP_gi_am_indexed128, 169 GICP_gi_am_indexed16, 170 GICP_gi_am_indexed32, 171 GICP_gi_am_indexed64, 172 GICP_gi_am_indexed8, 173 GICP_gi_am_unscaled128, 174 GICP_gi_am_unscaled16, 175 GICP_gi_am_unscaled32, 176 GICP_gi_am_unscaled64, 177 GICP_gi_am_unscaled8, 178}; 179// See constructor for table contents 180 181// PatFrag predicates. 182enum { 183 GIPFP_I64_Predicate_VectorIndex1 = GIPFP_I64_Invalid + 1, 184 GIPFP_I64_Predicate_VectorIndexB, 185 GIPFP_I64_Predicate_VectorIndexD, 186 GIPFP_I64_Predicate_VectorIndexH, 187 GIPFP_I64_Predicate_VectorIndexS, 188 GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i16, 189 GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i32, 190 GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i64, 191 GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i8, 192 GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i16, 193 GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i32, 194 GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i64, 195 GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i8, 196 GIPFP_I64_Predicate_i64imm_32bit, 197 GIPFP_I64_Predicate_imm0_1, 198 GIPFP_I64_Predicate_imm0_127, 199 GIPFP_I64_Predicate_imm0_15, 200 GIPFP_I64_Predicate_imm0_255, 201 GIPFP_I64_Predicate_imm0_31, 202 GIPFP_I64_Predicate_imm0_63, 203 GIPFP_I64_Predicate_imm0_65535, 204 GIPFP_I64_Predicate_imm0_7, 205 GIPFP_I64_Predicate_imm32_0_15, 206 GIPFP_I64_Predicate_imm32_0_31, 207 GIPFP_I64_Predicate_maski16_or_more, 208 GIPFP_I64_Predicate_maski8_or_more, 209 GIPFP_I64_Predicate_s64imm_32bit, 210 GIPFP_I64_Predicate_simm4s1, 211 GIPFP_I64_Predicate_simm4s16, 212 GIPFP_I64_Predicate_simm4s2, 213 GIPFP_I64_Predicate_simm4s3, 214 GIPFP_I64_Predicate_simm4s4, 215 GIPFP_I64_Predicate_simm5_32b, 216 GIPFP_I64_Predicate_simm5_64b, 217 GIPFP_I64_Predicate_simm6_32b, 218 GIPFP_I64_Predicate_simm6s1, 219 GIPFP_I64_Predicate_simm8, 220 GIPFP_I64_Predicate_simm9, 221 GIPFP_I64_Predicate_sve_elm_idx_extdup_b, 222 GIPFP_I64_Predicate_sve_elm_idx_extdup_d, 223 GIPFP_I64_Predicate_sve_elm_idx_extdup_h, 224 GIPFP_I64_Predicate_sve_elm_idx_extdup_q, 225 GIPFP_I64_Predicate_sve_elm_idx_extdup_s, 226 GIPFP_I64_Predicate_sve_incdec_imm, 227 GIPFP_I64_Predicate_sve_pred_enum, 228 GIPFP_I64_Predicate_sve_prfop, 229 GIPFP_I64_Predicate_tbz_imm0_31_diag, 230 GIPFP_I64_Predicate_tbz_imm0_31_nodiag, 231 GIPFP_I64_Predicate_tbz_imm32_63, 232 GIPFP_I64_Predicate_uimm5s2, 233 GIPFP_I64_Predicate_uimm5s4, 234 GIPFP_I64_Predicate_uimm5s8, 235 GIPFP_I64_Predicate_uimm6, 236 GIPFP_I64_Predicate_uimm6s1, 237 GIPFP_I64_Predicate_uimm6s2, 238 GIPFP_I64_Predicate_uimm6s4, 239 GIPFP_I64_Predicate_uimm6s8, 240 GIPFP_I64_Predicate_vecshiftL16, 241 GIPFP_I64_Predicate_vecshiftL32, 242 GIPFP_I64_Predicate_vecshiftL64, 243 GIPFP_I64_Predicate_vecshiftL8, 244 GIPFP_I64_Predicate_vecshiftR16, 245 GIPFP_I64_Predicate_vecshiftR16Narrow, 246 GIPFP_I64_Predicate_vecshiftR32, 247 GIPFP_I64_Predicate_vecshiftR32Narrow, 248 GIPFP_I64_Predicate_vecshiftR64, 249 GIPFP_I64_Predicate_vecshiftR64Narrow, 250 GIPFP_I64_Predicate_vecshiftR8, 251}; 252bool AArch64InstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { 253 switch (PredicateID) { 254 case GIPFP_I64_Predicate_VectorIndex1: { 255 return ((uint64_t)Imm) == 1; 256 llvm_unreachable("ImmediateCode should have returned"); 257 return false; 258 } 259 case GIPFP_I64_Predicate_VectorIndexB: { 260 return ((uint64_t)Imm) < 16; 261 llvm_unreachable("ImmediateCode should have returned"); 262 return false; 263 } 264 case GIPFP_I64_Predicate_VectorIndexD: { 265 return ((uint64_t)Imm) < 2; 266 llvm_unreachable("ImmediateCode should have returned"); 267 return false; 268 } 269 case GIPFP_I64_Predicate_VectorIndexH: { 270 return ((uint64_t)Imm) < 8; 271 llvm_unreachable("ImmediateCode should have returned"); 272 return false; 273 } 274 case GIPFP_I64_Predicate_VectorIndexS: { 275 return ((uint64_t)Imm) < 4; 276 llvm_unreachable("ImmediateCode should have returned"); 277 return false; 278 } 279 case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i16: { 280 281 return AArch64_AM::isSVEAddSubImm<int16_t>(Imm); 282 283 llvm_unreachable("ImmediateCode should have returned"); 284 return false; 285 } 286 case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i32: { 287 288 return AArch64_AM::isSVEAddSubImm<int32_t>(Imm); 289 290 llvm_unreachable("ImmediateCode should have returned"); 291 return false; 292 } 293 case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i64: { 294 295 return AArch64_AM::isSVEAddSubImm<int64_t>(Imm); 296 297 llvm_unreachable("ImmediateCode should have returned"); 298 return false; 299 } 300 case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i8: { 301 302 return AArch64_AM::isSVEAddSubImm<int8_t>(Imm); 303 304 llvm_unreachable("ImmediateCode should have returned"); 305 return false; 306 } 307 case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i16: { 308 309 return AArch64_AM::isSVECpyImm<int16_t>(Imm); 310 311 llvm_unreachable("ImmediateCode should have returned"); 312 return false; 313 } 314 case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i32: { 315 316 return AArch64_AM::isSVECpyImm<int32_t>(Imm); 317 318 llvm_unreachable("ImmediateCode should have returned"); 319 return false; 320 } 321 case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i64: { 322 323 return AArch64_AM::isSVECpyImm<int64_t>(Imm); 324 325 llvm_unreachable("ImmediateCode should have returned"); 326 return false; 327 } 328 case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i8: { 329 330 return AArch64_AM::isSVECpyImm<int8_t>(Imm); 331 332 llvm_unreachable("ImmediateCode should have returned"); 333 return false; 334 } 335 case GIPFP_I64_Predicate_i64imm_32bit: { 336 337 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm); 338 339 llvm_unreachable("ImmediateCode should have returned"); 340 return false; 341 } 342 case GIPFP_I64_Predicate_imm0_1: { 343 344 return ((uint64_t)Imm) < 2; 345 346 llvm_unreachable("ImmediateCode should have returned"); 347 return false; 348 } 349 case GIPFP_I64_Predicate_imm0_127: { 350 351 return ((uint32_t)Imm) < 128; 352 353 llvm_unreachable("ImmediateCode should have returned"); 354 return false; 355 } 356 case GIPFP_I64_Predicate_imm0_15: { 357 358 return ((uint64_t)Imm) < 16; 359 360 llvm_unreachable("ImmediateCode should have returned"); 361 return false; 362 } 363 case GIPFP_I64_Predicate_imm0_255: { 364 365 return ((uint32_t)Imm) < 256; 366 367 llvm_unreachable("ImmediateCode should have returned"); 368 return false; 369 } 370 case GIPFP_I64_Predicate_imm0_31: { 371 372 return ((uint64_t)Imm) < 32; 373 374 llvm_unreachable("ImmediateCode should have returned"); 375 return false; 376 } 377 case GIPFP_I64_Predicate_imm0_63: { 378 379 return ((uint64_t)Imm) < 64; 380 381 llvm_unreachable("ImmediateCode should have returned"); 382 return false; 383 } 384 case GIPFP_I64_Predicate_imm0_65535: { 385 386 return ((uint32_t)Imm) < 65536; 387 388 llvm_unreachable("ImmediateCode should have returned"); 389 return false; 390 } 391 case GIPFP_I64_Predicate_imm0_7: { 392 393 return ((uint64_t)Imm) < 8; 394 395 llvm_unreachable("ImmediateCode should have returned"); 396 return false; 397 } 398 case GIPFP_I64_Predicate_imm32_0_15: { 399 400 return ((uint32_t)Imm) < 16; 401 402 llvm_unreachable("ImmediateCode should have returned"); 403 return false; 404 } 405 case GIPFP_I64_Predicate_imm32_0_31: { 406 407 return ((uint64_t)Imm) < 32; 408 409 llvm_unreachable("ImmediateCode should have returned"); 410 return false; 411 } 412 case GIPFP_I64_Predicate_maski16_or_more: { 413 return (Imm & 0xffff) == 0xffff; 414 llvm_unreachable("ImmediateCode should have returned"); 415 return false; 416 } 417 case GIPFP_I64_Predicate_maski8_or_more: { 418 return (Imm & 0xff) == 0xff; 419 llvm_unreachable("ImmediateCode should have returned"); 420 return false; 421 } 422 case GIPFP_I64_Predicate_s64imm_32bit: { 423 424 int64_t Imm64 = static_cast<int64_t>(Imm); 425 return Imm64 >= std::numeric_limits<int32_t>::min() && 426 Imm64 <= std::numeric_limits<int32_t>::max(); 427 428 llvm_unreachable("ImmediateCode should have returned"); 429 return false; 430 } 431 case GIPFP_I64_Predicate_simm4s1: { 432 return Imm >=-8 && Imm <= 7; 433 llvm_unreachable("ImmediateCode should have returned"); 434 return false; 435 } 436 case GIPFP_I64_Predicate_simm4s16: { 437 return Imm >=-128 && Imm <= 112 && (Imm % 16) == 0x0; 438 llvm_unreachable("ImmediateCode should have returned"); 439 return false; 440 } 441 case GIPFP_I64_Predicate_simm4s2: { 442 return Imm >=-16 && Imm <= 14 && (Imm % 2) == 0x0; 443 llvm_unreachable("ImmediateCode should have returned"); 444 return false; 445 } 446 case GIPFP_I64_Predicate_simm4s3: { 447 return Imm >=-24 && Imm <= 21 && (Imm % 3) == 0x0; 448 llvm_unreachable("ImmediateCode should have returned"); 449 return false; 450 } 451 case GIPFP_I64_Predicate_simm4s4: { 452 return Imm >=-32 && Imm <= 28 && (Imm % 4) == 0x0; 453 llvm_unreachable("ImmediateCode should have returned"); 454 return false; 455 } 456 case GIPFP_I64_Predicate_simm5_32b: { 457 return Imm >= -16 && Imm < 16; 458 llvm_unreachable("ImmediateCode should have returned"); 459 return false; 460 } 461 case GIPFP_I64_Predicate_simm5_64b: { 462 return Imm >= -16 && Imm < 16; 463 llvm_unreachable("ImmediateCode should have returned"); 464 return false; 465 } 466 case GIPFP_I64_Predicate_simm6_32b: { 467 return Imm >= -32 && Imm < 32; 468 llvm_unreachable("ImmediateCode should have returned"); 469 return false; 470 } 471 case GIPFP_I64_Predicate_simm6s1: { 472 return Imm >= -32 && Imm < 32; 473 llvm_unreachable("ImmediateCode should have returned"); 474 return false; 475 } 476 case GIPFP_I64_Predicate_simm8: { 477 return Imm >= -128 && Imm < 127; 478 llvm_unreachable("ImmediateCode should have returned"); 479 return false; 480 } 481 case GIPFP_I64_Predicate_simm9: { 482 return Imm >= -256 && Imm < 256; 483 llvm_unreachable("ImmediateCode should have returned"); 484 return false; 485 } 486 case GIPFP_I64_Predicate_sve_elm_idx_extdup_b: { 487 return ((uint64_t)Imm) < 64; 488 llvm_unreachable("ImmediateCode should have returned"); 489 return false; 490 } 491 case GIPFP_I64_Predicate_sve_elm_idx_extdup_d: { 492 return ((uint64_t)Imm) < 8; 493 llvm_unreachable("ImmediateCode should have returned"); 494 return false; 495 } 496 case GIPFP_I64_Predicate_sve_elm_idx_extdup_h: { 497 return ((uint64_t)Imm) < 32; 498 llvm_unreachable("ImmediateCode should have returned"); 499 return false; 500 } 501 case GIPFP_I64_Predicate_sve_elm_idx_extdup_q: { 502 return ((uint64_t)Imm) < 4; 503 llvm_unreachable("ImmediateCode should have returned"); 504 return false; 505 } 506 case GIPFP_I64_Predicate_sve_elm_idx_extdup_s: { 507 return ((uint64_t)Imm) < 16; 508 llvm_unreachable("ImmediateCode should have returned"); 509 return false; 510 } 511 case GIPFP_I64_Predicate_sve_incdec_imm: { 512 513 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); 514 515 llvm_unreachable("ImmediateCode should have returned"); 516 return false; 517 } 518 case GIPFP_I64_Predicate_sve_pred_enum: { 519 520 return (((uint32_t)Imm) < 32); 521 522 llvm_unreachable("ImmediateCode should have returned"); 523 return false; 524 } 525 case GIPFP_I64_Predicate_sve_prfop: { 526 527 return (((uint32_t)Imm) <= 15); 528 529 llvm_unreachable("ImmediateCode should have returned"); 530 return false; 531 } 532 case GIPFP_I64_Predicate_tbz_imm0_31_diag: { 533 534 return (((uint32_t)Imm) < 32); 535 536 llvm_unreachable("ImmediateCode should have returned"); 537 return false; 538 } 539 case GIPFP_I64_Predicate_tbz_imm0_31_nodiag: { 540 541 return (((uint32_t)Imm) < 32); 542 543 llvm_unreachable("ImmediateCode should have returned"); 544 return false; 545 } 546 case GIPFP_I64_Predicate_tbz_imm32_63: { 547 548 return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64); 549 550 llvm_unreachable("ImmediateCode should have returned"); 551 return false; 552 } 553 case GIPFP_I64_Predicate_uimm5s2: { 554 return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0); 555 llvm_unreachable("ImmediateCode should have returned"); 556 return false; 557 } 558 case GIPFP_I64_Predicate_uimm5s4: { 559 return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); 560 llvm_unreachable("ImmediateCode should have returned"); 561 return false; 562 } 563 case GIPFP_I64_Predicate_uimm5s8: { 564 return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); 565 llvm_unreachable("ImmediateCode should have returned"); 566 return false; 567 } 568 case GIPFP_I64_Predicate_uimm6: { 569 return Imm >= 0 && Imm < 64; 570 llvm_unreachable("ImmediateCode should have returned"); 571 return false; 572 } 573 case GIPFP_I64_Predicate_uimm6s1: { 574 return Imm >= 0 && Imm < 64; 575 llvm_unreachable("ImmediateCode should have returned"); 576 return false; 577 } 578 case GIPFP_I64_Predicate_uimm6s2: { 579 return Imm >= 0 && Imm < (64*2) && ((Imm % 2) == 0); 580 llvm_unreachable("ImmediateCode should have returned"); 581 return false; 582 } 583 case GIPFP_I64_Predicate_uimm6s4: { 584 return Imm >= 0 && Imm < (64*4) && ((Imm % 4) == 0); 585 llvm_unreachable("ImmediateCode should have returned"); 586 return false; 587 } 588 case GIPFP_I64_Predicate_uimm6s8: { 589 return Imm >= 0 && Imm < (64*8) && ((Imm % 8) == 0); 590 llvm_unreachable("ImmediateCode should have returned"); 591 return false; 592 } 593 case GIPFP_I64_Predicate_vecshiftL16: { 594 595 return (((uint32_t)Imm) < 16); 596 597 llvm_unreachable("ImmediateCode should have returned"); 598 return false; 599 } 600 case GIPFP_I64_Predicate_vecshiftL32: { 601 602 return (((uint32_t)Imm) < 32); 603 604 llvm_unreachable("ImmediateCode should have returned"); 605 return false; 606 } 607 case GIPFP_I64_Predicate_vecshiftL64: { 608 609 return (((uint32_t)Imm) < 64); 610 611 llvm_unreachable("ImmediateCode should have returned"); 612 return false; 613 } 614 case GIPFP_I64_Predicate_vecshiftL8: { 615 616 return (((uint32_t)Imm) < 8); 617 618 llvm_unreachable("ImmediateCode should have returned"); 619 return false; 620 } 621 case GIPFP_I64_Predicate_vecshiftR16: { 622 623 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); 624 625 llvm_unreachable("ImmediateCode should have returned"); 626 return false; 627 } 628 case GIPFP_I64_Predicate_vecshiftR16Narrow: { 629 630 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9); 631 632 llvm_unreachable("ImmediateCode should have returned"); 633 return false; 634 } 635 case GIPFP_I64_Predicate_vecshiftR32: { 636 637 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33); 638 639 llvm_unreachable("ImmediateCode should have returned"); 640 return false; 641 } 642 case GIPFP_I64_Predicate_vecshiftR32Narrow: { 643 644 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); 645 646 llvm_unreachable("ImmediateCode should have returned"); 647 return false; 648 } 649 case GIPFP_I64_Predicate_vecshiftR64: { 650 651 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65); 652 653 llvm_unreachable("ImmediateCode should have returned"); 654 return false; 655 } 656 case GIPFP_I64_Predicate_vecshiftR64Narrow: { 657 658 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33); 659 660 llvm_unreachable("ImmediateCode should have returned"); 661 return false; 662 } 663 case GIPFP_I64_Predicate_vecshiftR8: { 664 665 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9); 666 667 llvm_unreachable("ImmediateCode should have returned"); 668 return false; 669 } 670 } 671 llvm_unreachable("Unknown predicate"); 672 return false; 673} 674// PatFrag predicates. 675enum { 676 GIPFP_APFloat_Predicate_fpimm0 = GIPFP_APFloat_Invalid + 1, 677 GIPFP_APFloat_Predicate_fpimm16, 678 GIPFP_APFloat_Predicate_fpimm32, 679 GIPFP_APFloat_Predicate_fpimm64, 680 GIPFP_APFloat_Predicate_simdimmtype10, 681}; 682bool AArch64InstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { 683 switch (PredicateID) { 684 case GIPFP_APFloat_Predicate_fpimm0: { 685 686 return Imm.isExactlyValue(+0.0); 687 688 llvm_unreachable("ImmediateCode should have returned"); 689 return false; 690 } 691 case GIPFP_APFloat_Predicate_fpimm16: { 692 693 return AArch64_AM::getFP16Imm(Imm) != -1; 694 695 llvm_unreachable("ImmediateCode should have returned"); 696 return false; 697 } 698 case GIPFP_APFloat_Predicate_fpimm32: { 699 700 return AArch64_AM::getFP32Imm(Imm) != -1; 701 702 llvm_unreachable("ImmediateCode should have returned"); 703 return false; 704 } 705 case GIPFP_APFloat_Predicate_fpimm64: { 706 707 return AArch64_AM::getFP64Imm(Imm) != -1; 708 709 llvm_unreachable("ImmediateCode should have returned"); 710 return false; 711 } 712 case GIPFP_APFloat_Predicate_simdimmtype10: { 713 714 return AArch64_AM::isAdvSIMDModImmType10( 715 Imm.bitcastToAPInt().getZExtValue()); 716 717 llvm_unreachable("ImmediateCode should have returned"); 718 return false; 719 } 720 } 721 llvm_unreachable("Unknown predicate"); 722 return false; 723} 724// PatFrag predicates. 725enum { 726 GIPFP_APInt_Predicate_logical_imm32 = GIPFP_APInt_Invalid + 1, 727 GIPFP_APInt_Predicate_logical_imm64, 728}; 729bool AArch64InstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { 730 switch (PredicateID) { 731 case GIPFP_APInt_Predicate_logical_imm32: { 732 733 return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 32); 734 735 llvm_unreachable("ImmediateCode should have returned"); 736 return false; 737 } 738 case GIPFP_APInt_Predicate_logical_imm64: { 739 740 return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 64); 741 742 llvm_unreachable("ImmediateCode should have returned"); 743 return false; 744 } 745 } 746 llvm_unreachable("Unknown predicate"); 747 return false; 748} 749bool AArch64InstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const { 750 const MachineFunction &MF = *MI.getParent()->getParent(); 751 const MachineRegisterInfo &MRI = MF.getRegInfo(); 752 (void)MRI; 753 llvm_unreachable("Unknown predicate"); 754 return false; 755} 756 757AArch64InstructionSelector::ComplexMatcherMemFn 758AArch64InstructionSelector::ComplexPredicateFns[] = { 759 nullptr, // GICP_Invalid 760 &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm32 761 &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm64 762 &AArch64InstructionSelector::selectAddrModeIndexed<128>, // gi_am_indexed128 763 &AArch64InstructionSelector::selectAddrModeIndexed<16>, // gi_am_indexed16 764 &AArch64InstructionSelector::selectAddrModeIndexed<32>, // gi_am_indexed32 765 &AArch64InstructionSelector::selectAddrModeIndexed<64>, // gi_am_indexed64 766 &AArch64InstructionSelector::selectAddrModeIndexed<8>, // gi_am_indexed8 767 &AArch64InstructionSelector::selectAddrModeUnscaled128, // gi_am_unscaled128 768 &AArch64InstructionSelector::selectAddrModeUnscaled16, // gi_am_unscaled16 769 &AArch64InstructionSelector::selectAddrModeUnscaled32, // gi_am_unscaled32 770 &AArch64InstructionSelector::selectAddrModeUnscaled64, // gi_am_unscaled64 771 &AArch64InstructionSelector::selectAddrModeUnscaled8, // gi_am_unscaled8 772}; 773 774// Custom renderers. 775enum { 776 GICR_Invalid, 777 GICR_renderTruncImm, 778}; 779AArch64InstructionSelector::CustomRendererFn 780AArch64InstructionSelector::CustomRenderers[] = { 781 nullptr, // GICP_Invalid 782 &AArch64InstructionSelector::renderTruncImm, // gi_trunc_imm 783}; 784 785bool AArch64InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { 786 MachineFunction &MF = *I.getParent()->getParent(); 787 MachineRegisterInfo &MRI = MF.getRegInfo(); 788 // FIXME: This should be computed on a per-function basis rather than per-insn. 789 AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF); 790 const PredicateBitset AvailableFeatures = getAvailableFeatures(); 791 NewMIVector OutMIs; 792 State.MIs.clear(); 793 State.MIs.push_back(&I); 794 795 if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) { 796 return true; 797 } 798 799 return false; 800} 801 802const int64_t *AArch64InstructionSelector::getMatchTable() const { 803 constexpr static int64_t MatchTable0[] = { 804 GIM_SwitchOpcode, /*MI*/0, /*[*/34, 124, /*)*//*default:*//*Label 49*/ 77510, 805 /*TargetOpcode::G_ADD*//*Label 0*/ 95, 806 /*TargetOpcode::G_SUB*//*Label 1*/ 7370, 807 /*TargetOpcode::G_MUL*//*Label 2*/ 9951, 808 /*TargetOpcode::G_SDIV*//*Label 3*/ 10732, 809 /*TargetOpcode::G_UDIV*//*Label 4*/ 10801, 0, 0, 810 /*TargetOpcode::G_AND*//*Label 5*/ 10870, 811 /*TargetOpcode::G_OR*//*Label 6*/ 11412, 812 /*TargetOpcode::G_XOR*//*Label 7*/ 11954, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 813 /*TargetOpcode::G_BITCAST*//*Label 8*/ 12664, 814 /*TargetOpcode::G_LOAD*//*Label 9*/ 20157, 815 /*TargetOpcode::G_SEXTLOAD*//*Label 10*/ 22213, 816 /*TargetOpcode::G_ZEXTLOAD*//*Label 11*/ 22684, 817 /*TargetOpcode::G_STORE*//*Label 12*/ 23036, 0, 818 /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 13*/ 24935, 819 /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 14*/ 26132, 820 /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 15*/ 27161, 821 /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 16*/ 28190, 822 /*TargetOpcode::G_ATOMICRMW_AND*//*Label 17*/ 29599, 0, 823 /*TargetOpcode::G_ATOMICRMW_OR*//*Label 18*/ 31008, 824 /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 19*/ 32037, 825 /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 20*/ 33066, 826 /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 21*/ 34095, 827 /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 22*/ 35124, 828 /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 23*/ 36153, 0, 0, 829 /*TargetOpcode::G_INTRINSIC*//*Label 24*/ 37182, 830 /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 25*/ 71113, 831 /*TargetOpcode::G_ANYEXT*//*Label 26*/ 71293, 832 /*TargetOpcode::G_TRUNC*//*Label 27*/ 71407, 833 /*TargetOpcode::G_CONSTANT*//*Label 28*/ 71532, 834 /*TargetOpcode::G_FCONSTANT*//*Label 29*/ 71585, 0, 0, 835 /*TargetOpcode::G_SEXT*//*Label 30*/ 71663, 836 /*TargetOpcode::G_ZEXT*//*Label 31*/ 71777, 837 /*TargetOpcode::G_SHL*//*Label 32*/ 72236, 838 /*TargetOpcode::G_LSHR*//*Label 33*/ 72412, 839 /*TargetOpcode::G_ASHR*//*Label 34*/ 72663, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 840 /*TargetOpcode::G_FADD*//*Label 35*/ 72914, 841 /*TargetOpcode::G_FSUB*//*Label 36*/ 73187, 842 /*TargetOpcode::G_FMUL*//*Label 37*/ 73460, 843 /*TargetOpcode::G_FMA*//*Label 38*/ 73733, 844 /*TargetOpcode::G_FDIV*//*Label 39*/ 75257, 0, 0, 0, 0, 0, 0, 845 /*TargetOpcode::G_FNEG*//*Label 40*/ 75530, 846 /*TargetOpcode::G_FPEXT*//*Label 41*/ 76078, 847 /*TargetOpcode::G_FPTRUNC*//*Label 42*/ 76207, 848 /*TargetOpcode::G_FPTOSI*//*Label 43*/ 76336, 849 /*TargetOpcode::G_FPTOUI*//*Label 44*/ 76612, 850 /*TargetOpcode::G_SITOFP*//*Label 45*/ 76888, 851 /*TargetOpcode::G_UITOFP*//*Label 46*/ 77166, 0, 0, 0, 852 /*TargetOpcode::G_BR*//*Label 47*/ 77444, 0, 0, 0, 853 /*TargetOpcode::G_BSWAP*//*Label 48*/ 77457, 854 // Label 0: @95 855 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 59*/ 7369, 856 /*GILLT_s32*//*Label 50*/ 111, 857 /*GILLT_s64*//*Label 51*/ 212, 0, 858 /*GILLT_v2s32*//*Label 52*/ 1284, 859 /*GILLT_v2s64*//*Label 53*/ 1897, 860 /*GILLT_v4s16*//*Label 54*/ 3000, 861 /*GILLT_v4s32*//*Label 55*/ 3613, 862 /*GILLT_v8s8*//*Label 56*/ 5086, 863 /*GILLT_v8s16*//*Label 57*/ 5491, 864 /*GILLT_v16s8*//*Label 58*/ 6964, 865 // Label 50: @111 866 GIM_Try, /*On fail goto*//*Label 60*/ 211, 867 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 868 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 869 GIM_Try, /*On fail goto*//*Label 61*/ 155, // Rule ID 3775 // 870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, 871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32spRegClassID, 872 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32, 873 // (add:{ *:[i32] } addsub_shifted_imm32:{ *:[i32] }:$imm, GPR32sp:{ *:[i32] }:$Rn) => (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) 874 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri, 875 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 876 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 877 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm 878 GIR_EraseFromParent, /*InsnID*/0, 879 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 880 // GIR_Coverage, 3775, 881 GIR_Done, 882 // Label 61: @155 883 GIM_Try, /*On fail goto*//*Label 62*/ 189, // Rule ID 33 // 884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, 885 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID, 886 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32, 887 // (add:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) => (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) 888 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri, 889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 891 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm 892 GIR_EraseFromParent, /*InsnID*/0, 893 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 894 // GIR_Coverage, 33, 895 GIR_Done, 896 // Label 62: @189 897 GIM_Try, /*On fail goto*//*Label 63*/ 210, // Rule ID 35 // 898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 901 // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (ADDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 902 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDWrr, 903 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 904 // GIR_Coverage, 35, 905 GIR_Done, 906 // Label 63: @210 907 GIM_Reject, 908 // Label 60: @211 909 GIM_Reject, 910 // Label 51: @212 911 GIM_Try, /*On fail goto*//*Label 64*/ 1283, 912 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 913 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 914 GIM_Try, /*On fail goto*//*Label 65*/ 256, // Rule ID 3776 // 915 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, 916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, 917 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm64, 918 // (add:{ *:[i64] } addsub_shifted_imm64:{ *:[i64] }:$imm, GPR64sp:{ *:[i64] }:$Rn) => (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) 919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri, 920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 922 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm 923 GIR_EraseFromParent, /*InsnID*/0, 924 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 925 // GIR_Coverage, 3776, 926 GIR_Done, 927 // Label 65: @256 928 GIM_Try, /*On fail goto*//*Label 66*/ 352, // Rule ID 1886 // 929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 930 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 931 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 932 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 933 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 934 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 935 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, 936 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 937 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 938 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] 939 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, 940 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, 941 // MIs[3] Operand 1 942 // No operand predicates 943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 944 GIM_CheckIsSafeToFold, /*InsnID*/1, 945 GIM_CheckIsSafeToFold, /*InsnID*/2, 946 GIM_CheckIsSafeToFold, /*InsnID*/3, 947 // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) 948 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 949 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, 950 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 951 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C 952 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 953 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, 954 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn 956 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 957 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra 958 GIR_EraseFromParent, /*InsnID*/0, 959 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 960 // GIR_Coverage, 1886, 961 GIR_Done, 962 // Label 66: @352 963 GIM_Try, /*On fail goto*//*Label 67*/ 448, // Rule ID 1887 // 964 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 965 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 966 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 967 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 968 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 969 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 970 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, 971 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 972 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 973 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] 974 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, 975 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, 976 // MIs[3] Operand 1 977 // No operand predicates 978 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 979 GIM_CheckIsSafeToFold, /*InsnID*/1, 980 GIM_CheckIsSafeToFold, /*InsnID*/2, 981 GIM_CheckIsSafeToFold, /*InsnID*/3, 982 // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) 983 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 984 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, 985 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 986 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C 987 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 988 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, 989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn 991 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra 993 GIR_EraseFromParent, /*InsnID*/0, 994 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 995 // GIR_Coverage, 1887, 996 GIR_Done, 997 // Label 67: @448 998 GIM_Try, /*On fail goto*//*Label 68*/ 482, // Rule ID 34 // 999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, 1000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 1001 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64, 1002 // (add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) => (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) 1003 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri, 1004 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 1005 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 1006 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm 1007 GIR_EraseFromParent, /*InsnID*/0, 1008 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1009 // GIR_Coverage, 34, 1010 GIR_Done, 1011 // Label 68: @482 1012 GIM_Try, /*On fail goto*//*Label 69*/ 578, // Rule ID 4027 // 1013 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 1014 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 1015 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1016 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1017 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 1018 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 1019 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 1020 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, 1021 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 1022 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 1023 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] 1024 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, 1025 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, 1026 // MIs[3] Operand 1 1027 // No operand predicates 1028 GIM_CheckIsSafeToFold, /*InsnID*/1, 1029 GIM_CheckIsSafeToFold, /*InsnID*/2, 1030 GIM_CheckIsSafeToFold, /*InsnID*/3, 1031 // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C)) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) 1032 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 1033 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, 1034 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 1035 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C 1036 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 1037 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, 1038 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 1039 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn 1040 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 1041 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra 1042 GIR_EraseFromParent, /*InsnID*/0, 1043 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1044 // GIR_Coverage, 4027, 1045 GIR_Done, 1046 // Label 69: @578 1047 GIM_Try, /*On fail goto*//*Label 70*/ 674, // Rule ID 4028 // 1048 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 1049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 1050 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1051 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1052 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 1053 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 1054 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 1055 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, 1056 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 1057 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 1058 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] 1059 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, 1060 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, 1061 // MIs[3] Operand 1 1062 // No operand predicates 1063 GIM_CheckIsSafeToFold, /*InsnID*/1, 1064 GIM_CheckIsSafeToFold, /*InsnID*/2, 1065 GIM_CheckIsSafeToFold, /*InsnID*/3, 1066 // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C)) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) 1067 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 1068 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, 1069 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 1070 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C 1071 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 1072 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, 1073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 1074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn 1075 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 1076 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra 1077 GIR_EraseFromParent, /*InsnID*/0, 1078 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1079 // GIR_Coverage, 4028, 1080 GIR_Done, 1081 // Label 70: @674 1082 GIM_Try, /*On fail goto*//*Label 71*/ 759, // Rule ID 3787 // 1083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 1084 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1085 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1086 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 1087 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 1088 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 1089 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, 1090 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 1091 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 1092 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] 1093 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT, 1094 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, 1095 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 1096 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 1097 GIM_CheckIsSafeToFold, /*InsnID*/1, 1098 GIM_CheckIsSafeToFold, /*InsnID*/2, 1099 GIM_CheckIsSafeToFold, /*InsnID*/3, 1100 // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) 1101 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, 1102 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 1103 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn 1104 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm 1105 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra 1106 GIR_EraseFromParent, /*InsnID*/0, 1107 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1108 // GIR_Coverage, 3787, 1109 GIR_Done, 1110 // Label 71: @759 1111 GIM_Try, /*On fail goto*//*Label 72*/ 844, // Rule ID 3788 // 1112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 1113 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1114 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1115 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 1116 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 1117 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 1118 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, 1119 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 1120 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 1121 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] 1122 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, 1123 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, 1124 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 1125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 1126 GIM_CheckIsSafeToFold, /*InsnID*/1, 1127 GIM_CheckIsSafeToFold, /*InsnID*/2, 1128 GIM_CheckIsSafeToFold, /*InsnID*/3, 1129 // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) 1130 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, 1131 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 1132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn 1133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm 1134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra 1135 GIR_EraseFromParent, /*InsnID*/0, 1136 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1137 // GIR_Coverage, 3788, 1138 GIR_Done, 1139 // Label 72: @844 1140 GIM_Try, /*On fail goto*//*Label 73*/ 929, // Rule ID 65 // 1141 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 1142 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 1143 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1144 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1145 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 1146 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 1147 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 1148 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, 1149 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 1150 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 1151 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] 1152 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT, 1153 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, 1154 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 1155 GIM_CheckIsSafeToFold, /*InsnID*/1, 1156 GIM_CheckIsSafeToFold, /*InsnID*/2, 1157 GIM_CheckIsSafeToFold, /*InsnID*/3, 1158 // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) 1159 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, 1160 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 1161 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn 1162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm 1163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra 1164 GIR_EraseFromParent, /*InsnID*/0, 1165 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1166 // GIR_Coverage, 65, 1167 GIR_Done, 1168 // Label 73: @929 1169 GIM_Try, /*On fail goto*//*Label 74*/ 1014, // Rule ID 67 // 1170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 1171 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 1172 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1173 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1174 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 1175 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 1176 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 1177 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, 1178 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 1179 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 1180 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] 1181 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, 1182 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, 1183 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 1184 GIM_CheckIsSafeToFold, /*InsnID*/1, 1185 GIM_CheckIsSafeToFold, /*InsnID*/2, 1186 GIM_CheckIsSafeToFold, /*InsnID*/3, 1187 // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) 1188 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, 1189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 1190 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn 1191 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm 1192 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra 1193 GIR_EraseFromParent, /*InsnID*/0, 1194 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1195 // GIR_Coverage, 67, 1196 GIR_Done, 1197 // Label 74: @1014 1198 GIM_Try, /*On fail goto*//*Label 75*/ 1070, // Rule ID 3841 // 1199 GIM_CheckFeatures, GIFBS_HasNEON, 1200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 1201 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1202 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1203 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 1204 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, 1205 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 1206 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1207 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1208 GIM_CheckIsSafeToFold, /*InsnID*/1, 1209 // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 271:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd) => (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn) 1210 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64, 1211 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1212 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 1213 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1214 GIR_EraseFromParent, /*InsnID*/0, 1215 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1216 // GIR_Coverage, 3841, 1217 GIR_Done, 1218 // Label 75: @1070 1219 GIM_Try, /*On fail goto*//*Label 76*/ 1126, // Rule ID 3847 // 1220 GIM_CheckFeatures, GIFBS_HasNEON, 1221 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 1222 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1223 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1224 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 1225 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, 1226 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 1227 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1228 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1229 GIM_CheckIsSafeToFold, /*InsnID*/1, 1230 // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 329:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd) => (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn) 1231 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv2i32_v1i64, 1232 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1233 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 1234 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1235 GIR_EraseFromParent, /*InsnID*/0, 1236 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1237 // GIR_Coverage, 3847, 1238 GIR_Done, 1239 // Label 76: @1126 1240 GIM_Try, /*On fail goto*//*Label 77*/ 1182, // Rule ID 687 // 1241 GIM_CheckFeatures, GIFBS_HasNEON, 1242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 1243 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 1244 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1245 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1246 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 1247 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, 1248 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 1249 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1250 GIM_CheckIsSafeToFold, /*InsnID*/1, 1251 // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 271:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)) => (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn) 1252 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64, 1253 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1254 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 1255 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1256 GIR_EraseFromParent, /*InsnID*/0, 1257 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1258 // GIR_Coverage, 687, 1259 GIR_Done, 1260 // Label 77: @1182 1261 GIM_Try, /*On fail goto*//*Label 78*/ 1238, // Rule ID 731 // 1262 GIM_CheckFeatures, GIFBS_HasNEON, 1263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 1264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 1265 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1266 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1267 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 1268 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, 1269 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 1270 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1271 GIM_CheckIsSafeToFold, /*InsnID*/1, 1272 // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 329:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)) => (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn) 1273 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv2i32_v1i64, 1274 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1275 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 1276 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1277 GIR_EraseFromParent, /*InsnID*/0, 1278 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1279 // GIR_Coverage, 731, 1280 GIR_Done, 1281 // Label 78: @1238 1282 GIM_Try, /*On fail goto*//*Label 79*/ 1259, // Rule ID 36 // 1283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 1284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 1285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 1286 // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ADDXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) 1287 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDXrr, 1288 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1289 // GIR_Coverage, 36, 1290 GIR_Done, 1291 // Label 79: @1259 1292 GIM_Try, /*On fail goto*//*Label 80*/ 1282, // Rule ID 1186 // 1293 GIM_CheckFeatures, GIFBS_HasNEON, 1294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 1295 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 1296 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1297 // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (ADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) 1298 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv1i64, 1299 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1300 // GIR_Coverage, 1186, 1301 GIR_Done, 1302 // Label 80: @1282 1303 GIM_Reject, 1304 // Label 64: @1283 1305 GIM_Reject, 1306 // Label 52: @1284 1307 GIM_Try, /*On fail goto*//*Label 81*/ 1896, 1308 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 1309 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 1310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 1311 GIM_Try, /*On fail goto*//*Label 82*/ 1362, // Rule ID 3859 // 1312 GIM_CheckFeatures, GIFBS_HasNEON, 1313 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1314 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1315 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 1316 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, 1317 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 1318 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, 1319 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1320 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 1321 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1322 GIM_CheckIsSafeToFold, /*InsnID*/1, 1323 // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 270:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd) => (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1324 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32, 1325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 1327 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1328 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 1329 GIR_EraseFromParent, /*InsnID*/0, 1330 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1331 // GIR_Coverage, 3859, 1332 GIR_Done, 1333 // Label 82: @1362 1334 GIM_Try, /*On fail goto*//*Label 83*/ 1426, // Rule ID 3865 // 1335 GIM_CheckFeatures, GIFBS_HasNEON, 1336 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1337 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1338 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 1339 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, 1340 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 1341 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, 1342 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1343 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 1344 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1345 GIM_CheckIsSafeToFold, /*InsnID*/1, 1346 // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 328:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd) => (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1347 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32, 1348 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1349 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 1350 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1351 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 1352 GIR_EraseFromParent, /*InsnID*/0, 1353 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1354 // GIR_Coverage, 3865, 1355 GIR_Done, 1356 // Label 83: @1426 1357 GIM_Try, /*On fail goto*//*Label 84*/ 1478, // Rule ID 3839 // 1358 GIM_CheckFeatures, GIFBS_HasNEON, 1359 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1360 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1361 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 1362 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, 1363 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 1364 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1366 GIM_CheckIsSafeToFold, /*InsnID*/1, 1367 // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 271:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd) => (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn) 1368 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32, 1369 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1370 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 1371 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1372 GIR_EraseFromParent, /*InsnID*/0, 1373 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1374 // GIR_Coverage, 3839, 1375 GIR_Done, 1376 // Label 84: @1478 1377 GIM_Try, /*On fail goto*//*Label 85*/ 1530, // Rule ID 3845 // 1378 GIM_CheckFeatures, GIFBS_HasNEON, 1379 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1380 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1381 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 1382 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, 1383 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 1384 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1386 GIM_CheckIsSafeToFold, /*InsnID*/1, 1387 // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 329:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd) => (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn) 1388 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i16_v2i32, 1389 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1390 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 1391 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1392 GIR_EraseFromParent, /*InsnID*/0, 1393 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1394 // GIR_Coverage, 3845, 1395 GIR_Done, 1396 // Label 85: @1530 1397 GIM_Try, /*On fail goto*//*Label 86*/ 1594, // Rule ID 961 // 1398 GIM_CheckFeatures, GIFBS_HasNEON, 1399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 1400 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1401 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1402 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 1403 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, 1404 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 1405 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, 1406 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1407 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 1408 GIM_CheckIsSafeToFold, /*InsnID*/1, 1409 // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 270:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1410 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32, 1411 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1412 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 1413 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1414 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 1415 GIR_EraseFromParent, /*InsnID*/0, 1416 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1417 // GIR_Coverage, 961, 1418 GIR_Done, 1419 // Label 86: @1594 1420 GIM_Try, /*On fail goto*//*Label 87*/ 1658, // Rule ID 1072 // 1421 GIM_CheckFeatures, GIFBS_HasNEON, 1422 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 1423 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1424 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1425 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 1426 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, 1427 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 1428 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, 1429 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1430 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 1431 GIM_CheckIsSafeToFold, /*InsnID*/1, 1432 // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 328:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32, 1434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1435 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 1436 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1437 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 1438 GIR_EraseFromParent, /*InsnID*/0, 1439 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1440 // GIR_Coverage, 1072, 1441 GIR_Done, 1442 // Label 87: @1658 1443 GIM_Try, /*On fail goto*//*Label 88*/ 1710, // Rule ID 685 // 1444 GIM_CheckFeatures, GIFBS_HasNEON, 1445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 1446 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1447 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1448 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 1449 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, 1450 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 1451 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1452 GIM_CheckIsSafeToFold, /*InsnID*/1, 1453 // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 271:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)) => (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn) 1454 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32, 1455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1456 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 1457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1458 GIR_EraseFromParent, /*InsnID*/0, 1459 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1460 // GIR_Coverage, 685, 1461 GIR_Done, 1462 // Label 88: @1710 1463 GIM_Try, /*On fail goto*//*Label 89*/ 1762, // Rule ID 729 // 1464 GIM_CheckFeatures, GIFBS_HasNEON, 1465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 1466 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1467 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1468 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 1469 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, 1470 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 1471 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1472 GIM_CheckIsSafeToFold, /*InsnID*/1, 1473 // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 329:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)) => (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn) 1474 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i16_v2i32, 1475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1476 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 1477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1478 GIR_EraseFromParent, /*InsnID*/0, 1479 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1480 // GIR_Coverage, 729, 1481 GIR_Done, 1482 // Label 89: @1762 1483 GIM_Try, /*On fail goto*//*Label 90*/ 1819, // Rule ID 3853 // 1484 GIM_CheckFeatures, GIFBS_HasNEON, 1485 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1486 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1487 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, 1488 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 1489 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 1490 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1491 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1492 GIM_CheckIsSafeToFold, /*InsnID*/1, 1493 // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd) => (MLAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1494 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv2i32, 1495 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1496 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 1497 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 1498 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 1499 GIR_EraseFromParent, /*InsnID*/0, 1500 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1501 // GIR_Coverage, 3853, 1502 GIR_Done, 1503 // Label 90: @1819 1504 GIM_Try, /*On fail goto*//*Label 91*/ 1876, // Rule ID 941 // 1505 GIM_CheckFeatures, GIFBS_HasNEON, 1506 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 1507 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1508 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1509 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, 1510 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 1511 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 1512 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1513 GIM_CheckIsSafeToFold, /*InsnID*/1, 1514 // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (MLAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1515 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv2i32, 1516 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1517 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 1518 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 1519 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 1520 GIR_EraseFromParent, /*InsnID*/0, 1521 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1522 // GIR_Coverage, 941, 1523 GIR_Done, 1524 // Label 91: @1876 1525 GIM_Try, /*On fail goto*//*Label 92*/ 1895, // Rule ID 765 // 1526 GIM_CheckFeatures, GIFBS_HasNEON, 1527 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 1528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1529 // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (ADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1530 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv2i32, 1531 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1532 // GIR_Coverage, 765, 1533 GIR_Done, 1534 // Label 92: @1895 1535 GIM_Reject, 1536 // Label 81: @1896 1537 GIM_Reject, 1538 // Label 53: @1897 1539 GIM_Try, /*On fail goto*//*Label 93*/ 2999, 1540 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 1541 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 1542 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 1543 GIM_Try, /*On fail goto*//*Label 94*/ 1988, // Rule ID 3913 // 1544 GIM_CheckFeatures, GIFBS_HasNEON, 1545 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1546 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 1547 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, 1548 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 1549 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, 1550 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, 1551 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, 1552 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, 1553 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, 1554 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1555 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 1556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 1557 GIM_CheckIsSafeToFold, /*InsnID*/1, 1558 GIM_CheckIsSafeToFold, /*InsnID*/2, 1559 // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 270:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd) => (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1560 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64, 1561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 1563 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn 1564 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm 1565 GIR_EraseFromParent, /*InsnID*/0, 1566 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1567 // GIR_Coverage, 3913, 1568 GIR_Done, 1569 // Label 94: @1988 1570 GIM_Try, /*On fail goto*//*Label 95*/ 2065, // Rule ID 3931 // 1571 GIM_CheckFeatures, GIFBS_HasNEON, 1572 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1573 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 1574 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, 1575 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 1576 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, 1577 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, 1578 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, 1579 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, 1580 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, 1581 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1582 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 1583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 1584 GIM_CheckIsSafeToFold, /*InsnID*/1, 1585 GIM_CheckIsSafeToFold, /*InsnID*/2, 1586 // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 328:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd) => (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1587 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64, 1588 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1589 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 1590 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn 1591 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm 1592 GIR_EraseFromParent, /*InsnID*/0, 1593 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1594 // GIR_Coverage, 3931, 1595 GIR_Done, 1596 // Label 95: @2065 1597 GIM_Try, /*On fail goto*//*Label 96*/ 2142, // Rule ID 1268 // 1598 GIM_CheckFeatures, GIFBS_HasNEON, 1599 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 1600 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1601 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 1602 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, 1603 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 1604 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, 1605 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, 1606 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, 1607 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, 1608 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, 1609 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1610 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 1611 GIM_CheckIsSafeToFold, /*InsnID*/1, 1612 GIM_CheckIsSafeToFold, /*InsnID*/2, 1613 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 270:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))) => (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1614 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64, 1615 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1616 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 1617 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn 1618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm 1619 GIR_EraseFromParent, /*InsnID*/0, 1620 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1621 // GIR_Coverage, 1268, 1622 GIR_Done, 1623 // Label 96: @2142 1624 GIM_Try, /*On fail goto*//*Label 97*/ 2219, // Rule ID 1334 // 1625 GIM_CheckFeatures, GIFBS_HasNEON, 1626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 1627 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1628 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 1629 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, 1630 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 1631 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, 1632 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, 1633 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, 1634 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, 1635 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, 1636 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1637 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 1638 GIM_CheckIsSafeToFold, /*InsnID*/1, 1639 GIM_CheckIsSafeToFold, /*InsnID*/2, 1640 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 328:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))) => (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1641 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64, 1642 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1643 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 1644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn 1645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm 1646 GIR_EraseFromParent, /*InsnID*/0, 1647 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1648 // GIR_Coverage, 1334, 1649 GIR_Done, 1650 // Label 97: @2219 1651 GIM_Try, /*On fail goto*//*Label 98*/ 2283, // Rule ID 3925 // 1652 GIM_CheckFeatures, GIFBS_HasNEON, 1653 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1654 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1655 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 1656 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, 1657 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 1658 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, 1659 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1660 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 1661 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 1662 GIM_CheckIsSafeToFold, /*InsnID*/1, 1663 // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 287:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd) => (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1664 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_v2i64, 1665 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1666 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 1667 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1668 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 1669 GIR_EraseFromParent, /*InsnID*/0, 1670 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1671 // GIR_Coverage, 3925, 1672 GIR_Done, 1673 // Label 98: @2283 1674 GIM_Try, /*On fail goto*//*Label 99*/ 2347, // Rule ID 3943 // 1675 GIM_CheckFeatures, GIFBS_HasNEON, 1676 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1677 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1678 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 1679 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, 1680 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 1681 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, 1682 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1683 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 1684 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 1685 GIM_CheckIsSafeToFold, /*InsnID*/1, 1686 // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 341:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd) => (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1687 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_v2i64, 1688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 1690 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1691 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 1692 GIR_EraseFromParent, /*InsnID*/0, 1693 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1694 // GIR_Coverage, 3943, 1695 GIR_Done, 1696 // Label 99: @2347 1697 GIM_Try, /*On fail goto*//*Label 100*/ 2399, // Rule ID 3842 // 1698 GIM_CheckFeatures, GIFBS_HasNEON, 1699 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1700 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1701 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 1702 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, 1703 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 1704 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 1705 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 1706 GIM_CheckIsSafeToFold, /*InsnID*/1, 1707 // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 271:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd) => (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn) 1708 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64, 1709 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1710 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 1711 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1712 GIR_EraseFromParent, /*InsnID*/0, 1713 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1714 // GIR_Coverage, 3842, 1715 GIR_Done, 1716 // Label 100: @2399 1717 GIM_Try, /*On fail goto*//*Label 101*/ 2451, // Rule ID 3848 // 1718 GIM_CheckFeatures, GIFBS_HasNEON, 1719 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1720 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1721 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 1722 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, 1723 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 1724 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 1725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 1726 GIM_CheckIsSafeToFold, /*InsnID*/1, 1727 // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 329:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd) => (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn) 1728 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i32_v2i64, 1729 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1730 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 1731 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1732 GIR_EraseFromParent, /*InsnID*/0, 1733 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1734 // GIR_Coverage, 3848, 1735 GIR_Done, 1736 // Label 101: @2451 1737 GIM_Try, /*On fail goto*//*Label 102*/ 2515, // Rule ID 1292 // 1738 GIM_CheckFeatures, GIFBS_HasNEON, 1739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 1740 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1741 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1742 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 1743 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, 1744 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 1745 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, 1746 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1747 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 1748 GIM_CheckIsSafeToFold, /*InsnID*/1, 1749 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 287:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1750 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_v2i64, 1751 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 1753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1754 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 1755 GIR_EraseFromParent, /*InsnID*/0, 1756 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1757 // GIR_Coverage, 1292, 1758 GIR_Done, 1759 // Label 102: @2515 1760 GIM_Try, /*On fail goto*//*Label 103*/ 2579, // Rule ID 1352 // 1761 GIM_CheckFeatures, GIFBS_HasNEON, 1762 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 1763 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1764 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1765 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 1766 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, 1767 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 1768 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, 1769 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1770 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 1771 GIM_CheckIsSafeToFold, /*InsnID*/1, 1772 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 341:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1773 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_v2i64, 1774 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1775 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 1776 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 1778 GIR_EraseFromParent, /*InsnID*/0, 1779 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1780 // GIR_Coverage, 1352, 1781 GIR_Done, 1782 // Label 103: @2579 1783 GIM_Try, /*On fail goto*//*Label 104*/ 2631, // Rule ID 688 // 1784 GIM_CheckFeatures, GIFBS_HasNEON, 1785 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 1786 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1787 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1788 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 1789 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, 1790 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 1791 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 1792 GIM_CheckIsSafeToFold, /*InsnID*/1, 1793 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 271:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn) 1794 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64, 1795 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1796 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 1797 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1798 GIR_EraseFromParent, /*InsnID*/0, 1799 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1800 // GIR_Coverage, 688, 1801 GIR_Done, 1802 // Label 104: @2631 1803 GIM_Try, /*On fail goto*//*Label 105*/ 2683, // Rule ID 732 // 1804 GIM_CheckFeatures, GIFBS_HasNEON, 1805 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 1806 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1807 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1808 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 1809 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, 1810 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 1811 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 1812 GIM_CheckIsSafeToFold, /*InsnID*/1, 1813 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 329:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn) 1814 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i32_v2i64, 1815 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1816 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 1817 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1818 GIR_EraseFromParent, /*InsnID*/0, 1819 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1820 // GIR_Coverage, 732, 1821 GIR_Done, 1822 // Label 105: @2683 1823 GIM_Try, /*On fail goto*//*Label 106*/ 2741, // Rule ID 1280 // 1824 GIM_CheckFeatures, GIFBS_HasNEON, 1825 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1826 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 1827 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, 1828 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 1829 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 1830 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, 1831 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, 1832 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 1833 GIM_CheckIsSafeToFold, /*InsnID*/1, 1834 GIM_CheckIsSafeToFold, /*InsnID*/2, 1835 // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1836 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv2i32_v2i64, 1837 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 1838 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 1839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm 1840 GIR_EraseFromParent, /*InsnID*/0, 1841 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1842 // GIR_Coverage, 1280, 1843 GIR_Done, 1844 // Label 106: @2741 1845 GIM_Try, /*On fail goto*//*Label 107*/ 2799, // Rule ID 1340 // 1846 GIM_CheckFeatures, GIFBS_HasNEON, 1847 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1848 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 1849 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, 1850 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 1851 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 1852 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, 1853 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, 1854 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 1855 GIM_CheckIsSafeToFold, /*InsnID*/1, 1856 GIM_CheckIsSafeToFold, /*InsnID*/2, 1857 // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1858 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv2i32_v2i64, 1859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 1860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 1861 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm 1862 GIR_EraseFromParent, /*InsnID*/0, 1863 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1864 // GIR_Coverage, 1340, 1865 GIR_Done, 1866 // Label 107: @2799 1867 GIM_Try, /*On fail goto*//*Label 108*/ 2844, // Rule ID 3919 // 1868 GIM_CheckFeatures, GIFBS_HasNEON, 1869 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1870 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 1871 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, 1872 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 1873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 1874 GIM_CheckIsSafeToFold, /*InsnID*/1, 1875 // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn) => (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1876 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv2i32_v2i64, 1877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 1878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 1879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 1880 GIR_EraseFromParent, /*InsnID*/0, 1881 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1882 // GIR_Coverage, 3919, 1883 GIR_Done, 1884 // Label 108: @2844 1885 GIM_Try, /*On fail goto*//*Label 109*/ 2889, // Rule ID 3937 // 1886 GIM_CheckFeatures, GIFBS_HasNEON, 1887 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1888 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 1889 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, 1890 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 1891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 1892 GIM_CheckIsSafeToFold, /*InsnID*/1, 1893 // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn) => (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1894 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64, 1895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 1896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 1897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 1898 GIR_EraseFromParent, /*InsnID*/0, 1899 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1900 // GIR_Coverage, 3937, 1901 GIR_Done, 1902 // Label 109: @2889 1903 GIM_Try, /*On fail goto*//*Label 110*/ 2934, // Rule ID 1286 // 1904 GIM_CheckFeatures, GIFBS_HasNEON, 1905 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 1906 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1907 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 1908 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, 1909 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 1910 GIM_CheckIsSafeToFold, /*InsnID*/1, 1911 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1912 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv2i32_v2i64, 1913 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 1914 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 1915 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 1916 GIR_EraseFromParent, /*InsnID*/0, 1917 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1918 // GIR_Coverage, 1286, 1919 GIR_Done, 1920 // Label 110: @2934 1921 GIM_Try, /*On fail goto*//*Label 111*/ 2979, // Rule ID 1346 // 1922 GIM_CheckFeatures, GIFBS_HasNEON, 1923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 1924 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1925 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 1926 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, 1927 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 1928 GIM_CheckIsSafeToFold, /*InsnID*/1, 1929 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) 1930 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64, 1931 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 1932 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 1933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 1934 GIR_EraseFromParent, /*InsnID*/0, 1935 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1936 // GIR_Coverage, 1346, 1937 GIR_Done, 1938 // Label 111: @2979 1939 GIM_Try, /*On fail goto*//*Label 112*/ 2998, // Rule ID 767 // 1940 GIM_CheckFeatures, GIFBS_HasNEON, 1941 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 1942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 1943 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) 1944 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv2i64, 1945 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1946 // GIR_Coverage, 767, 1947 GIR_Done, 1948 // Label 112: @2998 1949 GIM_Reject, 1950 // Label 93: @2999 1951 GIM_Reject, 1952 // Label 54: @3000 1953 GIM_Try, /*On fail goto*//*Label 113*/ 3612, 1954 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 1955 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 1956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 1957 GIM_Try, /*On fail goto*//*Label 114*/ 3078, // Rule ID 3857 // 1958 GIM_CheckFeatures, GIFBS_HasNEON, 1959 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1960 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1961 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 1962 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, 1963 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 1964 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, 1965 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1966 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 1967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1968 GIM_CheckIsSafeToFold, /*InsnID*/1, 1969 // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 270:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd) => (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 1970 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16, 1971 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 1973 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 1975 GIR_EraseFromParent, /*InsnID*/0, 1976 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1977 // GIR_Coverage, 3857, 1978 GIR_Done, 1979 // Label 114: @3078 1980 GIM_Try, /*On fail goto*//*Label 115*/ 3142, // Rule ID 3863 // 1981 GIM_CheckFeatures, GIFBS_HasNEON, 1982 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1983 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 1984 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 1985 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, 1986 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 1987 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, 1988 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1989 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 1990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 1991 GIM_CheckIsSafeToFold, /*InsnID*/1, 1992 // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 328:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd) => (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 1993 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16, 1994 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 1996 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 1997 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 1998 GIR_EraseFromParent, /*InsnID*/0, 1999 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2000 // GIR_Coverage, 3863, 2001 GIR_Done, 2002 // Label 115: @3142 2003 GIM_Try, /*On fail goto*//*Label 116*/ 3194, // Rule ID 3837 // 2004 GIM_CheckFeatures, GIFBS_HasNEON, 2005 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2006 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2007 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 2008 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, 2009 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, 2010 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2011 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2012 GIM_CheckIsSafeToFold, /*InsnID*/1, 2013 // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 271:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd) => (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn) 2014 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16, 2015 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2016 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 2017 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2018 GIR_EraseFromParent, /*InsnID*/0, 2019 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2020 // GIR_Coverage, 3837, 2021 GIR_Done, 2022 // Label 116: @3194 2023 GIM_Try, /*On fail goto*//*Label 117*/ 3246, // Rule ID 3843 // 2024 GIM_CheckFeatures, GIFBS_HasNEON, 2025 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2026 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2027 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 2028 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, 2029 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, 2030 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2031 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2032 GIM_CheckIsSafeToFold, /*InsnID*/1, 2033 // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 329:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd) => (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn) 2034 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16, 2035 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2036 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 2037 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2038 GIR_EraseFromParent, /*InsnID*/0, 2039 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2040 // GIR_Coverage, 3843, 2041 GIR_Done, 2042 // Label 117: @3246 2043 GIM_Try, /*On fail goto*//*Label 118*/ 3310, // Rule ID 959 // 2044 GIM_CheckFeatures, GIFBS_HasNEON, 2045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2046 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2047 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2048 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 2049 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, 2050 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 2051 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, 2052 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2053 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 2054 GIM_CheckIsSafeToFold, /*InsnID*/1, 2055 // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 270:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 2056 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16, 2057 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2058 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 2059 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2060 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 2061 GIR_EraseFromParent, /*InsnID*/0, 2062 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2063 // GIR_Coverage, 959, 2064 GIR_Done, 2065 // Label 118: @3310 2066 GIM_Try, /*On fail goto*//*Label 119*/ 3374, // Rule ID 1070 // 2067 GIM_CheckFeatures, GIFBS_HasNEON, 2068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2069 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2070 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2071 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 2072 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, 2073 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 2074 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, 2075 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2076 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 2077 GIM_CheckIsSafeToFold, /*InsnID*/1, 2078 // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 328:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 2079 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16, 2080 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2081 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 2082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2083 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 2084 GIR_EraseFromParent, /*InsnID*/0, 2085 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2086 // GIR_Coverage, 1070, 2087 GIR_Done, 2088 // Label 119: @3374 2089 GIM_Try, /*On fail goto*//*Label 120*/ 3426, // Rule ID 683 // 2090 GIM_CheckFeatures, GIFBS_HasNEON, 2091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2092 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2093 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2094 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 2095 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, 2096 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, 2097 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2098 GIM_CheckIsSafeToFold, /*InsnID*/1, 2099 // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 271:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)) => (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn) 2100 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16, 2101 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2102 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 2103 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2104 GIR_EraseFromParent, /*InsnID*/0, 2105 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2106 // GIR_Coverage, 683, 2107 GIR_Done, 2108 // Label 120: @3426 2109 GIM_Try, /*On fail goto*//*Label 121*/ 3478, // Rule ID 727 // 2110 GIM_CheckFeatures, GIFBS_HasNEON, 2111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2112 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2113 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2114 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 2115 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, 2116 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, 2117 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2118 GIM_CheckIsSafeToFold, /*InsnID*/1, 2119 // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 329:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)) => (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn) 2120 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16, 2121 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2122 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 2123 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2124 GIR_EraseFromParent, /*InsnID*/0, 2125 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2126 // GIR_Coverage, 727, 2127 GIR_Done, 2128 // Label 121: @3478 2129 GIM_Try, /*On fail goto*//*Label 122*/ 3535, // Rule ID 3851 // 2130 GIM_CheckFeatures, GIFBS_HasNEON, 2131 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2132 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 2133 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, 2134 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 2135 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2136 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2138 GIM_CheckIsSafeToFold, /*InsnID*/1, 2139 // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd) => (MLAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 2140 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i16, 2141 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2142 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 2143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 2144 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 2145 GIR_EraseFromParent, /*InsnID*/0, 2146 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2147 // GIR_Coverage, 3851, 2148 GIR_Done, 2149 // Label 122: @3535 2150 GIM_Try, /*On fail goto*//*Label 123*/ 3592, // Rule ID 939 // 2151 GIM_CheckFeatures, GIFBS_HasNEON, 2152 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2153 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2154 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 2155 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, 2156 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 2157 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2158 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2159 GIM_CheckIsSafeToFold, /*InsnID*/1, 2160 // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (MLAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 2161 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i16, 2162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 2164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 2165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 2166 GIR_EraseFromParent, /*InsnID*/0, 2167 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2168 // GIR_Coverage, 939, 2169 GIR_Done, 2170 // Label 123: @3592 2171 GIM_Try, /*On fail goto*//*Label 124*/ 3611, // Rule ID 763 // 2172 GIM_CheckFeatures, GIFBS_HasNEON, 2173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2175 // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (ADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 2176 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv4i16, 2177 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2178 // GIR_Coverage, 763, 2179 GIR_Done, 2180 // Label 124: @3611 2181 GIM_Reject, 2182 // Label 113: @3612 2183 GIM_Reject, 2184 // Label 55: @3613 2185 GIM_Try, /*On fail goto*//*Label 125*/ 5085, 2186 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 2187 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 2188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 2189 GIM_Try, /*On fail goto*//*Label 126*/ 3704, // Rule ID 3911 // 2190 GIM_CheckFeatures, GIFBS_HasNEON, 2191 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2192 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 2193 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, 2194 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 2195 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, 2196 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, 2197 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, 2198 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, 2199 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, 2200 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2201 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 2202 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2203 GIM_CheckIsSafeToFold, /*InsnID*/1, 2204 GIM_CheckIsSafeToFold, /*InsnID*/2, 2205 // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 270:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd) => (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 2206 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32, 2207 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2208 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 2209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn 2210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm 2211 GIR_EraseFromParent, /*InsnID*/0, 2212 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2213 // GIR_Coverage, 3911, 2214 GIR_Done, 2215 // Label 126: @3704 2216 GIM_Try, /*On fail goto*//*Label 127*/ 3781, // Rule ID 3929 // 2217 GIM_CheckFeatures, GIFBS_HasNEON, 2218 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2219 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 2220 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, 2221 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 2222 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, 2223 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, 2224 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, 2225 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, 2226 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, 2227 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2228 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 2229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2230 GIM_CheckIsSafeToFold, /*InsnID*/1, 2231 GIM_CheckIsSafeToFold, /*InsnID*/2, 2232 // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 328:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd) => (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 2233 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32, 2234 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2235 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 2236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn 2237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm 2238 GIR_EraseFromParent, /*InsnID*/0, 2239 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2240 // GIR_Coverage, 3929, 2241 GIR_Done, 2242 // Label 127: @3781 2243 GIM_Try, /*On fail goto*//*Label 128*/ 3858, // Rule ID 1266 // 2244 GIM_CheckFeatures, GIFBS_HasNEON, 2245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 2246 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2247 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 2248 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, 2249 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 2250 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, 2251 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, 2252 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, 2253 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, 2254 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, 2255 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2256 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 2257 GIM_CheckIsSafeToFold, /*InsnID*/1, 2258 GIM_CheckIsSafeToFold, /*InsnID*/2, 2259 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 270:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))) => (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 2260 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32, 2261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2262 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 2263 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn 2264 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm 2265 GIR_EraseFromParent, /*InsnID*/0, 2266 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2267 // GIR_Coverage, 1266, 2268 GIR_Done, 2269 // Label 128: @3858 2270 GIM_Try, /*On fail goto*//*Label 129*/ 3935, // Rule ID 1332 // 2271 GIM_CheckFeatures, GIFBS_HasNEON, 2272 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 2273 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2274 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 2275 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, 2276 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 2277 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, 2278 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, 2279 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, 2280 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, 2281 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, 2282 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2283 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 2284 GIM_CheckIsSafeToFold, /*InsnID*/1, 2285 GIM_CheckIsSafeToFold, /*InsnID*/2, 2286 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 328:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))) => (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 2287 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32, 2288 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2289 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 2290 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn 2291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm 2292 GIR_EraseFromParent, /*InsnID*/0, 2293 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2294 // GIR_Coverage, 1332, 2295 GIR_Done, 2296 // Label 129: @3935 2297 GIM_Try, /*On fail goto*//*Label 130*/ 3999, // Rule ID 3860 // 2298 GIM_CheckFeatures, GIFBS_HasNEON, 2299 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2300 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2301 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 2302 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, 2303 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 2304 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, 2305 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2306 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 2307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2308 GIM_CheckIsSafeToFold, /*InsnID*/1, 2309 // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 270:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd) => (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 2310 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32, 2311 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2312 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 2313 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 2315 GIR_EraseFromParent, /*InsnID*/0, 2316 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2317 // GIR_Coverage, 3860, 2318 GIR_Done, 2319 // Label 130: @3999 2320 GIM_Try, /*On fail goto*//*Label 131*/ 4063, // Rule ID 3866 // 2321 GIM_CheckFeatures, GIFBS_HasNEON, 2322 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2323 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2324 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 2325 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, 2326 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 2327 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, 2328 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2329 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 2330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2331 GIM_CheckIsSafeToFold, /*InsnID*/1, 2332 // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 328:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd) => (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 2333 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32, 2334 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2335 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 2336 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2337 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 2338 GIR_EraseFromParent, /*InsnID*/0, 2339 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2340 // GIR_Coverage, 3866, 2341 GIR_Done, 2342 // Label 131: @4063 2343 GIM_Try, /*On fail goto*//*Label 132*/ 4127, // Rule ID 3923 // 2344 GIM_CheckFeatures, GIFBS_HasNEON, 2345 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2346 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2347 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 2348 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, 2349 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 2350 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, 2351 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2352 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 2353 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2354 GIM_CheckIsSafeToFold, /*InsnID*/1, 2355 // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 287:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd) => (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 2356 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_v4i32, 2357 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2358 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 2359 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2360 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 2361 GIR_EraseFromParent, /*InsnID*/0, 2362 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2363 // GIR_Coverage, 3923, 2364 GIR_Done, 2365 // Label 132: @4127 2366 GIM_Try, /*On fail goto*//*Label 133*/ 4191, // Rule ID 3941 // 2367 GIM_CheckFeatures, GIFBS_HasNEON, 2368 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2369 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2370 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 2371 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, 2372 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 2373 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, 2374 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2375 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 2376 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2377 GIM_CheckIsSafeToFold, /*InsnID*/1, 2378 // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 341:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd) => (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 2379 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_v4i32, 2380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 2382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 2384 GIR_EraseFromParent, /*InsnID*/0, 2385 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2386 // GIR_Coverage, 3941, 2387 GIR_Done, 2388 // Label 133: @4191 2389 GIM_Try, /*On fail goto*//*Label 134*/ 4243, // Rule ID 3840 // 2390 GIM_CheckFeatures, GIFBS_HasNEON, 2391 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2392 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2393 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 2394 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, 2395 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 2396 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2398 GIM_CheckIsSafeToFold, /*InsnID*/1, 2399 // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 271:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd) => (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn) 2400 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32, 2401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 2403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2404 GIR_EraseFromParent, /*InsnID*/0, 2405 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2406 // GIR_Coverage, 3840, 2407 GIR_Done, 2408 // Label 134: @4243 2409 GIM_Try, /*On fail goto*//*Label 135*/ 4295, // Rule ID 3846 // 2410 GIM_CheckFeatures, GIFBS_HasNEON, 2411 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2412 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2413 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 2414 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, 2415 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 2416 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2418 GIM_CheckIsSafeToFold, /*InsnID*/1, 2419 // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 329:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd) => (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn) 2420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i16_v4i32, 2421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2422 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 2423 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2424 GIR_EraseFromParent, /*InsnID*/0, 2425 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2426 // GIR_Coverage, 3846, 2427 GIR_Done, 2428 // Label 135: @4295 2429 GIM_Try, /*On fail goto*//*Label 136*/ 4359, // Rule ID 962 // 2430 GIM_CheckFeatures, GIFBS_HasNEON, 2431 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 2432 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2433 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2434 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 2435 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, 2436 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 2437 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, 2438 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2439 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 2440 GIM_CheckIsSafeToFold, /*InsnID*/1, 2441 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 270:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 2442 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32, 2443 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2444 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 2445 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 2447 GIR_EraseFromParent, /*InsnID*/0, 2448 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2449 // GIR_Coverage, 962, 2450 GIR_Done, 2451 // Label 136: @4359 2452 GIM_Try, /*On fail goto*//*Label 137*/ 4423, // Rule ID 1073 // 2453 GIM_CheckFeatures, GIFBS_HasNEON, 2454 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 2455 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2456 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2457 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 2458 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, 2459 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 2460 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, 2461 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2462 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 2463 GIM_CheckIsSafeToFold, /*InsnID*/1, 2464 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 328:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 2465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32, 2466 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2467 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 2468 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2469 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 2470 GIR_EraseFromParent, /*InsnID*/0, 2471 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2472 // GIR_Coverage, 1073, 2473 GIR_Done, 2474 // Label 137: @4423 2475 GIM_Try, /*On fail goto*//*Label 138*/ 4487, // Rule ID 1290 // 2476 GIM_CheckFeatures, GIFBS_HasNEON, 2477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 2478 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2479 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2480 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 2481 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, 2482 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 2483 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, 2484 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2485 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 2486 GIM_CheckIsSafeToFold, /*InsnID*/1, 2487 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 287:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 2488 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_v4i32, 2489 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2490 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 2491 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2492 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 2493 GIR_EraseFromParent, /*InsnID*/0, 2494 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2495 // GIR_Coverage, 1290, 2496 GIR_Done, 2497 // Label 138: @4487 2498 GIM_Try, /*On fail goto*//*Label 139*/ 4551, // Rule ID 1350 // 2499 GIM_CheckFeatures, GIFBS_HasNEON, 2500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 2501 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2502 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2503 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 2504 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, 2505 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 2506 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, 2507 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2508 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 2509 GIM_CheckIsSafeToFold, /*InsnID*/1, 2510 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 341:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 2511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_v4i32, 2512 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2513 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 2514 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2515 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 2516 GIR_EraseFromParent, /*InsnID*/0, 2517 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2518 // GIR_Coverage, 1350, 2519 GIR_Done, 2520 // Label 139: @4551 2521 GIM_Try, /*On fail goto*//*Label 140*/ 4603, // Rule ID 686 // 2522 GIM_CheckFeatures, GIFBS_HasNEON, 2523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 2524 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2525 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2526 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 2527 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, 2528 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 2529 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2530 GIM_CheckIsSafeToFold, /*InsnID*/1, 2531 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 271:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn) 2532 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32, 2533 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2534 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 2535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2536 GIR_EraseFromParent, /*InsnID*/0, 2537 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2538 // GIR_Coverage, 686, 2539 GIR_Done, 2540 // Label 140: @4603 2541 GIM_Try, /*On fail goto*//*Label 141*/ 4655, // Rule ID 730 // 2542 GIM_CheckFeatures, GIFBS_HasNEON, 2543 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 2544 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2545 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2546 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 2547 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, 2548 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 2549 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2550 GIM_CheckIsSafeToFold, /*InsnID*/1, 2551 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 329:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn) 2552 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i16_v4i32, 2553 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2554 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 2555 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2556 GIR_EraseFromParent, /*InsnID*/0, 2557 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2558 // GIR_Coverage, 730, 2559 GIR_Done, 2560 // Label 141: @4655 2561 GIM_Try, /*On fail goto*//*Label 142*/ 4713, // Rule ID 1278 // 2562 GIM_CheckFeatures, GIFBS_HasNEON, 2563 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2564 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 2565 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, 2566 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2567 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 2568 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, 2569 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, 2570 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2571 GIM_CheckIsSafeToFold, /*InsnID*/1, 2572 GIM_CheckIsSafeToFold, /*InsnID*/2, 2573 // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 2574 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv4i16_v4i32, 2575 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 2576 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 2577 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm 2578 GIR_EraseFromParent, /*InsnID*/0, 2579 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2580 // GIR_Coverage, 1278, 2581 GIR_Done, 2582 // Label 142: @4713 2583 GIM_Try, /*On fail goto*//*Label 143*/ 4771, // Rule ID 1338 // 2584 GIM_CheckFeatures, GIFBS_HasNEON, 2585 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2586 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 2587 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, 2588 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2589 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 2590 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, 2591 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, 2592 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2593 GIM_CheckIsSafeToFold, /*InsnID*/1, 2594 GIM_CheckIsSafeToFold, /*InsnID*/2, 2595 // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 2596 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv4i16_v4i32, 2597 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 2598 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 2599 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm 2600 GIR_EraseFromParent, /*InsnID*/0, 2601 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2602 // GIR_Coverage, 1338, 2603 GIR_Done, 2604 // Label 143: @4771 2605 GIM_Try, /*On fail goto*//*Label 144*/ 4828, // Rule ID 3854 // 2606 GIM_CheckFeatures, GIFBS_HasNEON, 2607 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2608 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 2609 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 2610 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 2611 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 2612 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2614 GIM_CheckIsSafeToFold, /*InsnID*/1, 2615 // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd) => (MLAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 2616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i32, 2617 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 2619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 2620 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 2621 GIR_EraseFromParent, /*InsnID*/0, 2622 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2623 // GIR_Coverage, 3854, 2624 GIR_Done, 2625 // Label 144: @4828 2626 GIM_Try, /*On fail goto*//*Label 145*/ 4873, // Rule ID 3917 // 2627 GIM_CheckFeatures, GIFBS_HasNEON, 2628 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2629 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 2630 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, 2631 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2632 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2633 GIM_CheckIsSafeToFold, /*InsnID*/1, 2634 // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn) => (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) 2635 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv4i16_v4i32, 2636 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 2637 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 2638 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 2639 GIR_EraseFromParent, /*InsnID*/0, 2640 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2641 // GIR_Coverage, 3917, 2642 GIR_Done, 2643 // Label 145: @4873 2644 GIM_Try, /*On fail goto*//*Label 146*/ 4918, // Rule ID 3935 // 2645 GIM_CheckFeatures, GIFBS_HasNEON, 2646 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2647 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 2648 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, 2649 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2651 GIM_CheckIsSafeToFold, /*InsnID*/1, 2652 // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn) => (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) 2653 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32, 2654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 2655 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 2656 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 2657 GIR_EraseFromParent, /*InsnID*/0, 2658 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2659 // GIR_Coverage, 3935, 2660 GIR_Done, 2661 // Label 146: @4918 2662 GIM_Try, /*On fail goto*//*Label 147*/ 4975, // Rule ID 942 // 2663 GIM_CheckFeatures, GIFBS_HasNEON, 2664 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 2665 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2666 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 2667 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 2668 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 2669 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 2670 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2671 GIM_CheckIsSafeToFold, /*InsnID*/1, 2672 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (MLAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 2673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv4i32, 2674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 2676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 2677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 2678 GIR_EraseFromParent, /*InsnID*/0, 2679 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2680 // GIR_Coverage, 942, 2681 GIR_Done, 2682 // Label 147: @4975 2683 GIM_Try, /*On fail goto*//*Label 148*/ 5020, // Rule ID 1284 // 2684 GIM_CheckFeatures, GIFBS_HasNEON, 2685 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 2686 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2687 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 2688 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, 2689 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2690 GIM_CheckIsSafeToFold, /*InsnID*/1, 2691 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) 2692 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv4i16_v4i32, 2693 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 2694 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 2695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 2696 GIR_EraseFromParent, /*InsnID*/0, 2697 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2698 // GIR_Coverage, 1284, 2699 GIR_Done, 2700 // Label 148: @5020 2701 GIM_Try, /*On fail goto*//*Label 149*/ 5065, // Rule ID 1344 // 2702 GIM_CheckFeatures, GIFBS_HasNEON, 2703 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 2704 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2705 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 2706 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, 2707 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2708 GIM_CheckIsSafeToFold, /*InsnID*/1, 2709 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) 2710 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32, 2711 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 2712 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 2713 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 2714 GIR_EraseFromParent, /*InsnID*/0, 2715 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2716 // GIR_Coverage, 1344, 2717 GIR_Done, 2718 // Label 149: @5065 2719 GIM_Try, /*On fail goto*//*Label 150*/ 5084, // Rule ID 766 // 2720 GIM_CheckFeatures, GIFBS_HasNEON, 2721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 2722 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2723 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 2724 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv4i32, 2725 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2726 // GIR_Coverage, 766, 2727 GIR_Done, 2728 // Label 150: @5084 2729 GIM_Reject, 2730 // Label 125: @5085 2731 GIM_Reject, 2732 // Label 56: @5086 2733 GIM_Try, /*On fail goto*//*Label 151*/ 5490, 2734 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 2735 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 2736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 2737 GIM_Try, /*On fail goto*//*Label 152*/ 5164, // Rule ID 3855 // 2738 GIM_CheckFeatures, GIFBS_HasNEON, 2739 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2740 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2741 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 2742 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, 2743 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, 2744 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, 2745 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2746 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 2747 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2748 GIM_CheckIsSafeToFold, /*InsnID*/1, 2749 // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 270:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd) => (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 2750 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8, 2751 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 2753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2754 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 2755 GIR_EraseFromParent, /*InsnID*/0, 2756 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2757 // GIR_Coverage, 3855, 2758 GIR_Done, 2759 // Label 152: @5164 2760 GIM_Try, /*On fail goto*//*Label 153*/ 5228, // Rule ID 3861 // 2761 GIM_CheckFeatures, GIFBS_HasNEON, 2762 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2763 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2764 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 2765 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, 2766 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, 2767 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, 2768 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2769 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 2770 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2771 GIM_CheckIsSafeToFold, /*InsnID*/1, 2772 // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 328:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd) => (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 2773 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8, 2774 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2775 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 2776 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 2778 GIR_EraseFromParent, /*InsnID*/0, 2779 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2780 // GIR_Coverage, 3861, 2781 GIR_Done, 2782 // Label 153: @5228 2783 GIM_Try, /*On fail goto*//*Label 154*/ 5292, // Rule ID 957 // 2784 GIM_CheckFeatures, GIFBS_HasNEON, 2785 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2786 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2787 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2788 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 2789 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, 2790 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, 2791 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, 2792 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2793 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 2794 GIM_CheckIsSafeToFold, /*InsnID*/1, 2795 // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 270:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 2796 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8, 2797 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2798 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 2799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2800 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 2801 GIR_EraseFromParent, /*InsnID*/0, 2802 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2803 // GIR_Coverage, 957, 2804 GIR_Done, 2805 // Label 154: @5292 2806 GIM_Try, /*On fail goto*//*Label 155*/ 5356, // Rule ID 1068 // 2807 GIM_CheckFeatures, GIFBS_HasNEON, 2808 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2809 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2810 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 2811 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 2812 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, 2813 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, 2814 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, 2815 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2816 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 2817 GIM_CheckIsSafeToFold, /*InsnID*/1, 2818 // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 328:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 2819 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8, 2820 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2821 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 2822 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 2823 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 2824 GIR_EraseFromParent, /*InsnID*/0, 2825 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2826 // GIR_Coverage, 1068, 2827 GIR_Done, 2828 // Label 155: @5356 2829 GIM_Try, /*On fail goto*//*Label 156*/ 5413, // Rule ID 3849 // 2830 GIM_CheckFeatures, GIFBS_HasNEON, 2831 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2832 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 2833 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, 2834 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, 2835 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2836 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2838 GIM_CheckIsSafeToFold, /*InsnID*/1, 2839 // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd) => (MLAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 2840 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i8, 2841 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2842 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 2843 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 2844 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 2845 GIR_EraseFromParent, /*InsnID*/0, 2846 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2847 // GIR_Coverage, 3849, 2848 GIR_Done, 2849 // Label 156: @5413 2850 GIM_Try, /*On fail goto*//*Label 157*/ 5470, // Rule ID 937 // 2851 GIM_CheckFeatures, GIFBS_HasNEON, 2852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2853 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2854 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 2855 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, 2856 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, 2857 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2858 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2859 GIM_CheckIsSafeToFold, /*InsnID*/1, 2860 // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (MLAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 2861 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i8, 2862 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2863 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 2864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 2865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 2866 GIR_EraseFromParent, /*InsnID*/0, 2867 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2868 // GIR_Coverage, 937, 2869 GIR_Done, 2870 // Label 157: @5470 2871 GIM_Try, /*On fail goto*//*Label 158*/ 5489, // Rule ID 761 // 2872 GIM_CheckFeatures, GIFBS_HasNEON, 2873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 2874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2875 // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 2876 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv8i8, 2877 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2878 // GIR_Coverage, 761, 2879 GIR_Done, 2880 // Label 158: @5489 2881 GIM_Reject, 2882 // Label 151: @5490 2883 GIM_Reject, 2884 // Label 57: @5491 2885 GIM_Try, /*On fail goto*//*Label 159*/ 6963, 2886 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 2887 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 2888 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 2889 GIM_Try, /*On fail goto*//*Label 160*/ 5582, // Rule ID 3909 // 2890 GIM_CheckFeatures, GIFBS_HasNEON, 2891 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2892 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 2893 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, 2894 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 2895 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, 2896 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, 2897 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, 2898 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, 2899 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, 2900 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2901 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 2902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2903 GIM_CheckIsSafeToFold, /*InsnID*/1, 2904 GIM_CheckIsSafeToFold, /*InsnID*/2, 2905 // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 270:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd) => (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 2906 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16, 2907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 2909 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn 2910 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm 2911 GIR_EraseFromParent, /*InsnID*/0, 2912 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2913 // GIR_Coverage, 3909, 2914 GIR_Done, 2915 // Label 160: @5582 2916 GIM_Try, /*On fail goto*//*Label 161*/ 5659, // Rule ID 3927 // 2917 GIM_CheckFeatures, GIFBS_HasNEON, 2918 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2919 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 2920 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, 2921 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 2922 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, 2923 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, 2924 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, 2925 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, 2926 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, 2927 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2928 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 2929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 2930 GIM_CheckIsSafeToFold, /*InsnID*/1, 2931 GIM_CheckIsSafeToFold, /*InsnID*/2, 2932 // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 328:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd) => (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 2933 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16, 2934 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2935 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 2936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn 2937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm 2938 GIR_EraseFromParent, /*InsnID*/0, 2939 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2940 // GIR_Coverage, 3927, 2941 GIR_Done, 2942 // Label 161: @5659 2943 GIM_Try, /*On fail goto*//*Label 162*/ 5736, // Rule ID 1264 // 2944 GIM_CheckFeatures, GIFBS_HasNEON, 2945 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 2946 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2947 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 2948 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, 2949 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 2950 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, 2951 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, 2952 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, 2953 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, 2954 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, 2955 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2956 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 2957 GIM_CheckIsSafeToFold, /*InsnID*/1, 2958 GIM_CheckIsSafeToFold, /*InsnID*/2, 2959 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 270:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))) => (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 2960 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16, 2961 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2962 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 2963 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn 2964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm 2965 GIR_EraseFromParent, /*InsnID*/0, 2966 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2967 // GIR_Coverage, 1264, 2968 GIR_Done, 2969 // Label 162: @5736 2970 GIM_Try, /*On fail goto*//*Label 163*/ 5813, // Rule ID 1330 // 2971 GIM_CheckFeatures, GIFBS_HasNEON, 2972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 2973 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2974 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 2975 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, 2976 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 2977 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, 2978 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, 2979 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, 2980 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, 2981 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, 2982 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 2983 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 2984 GIM_CheckIsSafeToFold, /*InsnID*/1, 2985 GIM_CheckIsSafeToFold, /*InsnID*/2, 2986 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 328:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))) => (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 2987 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16, 2988 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 2990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn 2991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm 2992 GIR_EraseFromParent, /*InsnID*/0, 2993 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2994 // GIR_Coverage, 1330, 2995 GIR_Done, 2996 // Label 163: @5813 2997 GIM_Try, /*On fail goto*//*Label 164*/ 5877, // Rule ID 3858 // 2998 GIM_CheckFeatures, GIFBS_HasNEON, 2999 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3000 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 3001 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 3002 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, 3003 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 3004 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, 3005 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3006 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 3007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3008 GIM_CheckIsSafeToFold, /*InsnID*/1, 3009 // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 270:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd) => (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 3010 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16, 3011 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3012 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 3013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 3014 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 3015 GIR_EraseFromParent, /*InsnID*/0, 3016 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3017 // GIR_Coverage, 3858, 3018 GIR_Done, 3019 // Label 164: @5877 3020 GIM_Try, /*On fail goto*//*Label 165*/ 5941, // Rule ID 3864 // 3021 GIM_CheckFeatures, GIFBS_HasNEON, 3022 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3023 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 3024 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 3025 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, 3026 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 3027 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, 3028 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3029 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 3030 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3031 GIM_CheckIsSafeToFold, /*InsnID*/1, 3032 // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 328:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd) => (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 3033 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16, 3034 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3035 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 3036 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 3037 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 3038 GIR_EraseFromParent, /*InsnID*/0, 3039 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3040 // GIR_Coverage, 3864, 3041 GIR_Done, 3042 // Label 165: @5941 3043 GIM_Try, /*On fail goto*//*Label 166*/ 6005, // Rule ID 3921 // 3044 GIM_CheckFeatures, GIFBS_HasNEON, 3045 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3046 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 3047 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 3048 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, 3049 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, 3050 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, 3051 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 3052 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 3053 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3054 GIM_CheckIsSafeToFold, /*InsnID*/1, 3055 // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 287:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd) => (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 3056 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv8i8_v8i16, 3057 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3058 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 3059 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 3060 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 3061 GIR_EraseFromParent, /*InsnID*/0, 3062 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3063 // GIR_Coverage, 3921, 3064 GIR_Done, 3065 // Label 166: @6005 3066 GIM_Try, /*On fail goto*//*Label 167*/ 6069, // Rule ID 3939 // 3067 GIM_CheckFeatures, GIFBS_HasNEON, 3068 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3069 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 3070 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 3071 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, 3072 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, 3073 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, 3074 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 3075 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 3076 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3077 GIM_CheckIsSafeToFold, /*InsnID*/1, 3078 // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 341:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd) => (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 3079 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv8i8_v8i16, 3080 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3081 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 3082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 3083 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 3084 GIR_EraseFromParent, /*InsnID*/0, 3085 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3086 // GIR_Coverage, 3939, 3087 GIR_Done, 3088 // Label 167: @6069 3089 GIM_Try, /*On fail goto*//*Label 168*/ 6121, // Rule ID 3838 // 3090 GIM_CheckFeatures, GIFBS_HasNEON, 3091 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3092 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 3093 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 3094 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, 3095 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, 3096 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3097 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3098 GIM_CheckIsSafeToFold, /*InsnID*/1, 3099 // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 271:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd) => (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn) 3100 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16, 3101 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3102 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 3103 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 3104 GIR_EraseFromParent, /*InsnID*/0, 3105 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3106 // GIR_Coverage, 3838, 3107 GIR_Done, 3108 // Label 168: @6121 3109 GIM_Try, /*On fail goto*//*Label 169*/ 6173, // Rule ID 3844 // 3110 GIM_CheckFeatures, GIFBS_HasNEON, 3111 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3112 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 3113 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 3114 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, 3115 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, 3116 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3117 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3118 GIM_CheckIsSafeToFold, /*InsnID*/1, 3119 // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 329:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd) => (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn) 3120 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16, 3121 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3122 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 3123 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 3124 GIR_EraseFromParent, /*InsnID*/0, 3125 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3126 // GIR_Coverage, 3844, 3127 GIR_Done, 3128 // Label 169: @6173 3129 GIM_Try, /*On fail goto*//*Label 170*/ 6237, // Rule ID 960 // 3130 GIM_CheckFeatures, GIFBS_HasNEON, 3131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 3132 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3133 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 3134 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 3135 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, 3136 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 3137 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, 3138 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3139 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 3140 GIM_CheckIsSafeToFold, /*InsnID*/1, 3141 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 270:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 3142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16, 3143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3144 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 3145 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 3146 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 3147 GIR_EraseFromParent, /*InsnID*/0, 3148 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3149 // GIR_Coverage, 960, 3150 GIR_Done, 3151 // Label 170: @6237 3152 GIM_Try, /*On fail goto*//*Label 171*/ 6301, // Rule ID 1071 // 3153 GIM_CheckFeatures, GIFBS_HasNEON, 3154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 3155 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3156 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 3157 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 3158 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, 3159 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 3160 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, 3161 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3162 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 3163 GIM_CheckIsSafeToFold, /*InsnID*/1, 3164 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 328:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 3165 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16, 3166 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3167 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 3168 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 3169 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 3170 GIR_EraseFromParent, /*InsnID*/0, 3171 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3172 // GIR_Coverage, 1071, 3173 GIR_Done, 3174 // Label 171: @6301 3175 GIM_Try, /*On fail goto*//*Label 172*/ 6365, // Rule ID 1288 // 3176 GIM_CheckFeatures, GIFBS_HasNEON, 3177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 3178 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3179 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 3180 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 3181 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, 3182 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, 3183 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, 3184 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 3185 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 3186 GIM_CheckIsSafeToFold, /*InsnID*/1, 3187 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 287:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 3188 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv8i8_v8i16, 3189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3190 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 3191 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 3192 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 3193 GIR_EraseFromParent, /*InsnID*/0, 3194 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3195 // GIR_Coverage, 1288, 3196 GIR_Done, 3197 // Label 172: @6365 3198 GIM_Try, /*On fail goto*//*Label 173*/ 6429, // Rule ID 1348 // 3199 GIM_CheckFeatures, GIFBS_HasNEON, 3200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 3201 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3202 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 3203 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 3204 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, 3205 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, 3206 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, 3207 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 3208 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 3209 GIM_CheckIsSafeToFold, /*InsnID*/1, 3210 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 341:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 3211 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv8i8_v8i16, 3212 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3213 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 3214 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 3215 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 3216 GIR_EraseFromParent, /*InsnID*/0, 3217 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3218 // GIR_Coverage, 1348, 3219 GIR_Done, 3220 // Label 173: @6429 3221 GIM_Try, /*On fail goto*//*Label 174*/ 6481, // Rule ID 684 // 3222 GIM_CheckFeatures, GIFBS_HasNEON, 3223 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 3224 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3225 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 3226 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 3227 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, 3228 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, 3229 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3230 GIM_CheckIsSafeToFold, /*InsnID*/1, 3231 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 271:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)) => (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn) 3232 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16, 3233 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3234 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 3235 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 3236 GIR_EraseFromParent, /*InsnID*/0, 3237 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3238 // GIR_Coverage, 684, 3239 GIR_Done, 3240 // Label 174: @6481 3241 GIM_Try, /*On fail goto*//*Label 175*/ 6533, // Rule ID 728 // 3242 GIM_CheckFeatures, GIFBS_HasNEON, 3243 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 3244 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3245 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 3246 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, 3247 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, 3248 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, 3249 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3250 GIM_CheckIsSafeToFold, /*InsnID*/1, 3251 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 329:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)) => (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn) 3252 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16, 3253 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3254 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 3255 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 3256 GIR_EraseFromParent, /*InsnID*/0, 3257 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3258 // GIR_Coverage, 728, 3259 GIR_Done, 3260 // Label 175: @6533 3261 GIM_Try, /*On fail goto*//*Label 176*/ 6591, // Rule ID 1276 // 3262 GIM_CheckFeatures, GIFBS_HasNEON, 3263 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3264 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 3265 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, 3266 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 3267 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 3268 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, 3269 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, 3270 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 3271 GIM_CheckIsSafeToFold, /*InsnID*/1, 3272 GIM_CheckIsSafeToFold, /*InsnID*/2, 3273 // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 3274 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv8i8_v8i16, 3275 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 3276 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 3277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm 3278 GIR_EraseFromParent, /*InsnID*/0, 3279 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3280 // GIR_Coverage, 1276, 3281 GIR_Done, 3282 // Label 176: @6591 3283 GIM_Try, /*On fail goto*//*Label 177*/ 6649, // Rule ID 1336 // 3284 GIM_CheckFeatures, GIFBS_HasNEON, 3285 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3286 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 3287 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, 3288 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 3289 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 3290 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, 3291 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, 3292 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 3293 GIM_CheckIsSafeToFold, /*InsnID*/1, 3294 GIM_CheckIsSafeToFold, /*InsnID*/2, 3295 // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 3296 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv8i8_v8i16, 3297 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 3298 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 3299 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm 3300 GIR_EraseFromParent, /*InsnID*/0, 3301 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3302 // GIR_Coverage, 1336, 3303 GIR_Done, 3304 // Label 177: @6649 3305 GIM_Try, /*On fail goto*//*Label 178*/ 6706, // Rule ID 3852 // 3306 GIM_CheckFeatures, GIFBS_HasNEON, 3307 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3308 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 3309 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, 3310 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 3311 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 3312 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3314 GIM_CheckIsSafeToFold, /*InsnID*/1, 3315 // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd) => (MLAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 3316 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i16, 3317 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3318 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 3319 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 3320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 3321 GIR_EraseFromParent, /*InsnID*/0, 3322 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3323 // GIR_Coverage, 3852, 3324 GIR_Done, 3325 // Label 178: @6706 3326 GIM_Try, /*On fail goto*//*Label 179*/ 6751, // Rule ID 3915 // 3327 GIM_CheckFeatures, GIFBS_HasNEON, 3328 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3329 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 3330 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, 3331 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 3332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3333 GIM_CheckIsSafeToFold, /*InsnID*/1, 3334 // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn) => (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) 3335 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv8i8_v8i16, 3336 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 3337 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 3338 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 3339 GIR_EraseFromParent, /*InsnID*/0, 3340 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3341 // GIR_Coverage, 3915, 3342 GIR_Done, 3343 // Label 179: @6751 3344 GIM_Try, /*On fail goto*//*Label 180*/ 6796, // Rule ID 3933 // 3345 GIM_CheckFeatures, GIFBS_HasNEON, 3346 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3347 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 3348 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, 3349 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 3350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3351 GIM_CheckIsSafeToFold, /*InsnID*/1, 3352 // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn) => (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) 3353 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16, 3354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 3355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 3356 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 3357 GIR_EraseFromParent, /*InsnID*/0, 3358 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3359 // GIR_Coverage, 3933, 3360 GIR_Done, 3361 // Label 180: @6796 3362 GIM_Try, /*On fail goto*//*Label 181*/ 6853, // Rule ID 940 // 3363 GIM_CheckFeatures, GIFBS_HasNEON, 3364 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 3365 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3366 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 3367 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, 3368 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 3369 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 3370 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3371 GIM_CheckIsSafeToFold, /*InsnID*/1, 3372 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (MLAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 3373 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv8i16, 3374 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3375 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 3376 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 3377 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 3378 GIR_EraseFromParent, /*InsnID*/0, 3379 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3380 // GIR_Coverage, 940, 3381 GIR_Done, 3382 // Label 181: @6853 3383 GIM_Try, /*On fail goto*//*Label 182*/ 6898, // Rule ID 1282 // 3384 GIM_CheckFeatures, GIFBS_HasNEON, 3385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 3386 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3387 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 3388 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, 3389 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 3390 GIM_CheckIsSafeToFold, /*InsnID*/1, 3391 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) 3392 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv8i8_v8i16, 3393 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 3394 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 3395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 3396 GIR_EraseFromParent, /*InsnID*/0, 3397 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3398 // GIR_Coverage, 1282, 3399 GIR_Done, 3400 // Label 182: @6898 3401 GIM_Try, /*On fail goto*//*Label 183*/ 6943, // Rule ID 1342 // 3402 GIM_CheckFeatures, GIFBS_HasNEON, 3403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 3404 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3405 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 3406 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, 3407 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 3408 GIM_CheckIsSafeToFold, /*InsnID*/1, 3409 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) 3410 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16, 3411 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 3412 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 3413 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 3414 GIR_EraseFromParent, /*InsnID*/0, 3415 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3416 // GIR_Coverage, 1342, 3417 GIR_Done, 3418 // Label 183: @6943 3419 GIM_Try, /*On fail goto*//*Label 184*/ 6962, // Rule ID 764 // 3420 GIM_CheckFeatures, GIFBS_HasNEON, 3421 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 3422 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3423 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 3424 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv8i16, 3425 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3426 // GIR_Coverage, 764, 3427 GIR_Done, 3428 // Label 184: @6962 3429 GIM_Reject, 3430 // Label 159: @6963 3431 GIM_Reject, 3432 // Label 58: @6964 3433 GIM_Try, /*On fail goto*//*Label 185*/ 7368, 3434 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 3435 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 3436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 3437 GIM_Try, /*On fail goto*//*Label 186*/ 7042, // Rule ID 3856 // 3438 GIM_CheckFeatures, GIFBS_HasNEON, 3439 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3440 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 3441 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 3442 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, 3443 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, 3444 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, 3445 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3446 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 3447 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3448 GIM_CheckIsSafeToFold, /*InsnID*/1, 3449 // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 270:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd) => (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 3450 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8, 3451 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3452 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 3453 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 3454 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 3455 GIR_EraseFromParent, /*InsnID*/0, 3456 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3457 // GIR_Coverage, 3856, 3458 GIR_Done, 3459 // Label 186: @7042 3460 GIM_Try, /*On fail goto*//*Label 187*/ 7106, // Rule ID 3862 // 3461 GIM_CheckFeatures, GIFBS_HasNEON, 3462 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3463 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 3464 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 3465 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, 3466 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, 3467 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, 3468 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3469 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 3470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3471 GIM_CheckIsSafeToFold, /*InsnID*/1, 3472 // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 328:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd) => (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 3473 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8, 3474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 3476 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 3477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 3478 GIR_EraseFromParent, /*InsnID*/0, 3479 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3480 // GIR_Coverage, 3862, 3481 GIR_Done, 3482 // Label 187: @7106 3483 GIM_Try, /*On fail goto*//*Label 188*/ 7170, // Rule ID 958 // 3484 GIM_CheckFeatures, GIFBS_HasNEON, 3485 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 3486 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3487 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 3488 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 3489 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, 3490 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, 3491 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, 3492 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3493 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 3494 GIM_CheckIsSafeToFold, /*InsnID*/1, 3495 // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 270:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)) => (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 3496 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8, 3497 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3498 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 3499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 3500 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 3501 GIR_EraseFromParent, /*InsnID*/0, 3502 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3503 // GIR_Coverage, 958, 3504 GIR_Done, 3505 // Label 188: @7170 3506 GIM_Try, /*On fail goto*//*Label 189*/ 7234, // Rule ID 1069 // 3507 GIM_CheckFeatures, GIFBS_HasNEON, 3508 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 3509 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3510 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 3511 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 3512 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, 3513 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, 3514 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, 3515 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3516 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 3517 GIM_CheckIsSafeToFold, /*InsnID*/1, 3518 // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 328:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)) => (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 3519 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8, 3520 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3521 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 3522 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 3523 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 3524 GIR_EraseFromParent, /*InsnID*/0, 3525 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3526 // GIR_Coverage, 1069, 3527 GIR_Done, 3528 // Label 189: @7234 3529 GIM_Try, /*On fail goto*//*Label 190*/ 7291, // Rule ID 3850 // 3530 GIM_CheckFeatures, GIFBS_HasNEON, 3531 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3532 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 3533 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, 3534 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, 3535 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 3536 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3538 GIM_CheckIsSafeToFold, /*InsnID*/1, 3539 // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd) => (MLAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 3540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv16i8, 3541 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 3543 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 3544 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 3545 GIR_EraseFromParent, /*InsnID*/0, 3546 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3547 // GIR_Coverage, 3850, 3548 GIR_Done, 3549 // Label 190: @7291 3550 GIM_Try, /*On fail goto*//*Label 191*/ 7348, // Rule ID 938 // 3551 GIM_CheckFeatures, GIFBS_HasNEON, 3552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 3553 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3554 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 3555 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, 3556 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, 3557 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 3558 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3559 GIM_CheckIsSafeToFold, /*InsnID*/1, 3560 // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)) => (MLAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 3561 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLAv16i8, 3562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3563 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 3564 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 3565 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 3566 GIR_EraseFromParent, /*InsnID*/0, 3567 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3568 // GIR_Coverage, 938, 3569 GIR_Done, 3570 // Label 191: @7348 3571 GIM_Try, /*On fail goto*//*Label 192*/ 7367, // Rule ID 762 // 3572 GIM_CheckFeatures, GIFBS_HasNEON, 3573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 3574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 3575 // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 3576 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv16i8, 3577 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3578 // GIR_Coverage, 762, 3579 GIR_Done, 3580 // Label 192: @7367 3581 GIM_Reject, 3582 // Label 185: @7368 3583 GIM_Reject, 3584 // Label 59: @7369 3585 GIM_Reject, 3586 // Label 1: @7370 3587 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 202*/ 9950, 3588 /*GILLT_s32*//*Label 193*/ 7386, 3589 /*GILLT_s64*//*Label 194*/ 7506, 0, 3590 /*GILLT_v2s32*//*Label 195*/ 8377, 3591 /*GILLT_v2s64*//*Label 196*/ 8465, 3592 /*GILLT_v4s16*//*Label 197*/ 8834, 3593 /*GILLT_v4s32*//*Label 198*/ 8922, 3594 /*GILLT_v8s8*//*Label 199*/ 9348, 3595 /*GILLT_v8s16*//*Label 200*/ 9436, 3596 /*GILLT_v16s8*//*Label 201*/ 9862, 3597 // Label 193: @7386 3598 GIM_Try, /*On fail goto*//*Label 203*/ 7505, 3599 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 3600 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 3602 GIM_Try, /*On fail goto*//*Label 204*/ 7454, // Rule ID 1872 // 3603 GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, 3604 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3605 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 3606 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3607 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3608 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 3609 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 3610 GIM_CheckIsSafeToFold, /*InsnID*/1, 3611 // (sub:{ *:[i32] } 0:{ *:[i32] }, (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)) => (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] }) 3612 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr, 3613 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 3614 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 3615 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 3616 GIR_AddRegister, /*InsnID*/0, AArch64::WZR, 3617 GIR_EraseFromParent, /*InsnID*/0, 3618 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3619 // GIR_Coverage, 1872, 3620 GIR_Done, 3621 // Label 204: @7454 3622 GIM_Try, /*On fail goto*//*Label 205*/ 7484, // Rule ID 1838 // 3623 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID, 3624 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32, 3625 // (sub:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) => (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) 3626 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWri, 3627 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 3628 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 3629 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm 3630 GIR_EraseFromParent, /*InsnID*/0, 3631 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3632 // GIR_Coverage, 1838, 3633 GIR_Done, 3634 // Label 205: @7484 3635 GIM_Try, /*On fail goto*//*Label 206*/ 7504, // Rule ID 1840 // 3636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 3637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 3638 // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (SUBSWrr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 3639 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBSWrr, 3640 GIR_AddImplicitDef, /*InsnID*/0, AArch64::NZCV, 3641 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3642 // GIR_Coverage, 1840, 3643 GIR_Done, 3644 // Label 206: @7504 3645 GIM_Reject, 3646 // Label 203: @7505 3647 GIM_Reject, 3648 // Label 194: @7506 3649 GIM_Try, /*On fail goto*//*Label 207*/ 8376, 3650 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 3651 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3652 GIM_Try, /*On fail goto*//*Label 208*/ 7611, // Rule ID 1883 // 3653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 3654 GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, 3655 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3656 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 3657 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3658 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3659 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 3660 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, 3661 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 3662 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 3663 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] 3664 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, 3665 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, 3666 // MIs[3] Operand 1 3667 // No operand predicates 3668 GIM_CheckIsSafeToFold, /*InsnID*/1, 3669 GIM_CheckIsSafeToFold, /*InsnID*/2, 3670 GIM_CheckIsSafeToFold, /*InsnID*/3, 3671 // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C)) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] }) 3672 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 3673 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, 3674 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3675 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C 3676 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3677 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr, 3678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 3679 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn 3680 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3681 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, 3682 GIR_EraseFromParent, /*InsnID*/0, 3683 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3684 // GIR_Coverage, 1883, 3685 GIR_Done, 3686 // Label 208: @7611 3687 GIM_Try, /*On fail goto*//*Label 209*/ 7706, // Rule ID 1884 // 3688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 3689 GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, 3690 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3691 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 3692 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3693 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3694 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 3695 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, 3696 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 3697 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 3698 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] 3699 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, 3700 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, 3701 // MIs[3] Operand 1 3702 // No operand predicates 3703 GIM_CheckIsSafeToFold, /*InsnID*/1, 3704 GIM_CheckIsSafeToFold, /*InsnID*/2, 3705 GIM_CheckIsSafeToFold, /*InsnID*/3, 3706 // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C)) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] }) 3707 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 3708 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, 3709 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3710 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C 3711 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3712 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr, 3713 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 3714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn 3715 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3716 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, 3717 GIR_EraseFromParent, /*InsnID*/0, 3718 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3719 // GIR_Coverage, 1884, 3720 GIR_Done, 3721 // Label 209: @7706 3722 GIM_Try, /*On fail goto*//*Label 210*/ 7790, // Rule ID 1878 // 3723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 3724 GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, 3725 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3726 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 3727 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3728 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3729 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 3730 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, 3731 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 3732 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 3733 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] 3734 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT, 3735 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, 3736 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 3737 GIM_CheckIsSafeToFold, /*InsnID*/1, 3738 GIM_CheckIsSafeToFold, /*InsnID*/2, 3739 GIM_CheckIsSafeToFold, /*InsnID*/3, 3740 // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] }) 3741 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr, 3742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 3743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn 3744 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm 3745 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, 3746 GIR_EraseFromParent, /*InsnID*/0, 3747 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3748 // GIR_Coverage, 1878, 3749 GIR_Done, 3750 // Label 210: @7790 3751 GIM_Try, /*On fail goto*//*Label 211*/ 7874, // Rule ID 1879 // 3752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 3753 GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, 3754 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3755 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 3756 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3757 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3758 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 3759 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, 3760 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 3761 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 3762 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] 3763 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, 3764 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, 3765 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 3766 GIM_CheckIsSafeToFold, /*InsnID*/1, 3767 GIM_CheckIsSafeToFold, /*InsnID*/2, 3768 GIM_CheckIsSafeToFold, /*InsnID*/3, 3769 // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] }) 3770 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr, 3771 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 3772 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn 3773 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm 3774 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, 3775 GIR_EraseFromParent, /*InsnID*/0, 3776 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3777 // GIR_Coverage, 1879, 3778 GIR_Done, 3779 // Label 211: @7874 3780 GIM_Try, /*On fail goto*//*Label 212*/ 7970, // Rule ID 1889 // 3781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 3782 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 3783 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3784 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 3785 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3786 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3787 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 3788 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, 3789 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 3790 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 3791 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] 3792 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, 3793 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, 3794 // MIs[3] Operand 1 3795 // No operand predicates 3796 GIM_CheckIsSafeToFold, /*InsnID*/1, 3797 GIM_CheckIsSafeToFold, /*InsnID*/2, 3798 GIM_CheckIsSafeToFold, /*InsnID*/3, 3799 // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C)) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) 3800 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 3801 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, 3802 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3803 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C 3804 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3805 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr, 3806 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 3807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn 3808 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3809 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra 3810 GIR_EraseFromParent, /*InsnID*/0, 3811 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3812 // GIR_Coverage, 1889, 3813 GIR_Done, 3814 // Label 212: @7970 3815 GIM_Try, /*On fail goto*//*Label 213*/ 8066, // Rule ID 1890 // 3816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 3817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 3818 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3819 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 3820 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3821 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3822 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 3823 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, 3824 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 3825 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 3826 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] 3827 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, 3828 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, 3829 // MIs[3] Operand 1 3830 // No operand predicates 3831 GIM_CheckIsSafeToFold, /*InsnID*/1, 3832 GIM_CheckIsSafeToFold, /*InsnID*/2, 3833 GIM_CheckIsSafeToFold, /*InsnID*/3, 3834 // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C)) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) 3835 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 3836 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, 3837 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3838 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C 3839 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3840 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr, 3841 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 3842 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn 3843 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3844 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra 3845 GIR_EraseFromParent, /*InsnID*/0, 3846 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3847 // GIR_Coverage, 1890, 3848 GIR_Done, 3849 // Label 213: @8066 3850 GIM_Try, /*On fail goto*//*Label 214*/ 8151, // Rule ID 66 // 3851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 3852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 3853 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3854 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 3855 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3856 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3857 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 3858 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, 3859 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 3860 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 3861 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] 3862 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT, 3863 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, 3864 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 3865 GIM_CheckIsSafeToFold, /*InsnID*/1, 3866 GIM_CheckIsSafeToFold, /*InsnID*/2, 3867 GIM_CheckIsSafeToFold, /*InsnID*/3, 3868 // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) 3869 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr, 3870 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 3871 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn 3872 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm 3873 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra 3874 GIR_EraseFromParent, /*InsnID*/0, 3875 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3876 // GIR_Coverage, 66, 3877 GIR_Done, 3878 // Label 214: @8151 3879 GIM_Try, /*On fail goto*//*Label 215*/ 8236, // Rule ID 68 // 3880 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 3881 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 3882 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3883 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 3884 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3885 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3886 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 3887 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, 3888 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 3889 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 3890 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] 3891 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, 3892 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, 3893 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 3894 GIM_CheckIsSafeToFold, /*InsnID*/1, 3895 GIM_CheckIsSafeToFold, /*InsnID*/2, 3896 GIM_CheckIsSafeToFold, /*InsnID*/3, 3897 // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) 3898 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr, 3899 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 3900 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn 3901 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm 3902 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra 3903 GIR_EraseFromParent, /*InsnID*/0, 3904 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3905 // GIR_Coverage, 68, 3906 GIR_Done, 3907 // Label 215: @8236 3908 GIM_Try, /*On fail goto*//*Label 216*/ 8294, // Rule ID 1873 // 3909 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 3910 GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, 3911 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3912 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 3913 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3914 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3915 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 3916 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 3917 GIM_CheckIsSafeToFold, /*InsnID*/1, 3918 // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)) => (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] }) 3919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr, 3920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 3921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 3922 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 3923 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, 3924 GIR_EraseFromParent, /*InsnID*/0, 3925 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3926 // GIR_Coverage, 1873, 3927 GIR_Done, 3928 // Label 216: @8294 3929 GIM_Try, /*On fail goto*//*Label 217*/ 8328, // Rule ID 1839 // 3930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 3931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 3932 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64, 3933 // (sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) => (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) 3934 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXri, 3935 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 3936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 3937 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm 3938 GIR_EraseFromParent, /*InsnID*/0, 3939 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3940 // GIR_Coverage, 1839, 3941 GIR_Done, 3942 // Label 217: @8328 3943 GIM_Try, /*On fail goto*//*Label 218*/ 8351, // Rule ID 1223 // 3944 GIM_CheckFeatures, GIFBS_HasNEON, 3945 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 3946 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 3947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 3948 // (sub:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) 3949 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv1i64, 3950 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3951 // GIR_Coverage, 1223, 3952 GIR_Done, 3953 // Label 218: @8351 3954 GIM_Try, /*On fail goto*//*Label 219*/ 8375, // Rule ID 1841 // 3955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 3956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 3957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 3958 // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SUBSXrr:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) 3959 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBSXrr, 3960 GIR_AddImplicitDef, /*InsnID*/0, AArch64::NZCV, 3961 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3962 // GIR_Coverage, 1841, 3963 GIR_Done, 3964 // Label 219: @8375 3965 GIM_Reject, 3966 // Label 207: @8376 3967 GIM_Reject, 3968 // Label 195: @8377 3969 GIM_Try, /*On fail goto*//*Label 220*/ 8464, 3970 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 3971 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 3972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 3973 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 3974 GIM_Try, /*On fail goto*//*Label 221*/ 8448, // Rule ID 947 // 3975 GIM_CheckFeatures, GIFBS_HasNEON, 3976 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3977 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 3978 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, 3979 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 3980 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 3981 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 3982 GIM_CheckIsSafeToFold, /*InsnID*/1, 3983 // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (MLSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 3984 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv2i32, 3985 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3986 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 3987 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 3988 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 3989 GIR_EraseFromParent, /*InsnID*/0, 3990 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3991 // GIR_Coverage, 947, 3992 GIR_Done, 3993 // Label 221: @8448 3994 GIM_Try, /*On fail goto*//*Label 222*/ 8463, // Rule ID 1065 // 3995 GIM_CheckFeatures, GIFBS_HasNEON, 3996 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 3997 // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 3998 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv2i32, 3999 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4000 // GIR_Coverage, 1065, 4001 GIR_Done, 4002 // Label 222: @8463 4003 GIM_Reject, 4004 // Label 220: @8464 4005 GIM_Reject, 4006 // Label 196: @8465 4007 GIM_Try, /*On fail goto*//*Label 223*/ 8833, 4008 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 4009 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 4010 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 4011 GIM_Try, /*On fail goto*//*Label 224*/ 8543, // Rule ID 1298 // 4012 GIM_CheckFeatures, GIFBS_HasNEON, 4013 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4014 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4015 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 4016 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 4017 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, 4018 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 4019 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, 4020 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 4021 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 4022 GIM_CheckIsSafeToFold, /*InsnID*/1, 4023 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 287:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 4024 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv2i32_v2i64, 4025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 4027 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 4028 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 4029 GIR_EraseFromParent, /*InsnID*/0, 4030 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4031 // GIR_Coverage, 1298, 4032 GIR_Done, 4033 // Label 224: @8543 4034 GIM_Try, /*On fail goto*//*Label 225*/ 8607, // Rule ID 1358 // 4035 GIM_CheckFeatures, GIFBS_HasNEON, 4036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4037 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4038 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 4039 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 4040 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, 4041 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 4042 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, 4043 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 4044 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 4045 GIM_CheckIsSafeToFold, /*InsnID*/1, 4046 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 341:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (UMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 4047 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv2i32_v2i64, 4048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 4050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 4051 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 4052 GIR_EraseFromParent, /*InsnID*/0, 4053 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4054 // GIR_Coverage, 1358, 4055 GIR_Done, 4056 // Label 225: @8607 4057 GIM_Try, /*On fail goto*//*Label 226*/ 8665, // Rule ID 1322 // 4058 GIM_CheckFeatures, GIFBS_HasNEON, 4059 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4060 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 4061 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, 4062 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4063 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 4064 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, 4065 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, 4066 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4067 GIM_CheckIsSafeToFold, /*InsnID*/1, 4068 GIM_CheckIsSafeToFold, /*InsnID*/2, 4069 // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SSUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 4070 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv2i32_v2i64, 4071 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4072 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 4073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm 4074 GIR_EraseFromParent, /*InsnID*/0, 4075 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4076 // GIR_Coverage, 1322, 4077 GIR_Done, 4078 // Label 226: @8665 4079 GIM_Try, /*On fail goto*//*Label 227*/ 8723, // Rule ID 1370 // 4080 GIM_CheckFeatures, GIFBS_HasNEON, 4081 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4082 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 4083 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, 4084 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4085 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 4086 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, 4087 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, 4088 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4089 GIM_CheckIsSafeToFold, /*InsnID*/1, 4090 GIM_CheckIsSafeToFold, /*InsnID*/2, 4091 // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 4092 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv2i32_v2i64, 4093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 4095 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm 4096 GIR_EraseFromParent, /*InsnID*/0, 4097 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4098 // GIR_Coverage, 1370, 4099 GIR_Done, 4100 // Label 227: @8723 4101 GIM_Try, /*On fail goto*//*Label 228*/ 8768, // Rule ID 1328 // 4102 GIM_CheckFeatures, GIFBS_HasNEON, 4103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4104 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4105 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 4106 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, 4107 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4108 GIM_CheckIsSafeToFold, /*InsnID*/1, 4109 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SSUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) 4110 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv2i32_v2i64, 4111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4112 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 4113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 4114 GIR_EraseFromParent, /*InsnID*/0, 4115 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4116 // GIR_Coverage, 1328, 4117 GIR_Done, 4118 // Label 228: @8768 4119 GIM_Try, /*On fail goto*//*Label 229*/ 8813, // Rule ID 1376 // 4120 GIM_CheckFeatures, GIFBS_HasNEON, 4121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4122 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4123 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 4124 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, 4125 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4126 GIM_CheckIsSafeToFold, /*InsnID*/1, 4127 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) 4128 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv2i32_v2i64, 4129 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4130 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 4131 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 4132 GIR_EraseFromParent, /*InsnID*/0, 4133 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4134 // GIR_Coverage, 1376, 4135 GIR_Done, 4136 // Label 229: @8813 4137 GIM_Try, /*On fail goto*//*Label 230*/ 8832, // Rule ID 1067 // 4138 GIM_CheckFeatures, GIFBS_HasNEON, 4139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 4141 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) 4142 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv2i64, 4143 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4144 // GIR_Coverage, 1067, 4145 GIR_Done, 4146 // Label 230: @8832 4147 GIM_Reject, 4148 // Label 223: @8833 4149 GIM_Reject, 4150 // Label 197: @8834 4151 GIM_Try, /*On fail goto*//*Label 231*/ 8921, 4152 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 4153 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 4154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 4155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4156 GIM_Try, /*On fail goto*//*Label 232*/ 8905, // Rule ID 945 // 4157 GIM_CheckFeatures, GIFBS_HasNEON, 4158 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4159 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 4160 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, 4161 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 4162 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4163 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 4164 GIM_CheckIsSafeToFold, /*InsnID*/1, 4165 // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (MLSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 4166 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv4i16, 4167 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4168 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 4169 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 4170 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 4171 GIR_EraseFromParent, /*InsnID*/0, 4172 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4173 // GIR_Coverage, 945, 4174 GIR_Done, 4175 // Label 232: @8905 4176 GIM_Try, /*On fail goto*//*Label 233*/ 8920, // Rule ID 1063 // 4177 GIM_CheckFeatures, GIFBS_HasNEON, 4178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 4179 // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 4180 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv4i16, 4181 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4182 // GIR_Coverage, 1063, 4183 GIR_Done, 4184 // Label 233: @8920 4185 GIM_Reject, 4186 // Label 231: @8921 4187 GIM_Reject, 4188 // Label 198: @8922 4189 GIM_Try, /*On fail goto*//*Label 234*/ 9347, 4190 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 4191 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4192 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 4193 GIM_Try, /*On fail goto*//*Label 235*/ 9000, // Rule ID 1296 // 4194 GIM_CheckFeatures, GIFBS_HasNEON, 4195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4196 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4197 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 4198 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 4199 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, 4200 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 4201 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, 4202 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 4203 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 4204 GIM_CheckIsSafeToFold, /*InsnID*/1, 4205 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 287:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 4206 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv4i16_v4i32, 4207 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4208 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 4209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 4210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 4211 GIR_EraseFromParent, /*InsnID*/0, 4212 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4213 // GIR_Coverage, 1296, 4214 GIR_Done, 4215 // Label 235: @9000 4216 GIM_Try, /*On fail goto*//*Label 236*/ 9064, // Rule ID 1356 // 4217 GIM_CheckFeatures, GIFBS_HasNEON, 4218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4219 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4220 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 4221 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 4222 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, 4223 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 4224 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, 4225 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 4226 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 4227 GIM_CheckIsSafeToFold, /*InsnID*/1, 4228 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 341:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (UMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 4229 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv4i16_v4i32, 4230 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4231 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 4232 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 4233 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 4234 GIR_EraseFromParent, /*InsnID*/0, 4235 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4236 // GIR_Coverage, 1356, 4237 GIR_Done, 4238 // Label 236: @9064 4239 GIM_Try, /*On fail goto*//*Label 237*/ 9122, // Rule ID 1320 // 4240 GIM_CheckFeatures, GIFBS_HasNEON, 4241 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4242 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 4243 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, 4244 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4245 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 4246 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, 4247 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, 4248 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4249 GIM_CheckIsSafeToFold, /*InsnID*/1, 4250 GIM_CheckIsSafeToFold, /*InsnID*/2, 4251 // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SSUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 4252 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv4i16_v4i32, 4253 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4254 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 4255 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm 4256 GIR_EraseFromParent, /*InsnID*/0, 4257 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4258 // GIR_Coverage, 1320, 4259 GIR_Done, 4260 // Label 237: @9122 4261 GIM_Try, /*On fail goto*//*Label 238*/ 9180, // Rule ID 1368 // 4262 GIM_CheckFeatures, GIFBS_HasNEON, 4263 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4264 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 4265 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, 4266 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4267 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 4268 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, 4269 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, 4270 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4271 GIM_CheckIsSafeToFold, /*InsnID*/1, 4272 GIM_CheckIsSafeToFold, /*InsnID*/2, 4273 // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 4274 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv4i16_v4i32, 4275 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4276 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 4277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm 4278 GIR_EraseFromParent, /*InsnID*/0, 4279 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4280 // GIR_Coverage, 1368, 4281 GIR_Done, 4282 // Label 238: @9180 4283 GIM_Try, /*On fail goto*//*Label 239*/ 9237, // Rule ID 948 // 4284 GIM_CheckFeatures, GIFBS_HasNEON, 4285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4286 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4287 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 4288 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 4289 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 4290 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4291 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 4292 GIM_CheckIsSafeToFold, /*InsnID*/1, 4293 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (MLSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 4294 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv4i32, 4295 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4296 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 4297 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 4298 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 4299 GIR_EraseFromParent, /*InsnID*/0, 4300 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4301 // GIR_Coverage, 948, 4302 GIR_Done, 4303 // Label 239: @9237 4304 GIM_Try, /*On fail goto*//*Label 240*/ 9282, // Rule ID 1326 // 4305 GIM_CheckFeatures, GIFBS_HasNEON, 4306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4307 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4308 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 4309 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, 4310 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4311 GIM_CheckIsSafeToFold, /*InsnID*/1, 4312 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SSUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) 4313 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv4i16_v4i32, 4314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4315 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 4316 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 4317 GIR_EraseFromParent, /*InsnID*/0, 4318 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4319 // GIR_Coverage, 1326, 4320 GIR_Done, 4321 // Label 240: @9282 4322 GIM_Try, /*On fail goto*//*Label 241*/ 9327, // Rule ID 1374 // 4323 GIM_CheckFeatures, GIFBS_HasNEON, 4324 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4325 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4326 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 4327 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, 4328 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4329 GIM_CheckIsSafeToFold, /*InsnID*/1, 4330 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) 4331 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv4i16_v4i32, 4332 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 4334 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 4335 GIR_EraseFromParent, /*InsnID*/0, 4336 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4337 // GIR_Coverage, 1374, 4338 GIR_Done, 4339 // Label 241: @9327 4340 GIM_Try, /*On fail goto*//*Label 242*/ 9346, // Rule ID 1066 // 4341 GIM_CheckFeatures, GIFBS_HasNEON, 4342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4343 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 4344 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 4345 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv4i32, 4346 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4347 // GIR_Coverage, 1066, 4348 GIR_Done, 4349 // Label 242: @9346 4350 GIM_Reject, 4351 // Label 234: @9347 4352 GIM_Reject, 4353 // Label 199: @9348 4354 GIM_Try, /*On fail goto*//*Label 243*/ 9435, 4355 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 4356 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 4357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 4358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4359 GIM_Try, /*On fail goto*//*Label 244*/ 9419, // Rule ID 943 // 4360 GIM_CheckFeatures, GIFBS_HasNEON, 4361 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4362 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 4363 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, 4364 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, 4365 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4366 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 4367 GIM_CheckIsSafeToFold, /*InsnID*/1, 4368 // (sub:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (MLSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 4369 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv8i8, 4370 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4371 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 4372 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 4373 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 4374 GIR_EraseFromParent, /*InsnID*/0, 4375 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4376 // GIR_Coverage, 943, 4377 GIR_Done, 4378 // Label 244: @9419 4379 GIM_Try, /*On fail goto*//*Label 245*/ 9434, // Rule ID 1061 // 4380 GIM_CheckFeatures, GIFBS_HasNEON, 4381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 4382 // (sub:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 4383 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv8i8, 4384 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4385 // GIR_Coverage, 1061, 4386 GIR_Done, 4387 // Label 245: @9434 4388 GIM_Reject, 4389 // Label 243: @9435 4390 GIM_Reject, 4391 // Label 200: @9436 4392 GIM_Try, /*On fail goto*//*Label 246*/ 9861, 4393 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 4394 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 4395 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 4396 GIM_Try, /*On fail goto*//*Label 247*/ 9514, // Rule ID 1294 // 4397 GIM_CheckFeatures, GIFBS_HasNEON, 4398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4399 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4400 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 4401 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 4402 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, 4403 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, 4404 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, 4405 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 4406 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 4407 GIM_CheckIsSafeToFold, /*InsnID*/1, 4408 // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 287:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (SMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 4409 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv8i8_v8i16, 4410 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4411 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 4412 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 4413 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 4414 GIR_EraseFromParent, /*InsnID*/0, 4415 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4416 // GIR_Coverage, 1294, 4417 GIR_Done, 4418 // Label 247: @9514 4419 GIM_Try, /*On fail goto*//*Label 248*/ 9578, // Rule ID 1354 // 4420 GIM_CheckFeatures, GIFBS_HasNEON, 4421 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4422 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4423 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 4424 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 4425 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, 4426 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, 4427 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, 4428 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 4429 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 4430 GIM_CheckIsSafeToFold, /*InsnID*/1, 4431 // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 341:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (UMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 4432 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv8i8_v8i16, 4433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 4435 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 4436 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 4437 GIR_EraseFromParent, /*InsnID*/0, 4438 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4439 // GIR_Coverage, 1354, 4440 GIR_Done, 4441 // Label 248: @9578 4442 GIM_Try, /*On fail goto*//*Label 249*/ 9636, // Rule ID 1318 // 4443 GIM_CheckFeatures, GIFBS_HasNEON, 4444 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4445 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 4446 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, 4447 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4448 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 4449 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, 4450 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, 4451 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4452 GIM_CheckIsSafeToFold, /*InsnID*/1, 4453 GIM_CheckIsSafeToFold, /*InsnID*/2, 4454 // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SSUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 4455 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv8i8_v8i16, 4456 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 4458 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm 4459 GIR_EraseFromParent, /*InsnID*/0, 4460 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4461 // GIR_Coverage, 1318, 4462 GIR_Done, 4463 // Label 249: @9636 4464 GIM_Try, /*On fail goto*//*Label 250*/ 9694, // Rule ID 1366 // 4465 GIM_CheckFeatures, GIFBS_HasNEON, 4466 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4467 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 4468 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, 4469 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4470 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 4471 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, 4472 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, 4473 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4474 GIM_CheckIsSafeToFold, /*InsnID*/1, 4475 GIM_CheckIsSafeToFold, /*InsnID*/2, 4476 // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 4477 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv8i8_v8i16, 4478 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4479 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 4480 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm 4481 GIR_EraseFromParent, /*InsnID*/0, 4482 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4483 // GIR_Coverage, 1366, 4484 GIR_Done, 4485 // Label 250: @9694 4486 GIM_Try, /*On fail goto*//*Label 251*/ 9751, // Rule ID 946 // 4487 GIM_CheckFeatures, GIFBS_HasNEON, 4488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4489 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4490 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 4491 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, 4492 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 4493 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4494 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 4495 GIM_CheckIsSafeToFold, /*InsnID*/1, 4496 // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (MLSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 4497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv8i16, 4498 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 4500 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 4501 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 4502 GIR_EraseFromParent, /*InsnID*/0, 4503 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4504 // GIR_Coverage, 946, 4505 GIR_Done, 4506 // Label 251: @9751 4507 GIM_Try, /*On fail goto*//*Label 252*/ 9796, // Rule ID 1324 // 4508 GIM_CheckFeatures, GIFBS_HasNEON, 4509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4510 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4511 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 4512 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, 4513 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4514 GIM_CheckIsSafeToFold, /*InsnID*/1, 4515 // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SSUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) 4516 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv8i8_v8i16, 4517 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4518 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 4519 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 4520 GIR_EraseFromParent, /*InsnID*/0, 4521 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4522 // GIR_Coverage, 1324, 4523 GIR_Done, 4524 // Label 252: @9796 4525 GIM_Try, /*On fail goto*//*Label 253*/ 9841, // Rule ID 1372 // 4526 GIM_CheckFeatures, GIFBS_HasNEON, 4527 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4528 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4529 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 4530 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, 4531 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4532 GIM_CheckIsSafeToFold, /*InsnID*/1, 4533 // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) 4534 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv8i8_v8i16, 4535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4536 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 4537 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 4538 GIR_EraseFromParent, /*InsnID*/0, 4539 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4540 // GIR_Coverage, 1372, 4541 GIR_Done, 4542 // Label 253: @9841 4543 GIM_Try, /*On fail goto*//*Label 254*/ 9860, // Rule ID 1064 // 4544 GIM_CheckFeatures, GIFBS_HasNEON, 4545 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 4547 // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 4548 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv8i16, 4549 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4550 // GIR_Coverage, 1064, 4551 GIR_Done, 4552 // Label 254: @9860 4553 GIM_Reject, 4554 // Label 246: @9861 4555 GIM_Reject, 4556 // Label 201: @9862 4557 GIM_Try, /*On fail goto*//*Label 255*/ 9949, 4558 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 4559 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 4560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 4561 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4562 GIM_Try, /*On fail goto*//*Label 256*/ 9933, // Rule ID 944 // 4563 GIM_CheckFeatures, GIFBS_HasNEON, 4564 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4565 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 4566 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, 4567 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, 4568 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4569 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 4570 GIM_CheckIsSafeToFold, /*InsnID*/1, 4571 // (sub:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)) => (MLSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 4572 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MLSv16i8, 4573 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4574 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd 4575 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 4576 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 4577 GIR_EraseFromParent, /*InsnID*/0, 4578 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4579 // GIR_Coverage, 944, 4580 GIR_Done, 4581 // Label 256: @9933 4582 GIM_Try, /*On fail goto*//*Label 257*/ 9948, // Rule ID 1062 // 4583 GIM_CheckFeatures, GIFBS_HasNEON, 4584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 4585 // (sub:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 4586 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv16i8, 4587 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4588 // GIR_Coverage, 1062, 4589 GIR_Done, 4590 // Label 257: @9948 4591 GIM_Reject, 4592 // Label 255: @9949 4593 GIM_Reject, 4594 // Label 202: @9950 4595 GIM_Reject, 4596 // Label 2: @9951 4597 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 266*/ 10731, 4598 /*GILLT_s32*//*Label 258*/ 9967, 4599 /*GILLT_s64*//*Label 259*/ 10124, 0, 4600 /*GILLT_v2s32*//*Label 260*/ 10539, 0, 4601 /*GILLT_v4s16*//*Label 261*/ 10571, 4602 /*GILLT_v4s32*//*Label 262*/ 10603, 4603 /*GILLT_v8s8*//*Label 263*/ 10635, 4604 /*GILLT_v8s16*//*Label 264*/ 10667, 4605 /*GILLT_v16s8*//*Label 265*/ 10699, 4606 // Label 258: @9967 4607 GIM_Try, /*On fail goto*//*Label 267*/ 10123, 4608 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 4609 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4610 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 4611 GIM_Try, /*On fail goto*//*Label 268*/ 10035, // Rule ID 1874 // 4612 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4613 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 4614 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4615 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 4616 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, 4617 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 4618 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 4619 GIM_CheckIsSafeToFold, /*InsnID*/1, 4620 // (mul:{ *:[i32] } (sub:{ *:[i32] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rn), GPR32:{ *:[i32] }:$Rm) => (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] }) 4621 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr, 4622 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 4624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 4625 GIR_AddRegister, /*InsnID*/0, AArch64::WZR, 4626 GIR_EraseFromParent, /*InsnID*/0, 4627 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4628 // GIR_Coverage, 1874, 4629 GIR_Done, 4630 // Label 268: @10035 4631 GIM_Try, /*On fail goto*//*Label 269*/ 10089, // Rule ID 4025 // 4632 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 4633 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4634 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 4635 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4636 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 4637 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, 4638 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 4639 GIM_CheckIsSafeToFold, /*InsnID*/1, 4640 // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, (sub:{ *:[i32] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rn)) => (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] }) 4641 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr, 4642 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4643 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 4644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm 4645 GIR_AddRegister, /*InsnID*/0, AArch64::WZR, 4646 GIR_EraseFromParent, /*InsnID*/0, 4647 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4648 // GIR_Coverage, 4025, 4649 GIR_Done, 4650 // Label 269: @10089 4651 GIM_Try, /*On fail goto*//*Label 270*/ 10122, // Rule ID 1870 // 4652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 4653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 4654 // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (MADDWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] }) 4655 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MADDWrrr, 4656 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 4658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 4659 GIR_AddRegister, /*InsnID*/0, AArch64::WZR, 4660 GIR_EraseFromParent, /*InsnID*/0, 4661 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4662 // GIR_Coverage, 1870, 4663 GIR_Done, 4664 // Label 270: @10122 4665 GIM_Reject, 4666 // Label 267: @10123 4667 GIM_Reject, 4668 // Label 259: @10124 4669 GIM_Try, /*On fail goto*//*Label 271*/ 10538, 4670 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 4671 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 4673 GIM_Try, /*On fail goto*//*Label 272*/ 10192, // Rule ID 1875 // 4674 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4675 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 4676 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 4677 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 4678 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, 4679 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 4680 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 4681 GIM_CheckIsSafeToFold, /*InsnID*/1, 4682 // (mul:{ *:[i64] } (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rn), GPR64:{ *:[i64] }:$Rm) => (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] }) 4683 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr, 4684 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4685 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 4686 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 4687 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, 4688 GIR_EraseFromParent, /*InsnID*/0, 4689 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4690 // GIR_Coverage, 1875, 4691 GIR_Done, 4692 // Label 272: @10192 4693 GIM_Try, /*On fail goto*//*Label 273*/ 10246, // Rule ID 4026 // 4694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 4695 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4696 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 4697 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 4698 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 4699 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, 4700 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 4701 GIM_CheckIsSafeToFold, /*InsnID*/1, 4702 // (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rn)) => (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] }) 4703 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr, 4704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 4706 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm 4707 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, 4708 GIR_EraseFromParent, /*InsnID*/0, 4709 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4710 // GIR_Coverage, 4026, 4711 GIR_Done, 4712 // Label 273: @10246 4713 GIM_Try, /*On fail goto*//*Label 274*/ 10316, // Rule ID 1880 // 4714 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4715 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 4716 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4717 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 4718 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 4719 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 4720 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, 4721 // MIs[2] Operand 1 4722 // No operand predicates 4723 GIM_CheckIsSafeToFold, /*InsnID*/1, 4724 GIM_CheckIsSafeToFold, /*InsnID*/2, 4725 // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] }) 4726 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 4727 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, 4728 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4729 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GICR_renderTruncImm, // C 4730 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 4731 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, 4732 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4733 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 4734 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4735 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, 4736 GIR_EraseFromParent, /*InsnID*/0, 4737 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4738 // GIR_Coverage, 1880, 4739 GIR_Done, 4740 // Label 274: @10316 4741 GIM_Try, /*On fail goto*//*Label 275*/ 10386, // Rule ID 1881 // 4742 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4743 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 4744 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4745 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 4746 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 4747 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 4748 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, 4749 // MIs[2] Operand 1 4750 // No operand predicates 4751 GIM_CheckIsSafeToFold, /*InsnID*/1, 4752 GIM_CheckIsSafeToFold, /*InsnID*/2, 4753 // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] }) 4754 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 4755 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, 4756 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4757 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GICR_renderTruncImm, // C 4758 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 4759 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, 4760 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4761 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 4762 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4763 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, 4764 GIR_EraseFromParent, /*InsnID*/0, 4765 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4766 // GIR_Coverage, 1881, 4767 GIR_Done, 4768 // Label 275: @10386 4769 GIM_Try, /*On fail goto*//*Label 276*/ 10445, // Rule ID 1876 // 4770 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4771 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 4772 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4773 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 4774 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 4775 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, 4776 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 4777 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 4778 GIM_CheckIsSafeToFold, /*InsnID*/1, 4779 GIM_CheckIsSafeToFold, /*InsnID*/2, 4780 // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] }) 4781 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, 4782 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4783 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 4784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm 4785 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, 4786 GIR_EraseFromParent, /*InsnID*/0, 4787 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4788 // GIR_Coverage, 1876, 4789 GIR_Done, 4790 // Label 276: @10445 4791 GIM_Try, /*On fail goto*//*Label 277*/ 10504, // Rule ID 1877 // 4792 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4793 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 4794 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4795 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 4796 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 4797 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, 4798 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 4799 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 4800 GIM_CheckIsSafeToFold, /*InsnID*/1, 4801 GIM_CheckIsSafeToFold, /*InsnID*/2, 4802 // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] }) 4803 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, 4804 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4805 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 4806 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm 4807 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, 4808 GIR_EraseFromParent, /*InsnID*/0, 4809 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4810 // GIR_Coverage, 1877, 4811 GIR_Done, 4812 // Label 277: @10504 4813 GIM_Try, /*On fail goto*//*Label 278*/ 10537, // Rule ID 1871 // 4814 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 4815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 4816 // (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (MADDXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] }) 4817 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MADDXrrr, 4818 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 4819 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 4820 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 4821 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, 4822 GIR_EraseFromParent, /*InsnID*/0, 4823 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4824 // GIR_Coverage, 1871, 4825 GIR_Done, 4826 // Label 278: @10537 4827 GIM_Reject, 4828 // Label 271: @10538 4829 GIM_Reject, 4830 // Label 260: @10539 4831 GIM_Try, /*On fail goto*//*Label 279*/ 10570, // Rule ID 953 // 4832 GIM_CheckFeatures, GIFBS_HasNEON, 4833 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 4834 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 4835 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 4836 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 4838 // (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (MULv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 4839 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv2i32, 4840 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4841 // GIR_Coverage, 953, 4842 GIR_Done, 4843 // Label 279: @10570 4844 GIM_Reject, 4845 // Label 261: @10571 4846 GIM_Try, /*On fail goto*//*Label 280*/ 10602, // Rule ID 951 // 4847 GIM_CheckFeatures, GIFBS_HasNEON, 4848 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 4849 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 4850 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 4851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 4853 // (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (MULv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 4854 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv4i16, 4855 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4856 // GIR_Coverage, 951, 4857 GIR_Done, 4858 // Label 280: @10602 4859 GIM_Reject, 4860 // Label 262: @10603 4861 GIM_Try, /*On fail goto*//*Label 281*/ 10634, // Rule ID 954 // 4862 GIM_CheckFeatures, GIFBS_HasNEON, 4863 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 4864 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4865 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 4866 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4867 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 4868 // (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (MULv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 4869 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv4i32, 4870 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4871 // GIR_Coverage, 954, 4872 GIR_Done, 4873 // Label 281: @10634 4874 GIM_Reject, 4875 // Label 263: @10635 4876 GIM_Try, /*On fail goto*//*Label 282*/ 10666, // Rule ID 949 // 4877 GIM_CheckFeatures, GIFBS_HasNEON, 4878 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 4879 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 4880 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 4881 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 4882 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 4883 // (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (MULv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 4884 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv8i8, 4885 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4886 // GIR_Coverage, 949, 4887 GIR_Done, 4888 // Label 282: @10666 4889 GIM_Reject, 4890 // Label 264: @10667 4891 GIM_Try, /*On fail goto*//*Label 283*/ 10698, // Rule ID 952 // 4892 GIM_CheckFeatures, GIFBS_HasNEON, 4893 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 4894 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 4895 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 4896 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4897 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 4898 // (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (MULv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 4899 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv8i16, 4900 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4901 // GIR_Coverage, 952, 4902 GIR_Done, 4903 // Label 283: @10698 4904 GIM_Reject, 4905 // Label 265: @10699 4906 GIM_Try, /*On fail goto*//*Label 284*/ 10730, // Rule ID 950 // 4907 GIM_CheckFeatures, GIFBS_HasNEON, 4908 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 4909 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 4910 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 4911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 4912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 4913 // (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (MULv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 4914 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv16i8, 4915 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4916 // GIR_Coverage, 950, 4917 GIR_Done, 4918 // Label 284: @10730 4919 GIM_Reject, 4920 // Label 266: @10731 4921 GIM_Reject, 4922 // Label 3: @10732 4923 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 287*/ 10800, 4924 /*GILLT_s32*//*Label 285*/ 10740, 4925 /*GILLT_s64*//*Label 286*/ 10770, 4926 // Label 285: @10740 4927 GIM_Try, /*On fail goto*//*Label 288*/ 10769, // Rule ID 59 // 4928 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 4929 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 4931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 4932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 4933 // (sdiv:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (SDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 4934 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SDIVWr, 4935 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4936 // GIR_Coverage, 59, 4937 GIR_Done, 4938 // Label 288: @10769 4939 GIM_Reject, 4940 // Label 286: @10770 4941 GIM_Try, /*On fail goto*//*Label 289*/ 10799, // Rule ID 60 // 4942 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 4943 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4944 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 4945 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 4946 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 4947 // (sdiv:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) 4948 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SDIVXr, 4949 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4950 // GIR_Coverage, 60, 4951 GIR_Done, 4952 // Label 289: @10799 4953 GIM_Reject, 4954 // Label 287: @10800 4955 GIM_Reject, 4956 // Label 4: @10801 4957 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 292*/ 10869, 4958 /*GILLT_s32*//*Label 290*/ 10809, 4959 /*GILLT_s64*//*Label 291*/ 10839, 4960 // Label 290: @10809 4961 GIM_Try, /*On fail goto*//*Label 293*/ 10838, // Rule ID 57 // 4962 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 4963 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4964 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 4965 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 4966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 4967 // (udiv:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (UDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 4968 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UDIVWr, 4969 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4970 // GIR_Coverage, 57, 4971 GIR_Done, 4972 // Label 293: @10838 4973 GIM_Reject, 4974 // Label 291: @10839 4975 GIM_Try, /*On fail goto*//*Label 294*/ 10868, // Rule ID 58 // 4976 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 4977 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4978 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 4979 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 4980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 4981 // (udiv:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (UDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) 4982 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UDIVXr, 4983 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4984 // GIR_Coverage, 58, 4985 GIR_Done, 4986 // Label 294: @10868 4987 GIM_Reject, 4988 // Label 292: @10869 4989 GIM_Reject, 4990 // Label 5: @10870 4991 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 304*/ 11411, 4992 /*GILLT_s32*//*Label 295*/ 10886, 4993 /*GILLT_s64*//*Label 296*/ 11021, 0, 4994 /*GILLT_v2s32*//*Label 297*/ 11187, 4995 /*GILLT_v2s64*//*Label 298*/ 11219, 4996 /*GILLT_v4s16*//*Label 299*/ 11251, 4997 /*GILLT_v4s32*//*Label 300*/ 11283, 4998 /*GILLT_v8s8*//*Label 301*/ 11315, 4999 /*GILLT_v8s16*//*Label 302*/ 11347, 5000 /*GILLT_v16s8*//*Label 303*/ 11379, 5001 // Label 295: @10886 5002 GIM_Try, /*On fail goto*//*Label 305*/ 11020, 5003 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 5004 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 5006 GIM_Try, /*On fail goto*//*Label 306*/ 10951, // Rule ID 3797 // 5007 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5008 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5009 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5010 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5011 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 5012 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5013 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 5014 GIM_CheckIsSafeToFold, /*InsnID*/1, 5015 // (and:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (BICWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 5016 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICWrr, 5017 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5018 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 5019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 5020 GIR_EraseFromParent, /*InsnID*/0, 5021 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5022 // GIR_Coverage, 3797, 5023 GIR_Done, 5024 // Label 306: @10951 5025 GIM_Try, /*On fail goto*//*Label 307*/ 11002, // Rule ID 99 // 5026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 5027 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5028 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5029 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5030 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5031 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 5032 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5033 GIM_CheckIsSafeToFold, /*InsnID*/1, 5034 // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (BICWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 5035 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICWrr, 5036 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5037 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 5038 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 5039 GIR_EraseFromParent, /*InsnID*/0, 5040 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5041 // GIR_Coverage, 99, 5042 GIR_Done, 5043 // Label 307: @11002 5044 GIM_Try, /*On fail goto*//*Label 308*/ 11019, // Rule ID 95 // 5045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 5046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 5047 // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (ANDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 5048 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDWrr, 5049 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5050 // GIR_Coverage, 95, 5051 GIR_Done, 5052 // Label 308: @11019 5053 GIM_Reject, 5054 // Label 305: @11020 5055 GIM_Reject, 5056 // Label 296: @11021 5057 GIM_Try, /*On fail goto*//*Label 309*/ 11186, 5058 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 5059 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5060 GIM_Try, /*On fail goto*//*Label 310*/ 11086, // Rule ID 3798 // 5061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 5062 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5063 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5064 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 5065 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 5066 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 5067 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 5069 GIM_CheckIsSafeToFold, /*InsnID*/1, 5070 // (and:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (BICXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) 5071 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICXrr, 5072 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 5074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 5075 GIR_EraseFromParent, /*InsnID*/0, 5076 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5077 // GIR_Coverage, 3798, 5078 GIR_Done, 5079 // Label 310: @11086 5080 GIM_Try, /*On fail goto*//*Label 311*/ 11141, // Rule ID 100 // 5081 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 5082 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 5083 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5084 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5085 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 5086 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 5087 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 5088 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5089 GIM_CheckIsSafeToFold, /*InsnID*/1, 5090 // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] })) => (BICXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) 5091 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICXrr, 5092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 5094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 5095 GIR_EraseFromParent, /*InsnID*/0, 5096 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5097 // GIR_Coverage, 100, 5098 GIR_Done, 5099 // Label 311: @11141 5100 GIM_Try, /*On fail goto*//*Label 312*/ 11162, // Rule ID 96 // 5101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 5102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 5103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 5104 // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ANDXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) 5105 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDXrr, 5106 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5107 // GIR_Coverage, 96, 5108 GIR_Done, 5109 // Label 312: @11162 5110 GIM_Try, /*On fail goto*//*Label 313*/ 11185, // Rule ID 1766 // 5111 GIM_CheckFeatures, GIFBS_HasNEON, 5112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 5113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5114 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 5115 // (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) => (ANDv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) 5116 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv8i8, 5117 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5118 // GIR_Coverage, 1766, 5119 GIR_Done, 5120 // Label 313: @11185 5121 GIM_Reject, 5122 // Label 309: @11186 5123 GIM_Reject, 5124 // Label 297: @11187 5125 GIM_Try, /*On fail goto*//*Label 314*/ 11218, // Rule ID 1765 // 5126 GIM_CheckFeatures, GIFBS_HasNEON, 5127 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 5128 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 5129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 5130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 5132 // (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (ANDv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) 5133 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv8i8, 5134 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5135 // GIR_Coverage, 1765, 5136 GIR_Done, 5137 // Label 314: @11218 5138 GIM_Reject, 5139 // Label 298: @11219 5140 GIM_Try, /*On fail goto*//*Label 315*/ 11250, // Rule ID 1769 // 5141 GIM_CheckFeatures, GIFBS_HasNEON, 5142 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 5143 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 5144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 5145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 5146 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 5147 // (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (ANDv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) 5148 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv16i8, 5149 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5150 // GIR_Coverage, 1769, 5151 GIR_Done, 5152 // Label 315: @11250 5153 GIM_Reject, 5154 // Label 299: @11251 5155 GIM_Try, /*On fail goto*//*Label 316*/ 11282, // Rule ID 1764 // 5156 GIM_CheckFeatures, GIFBS_HasNEON, 5157 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 5158 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 5159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 5160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5161 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 5162 // (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (ANDv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) 5163 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv8i8, 5164 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5165 // GIR_Coverage, 1764, 5166 GIR_Done, 5167 // Label 316: @11282 5168 GIM_Reject, 5169 // Label 300: @11283 5170 GIM_Try, /*On fail goto*//*Label 317*/ 11314, // Rule ID 1768 // 5171 GIM_CheckFeatures, GIFBS_HasNEON, 5172 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 5173 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 5175 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 5176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 5177 // (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (ANDv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) 5178 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv16i8, 5179 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5180 // GIR_Coverage, 1768, 5181 GIR_Done, 5182 // Label 317: @11314 5183 GIM_Reject, 5184 // Label 301: @11315 5185 GIM_Try, /*On fail goto*//*Label 318*/ 11346, // Rule ID 1172 // 5186 GIM_CheckFeatures, GIFBS_HasNEON, 5187 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 5188 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 5189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 5190 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5191 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 5192 // (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ANDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 5193 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv8i8, 5194 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5195 // GIR_Coverage, 1172, 5196 GIR_Done, 5197 // Label 318: @11346 5198 GIM_Reject, 5199 // Label 302: @11347 5200 GIM_Try, /*On fail goto*//*Label 319*/ 11378, // Rule ID 1767 // 5201 GIM_CheckFeatures, GIFBS_HasNEON, 5202 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 5203 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5204 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 5205 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 5206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 5207 // (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (ANDv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) 5208 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv16i8, 5209 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5210 // GIR_Coverage, 1767, 5211 GIR_Done, 5212 // Label 319: @11378 5213 GIM_Reject, 5214 // Label 303: @11379 5215 GIM_Try, /*On fail goto*//*Label 320*/ 11410, // Rule ID 1173 // 5216 GIM_CheckFeatures, GIFBS_HasNEON, 5217 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 5218 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 5220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 5221 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 5222 // (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ANDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 5223 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv16i8, 5224 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5225 // GIR_Coverage, 1173, 5226 GIR_Done, 5227 // Label 320: @11410 5228 GIM_Reject, 5229 // Label 304: @11411 5230 GIM_Reject, 5231 // Label 6: @11412 5232 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 330*/ 11953, 5233 /*GILLT_s32*//*Label 321*/ 11428, 5234 /*GILLT_s64*//*Label 322*/ 11563, 0, 5235 /*GILLT_v2s32*//*Label 323*/ 11729, 5236 /*GILLT_v2s64*//*Label 324*/ 11761, 5237 /*GILLT_v4s16*//*Label 325*/ 11793, 5238 /*GILLT_v4s32*//*Label 326*/ 11825, 5239 /*GILLT_v8s8*//*Label 327*/ 11857, 5240 /*GILLT_v8s16*//*Label 328*/ 11889, 5241 /*GILLT_v16s8*//*Label 329*/ 11921, 5242 // Label 321: @11428 5243 GIM_Try, /*On fail goto*//*Label 331*/ 11562, 5244 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 5245 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 5247 GIM_Try, /*On fail goto*//*Label 332*/ 11493, // Rule ID 3817 // 5248 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5249 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5250 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5251 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5252 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 5253 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 5255 GIM_CheckIsSafeToFold, /*InsnID*/1, 5256 // (or:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (ORNWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 5257 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrr, 5258 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5259 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 5260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 5261 GIR_EraseFromParent, /*InsnID*/0, 5262 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5263 // GIR_Coverage, 3817, 5264 GIR_Done, 5265 // Label 332: @11493 5266 GIM_Try, /*On fail goto*//*Label 333*/ 11544, // Rule ID 111 // 5267 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 5268 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5269 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5270 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5271 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5272 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 5273 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5274 GIM_CheckIsSafeToFold, /*InsnID*/1, 5275 // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (ORNWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 5276 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrr, 5277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5278 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 5279 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 5280 GIR_EraseFromParent, /*InsnID*/0, 5281 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5282 // GIR_Coverage, 111, 5283 GIR_Done, 5284 // Label 333: @11544 5285 GIM_Try, /*On fail goto*//*Label 334*/ 11561, // Rule ID 115 // 5286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 5287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 5288 // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (ORRWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 5289 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRWrr, 5290 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5291 // GIR_Coverage, 115, 5292 GIR_Done, 5293 // Label 334: @11561 5294 GIM_Reject, 5295 // Label 331: @11562 5296 GIM_Reject, 5297 // Label 322: @11563 5298 GIM_Try, /*On fail goto*//*Label 335*/ 11728, 5299 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 5300 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5301 GIM_Try, /*On fail goto*//*Label 336*/ 11628, // Rule ID 3818 // 5302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 5303 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5304 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5305 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 5306 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 5307 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 5308 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 5310 GIM_CheckIsSafeToFold, /*InsnID*/1, 5311 // (or:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (ORNXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) 5312 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrr, 5313 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 5315 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 5316 GIR_EraseFromParent, /*InsnID*/0, 5317 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5318 // GIR_Coverage, 3818, 5319 GIR_Done, 5320 // Label 336: @11628 5321 GIM_Try, /*On fail goto*//*Label 337*/ 11683, // Rule ID 112 // 5322 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 5323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 5324 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5325 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5326 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 5327 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 5328 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 5329 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5330 GIM_CheckIsSafeToFold, /*InsnID*/1, 5331 // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] })) => (ORNXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) 5332 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrr, 5333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5334 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 5335 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 5336 GIR_EraseFromParent, /*InsnID*/0, 5337 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5338 // GIR_Coverage, 112, 5339 GIR_Done, 5340 // Label 337: @11683 5341 GIM_Try, /*On fail goto*//*Label 338*/ 11704, // Rule ID 116 // 5342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 5343 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 5344 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 5345 // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ORRXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) 5346 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRXrr, 5347 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5348 // GIR_Coverage, 116, 5349 GIR_Done, 5350 // Label 338: @11704 5351 GIM_Try, /*On fail goto*//*Label 339*/ 11727, // Rule ID 2393 // 5352 GIM_CheckFeatures, GIFBS_HasNEON, 5353 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 5354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 5356 // (or:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) => (ORRv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) 5357 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv8i8, 5358 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5359 // GIR_Coverage, 2393, 5360 GIR_Done, 5361 // Label 339: @11727 5362 GIM_Reject, 5363 // Label 335: @11728 5364 GIM_Reject, 5365 // Label 323: @11729 5366 GIM_Try, /*On fail goto*//*Label 340*/ 11760, // Rule ID 2392 // 5367 GIM_CheckFeatures, GIFBS_HasNEON, 5368 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 5369 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 5370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 5371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5372 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 5373 // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (ORRv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) 5374 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv8i8, 5375 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5376 // GIR_Coverage, 2392, 5377 GIR_Done, 5378 // Label 340: @11760 5379 GIM_Reject, 5380 // Label 324: @11761 5381 GIM_Try, /*On fail goto*//*Label 341*/ 11792, // Rule ID 2396 // 5382 GIM_CheckFeatures, GIFBS_HasNEON, 5383 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 5384 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 5385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 5386 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 5387 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 5388 // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (ORRv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) 5389 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv16i8, 5390 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5391 // GIR_Coverage, 2396, 5392 GIR_Done, 5393 // Label 341: @11792 5394 GIM_Reject, 5395 // Label 325: @11793 5396 GIM_Try, /*On fail goto*//*Label 342*/ 11824, // Rule ID 2391 // 5397 GIM_CheckFeatures, GIFBS_HasNEON, 5398 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 5399 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 5400 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 5401 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5402 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 5403 // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (ORRv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) 5404 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv8i8, 5405 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5406 // GIR_Coverage, 2391, 5407 GIR_Done, 5408 // Label 342: @11824 5409 GIM_Reject, 5410 // Label 326: @11825 5411 GIM_Try, /*On fail goto*//*Label 343*/ 11856, // Rule ID 2395 // 5412 GIM_CheckFeatures, GIFBS_HasNEON, 5413 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 5414 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 5416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 5417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 5418 // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (ORRv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) 5419 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv16i8, 5420 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5421 // GIR_Coverage, 2395, 5422 GIR_Done, 5423 // Label 343: @11856 5424 GIM_Reject, 5425 // Label 327: @11857 5426 GIM_Try, /*On fail goto*//*Label 344*/ 11888, // Rule ID 1184 // 5427 GIM_CheckFeatures, GIFBS_HasNEON, 5428 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 5429 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 5430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 5431 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5432 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 5433 // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ORRv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 5434 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv8i8, 5435 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5436 // GIR_Coverage, 1184, 5437 GIR_Done, 5438 // Label 344: @11888 5439 GIM_Reject, 5440 // Label 328: @11889 5441 GIM_Try, /*On fail goto*//*Label 345*/ 11920, // Rule ID 2394 // 5442 GIM_CheckFeatures, GIFBS_HasNEON, 5443 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 5444 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 5446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 5447 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 5448 // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (ORRv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) 5449 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv16i8, 5450 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5451 // GIR_Coverage, 2394, 5452 GIR_Done, 5453 // Label 345: @11920 5454 GIM_Reject, 5455 // Label 329: @11921 5456 GIM_Try, /*On fail goto*//*Label 346*/ 11952, // Rule ID 1185 // 5457 GIM_CheckFeatures, GIFBS_HasNEON, 5458 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 5459 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5460 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 5461 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 5462 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 5463 // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ORRv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 5464 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv16i8, 5465 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5466 // GIR_Coverage, 1185, 5467 GIR_Done, 5468 // Label 346: @11952 5469 GIM_Reject, 5470 // Label 330: @11953 5471 GIM_Reject, 5472 // Label 7: @11954 5473 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 356*/ 12663, 5474 /*GILLT_s32*//*Label 347*/ 11970, 5475 /*GILLT_s64*//*Label 348*/ 12185, 0, 5476 /*GILLT_v2s32*//*Label 349*/ 12439, 5477 /*GILLT_v2s64*//*Label 350*/ 12471, 5478 /*GILLT_v4s16*//*Label 351*/ 12503, 5479 /*GILLT_v4s32*//*Label 352*/ 12535, 5480 /*GILLT_v8s8*//*Label 353*/ 12567, 5481 /*GILLT_v8s16*//*Label 354*/ 12599, 5482 /*GILLT_v16s8*//*Label 355*/ 12631, 5483 // Label 347: @11970 5484 GIM_Try, /*On fail goto*//*Label 357*/ 12184, 5485 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 5486 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5487 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 5488 GIM_Try, /*On fail goto*//*Label 358*/ 12035, // Rule ID 3801 // 5489 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5490 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5491 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5492 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5493 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 5494 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5495 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 5496 GIM_CheckIsSafeToFold, /*InsnID*/1, 5497 // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rm) => (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 5498 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrr, 5499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5500 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 5501 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 5502 GIR_EraseFromParent, /*InsnID*/0, 5503 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5504 // GIR_Coverage, 3801, 5505 GIR_Done, 5506 // Label 358: @12035 5507 GIM_Try, /*On fail goto*//*Label 359*/ 12086, // Rule ID 103 // 5508 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5509 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5510 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5511 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5512 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 5513 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 5514 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 5515 GIM_CheckIsSafeToFold, /*InsnID*/1, 5516 // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm), -1:{ *:[i32] }) => (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 5517 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrr, 5518 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5519 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 5520 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 5521 GIR_EraseFromParent, /*InsnID*/0, 5522 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5523 // GIR_Coverage, 103, 5524 GIR_Done, 5525 // Label 359: @12086 5526 GIM_Try, /*On fail goto*//*Label 360*/ 12137, // Rule ID 3802 // 5527 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 5528 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5529 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5530 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5531 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5532 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 5533 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5534 GIM_CheckIsSafeToFold, /*InsnID*/1, 5535 // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] })) => (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 5536 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrr, 5537 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5538 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 5539 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm 5540 GIR_EraseFromParent, /*InsnID*/0, 5541 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5542 // GIR_Coverage, 3802, 5543 GIR_Done, 5544 // Label 360: @12137 5545 GIM_Try, /*On fail goto*//*Label 361*/ 12166, // Rule ID 1892 // 5546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 5547 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 5548 // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Wm, -1:{ *:[i32] }) => (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Wm) 5549 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrr, 5550 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5551 GIR_AddRegister, /*InsnID*/0, AArch64::WZR, 5552 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Wm 5553 GIR_EraseFromParent, /*InsnID*/0, 5554 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5555 // GIR_Coverage, 1892, 5556 GIR_Done, 5557 // Label 361: @12166 5558 GIM_Try, /*On fail goto*//*Label 362*/ 12183, // Rule ID 107 // 5559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 5560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 5561 // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (EORWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 5562 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORWrr, 5563 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5564 // GIR_Coverage, 107, 5565 GIR_Done, 5566 // Label 362: @12183 5567 GIM_Reject, 5568 // Label 357: @12184 5569 GIM_Reject, 5570 // Label 348: @12185 5571 GIM_Try, /*On fail goto*//*Label 363*/ 12438, 5572 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 5573 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5574 GIM_Try, /*On fail goto*//*Label 364*/ 12250, // Rule ID 3803 // 5575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 5576 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5577 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5578 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 5579 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 5580 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 5581 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5582 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 5583 GIM_CheckIsSafeToFold, /*InsnID*/1, 5584 // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rm) => (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) 5585 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrr, 5586 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5587 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 5588 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 5589 GIR_EraseFromParent, /*InsnID*/0, 5590 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5591 // GIR_Coverage, 3803, 5592 GIR_Done, 5593 // Label 364: @12250 5594 GIM_Try, /*On fail goto*//*Label 365*/ 12305, // Rule ID 104 // 5595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 5596 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5597 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5598 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 5599 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 5600 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 5601 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 5602 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 5603 GIM_CheckIsSafeToFold, /*InsnID*/1, 5604 // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm), -1:{ *:[i64] }) => (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) 5605 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrr, 5606 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5607 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 5608 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 5609 GIR_EraseFromParent, /*InsnID*/0, 5610 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5611 // GIR_Coverage, 104, 5612 GIR_Done, 5613 // Label 365: @12305 5614 GIM_Try, /*On fail goto*//*Label 366*/ 12360, // Rule ID 3804 // 5615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 5616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 5617 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5618 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5619 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 5620 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 5621 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 5622 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5623 GIM_CheckIsSafeToFold, /*InsnID*/1, 5624 // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] })) => (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) 5625 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrr, 5626 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5627 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 5628 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm 5629 GIR_EraseFromParent, /*InsnID*/0, 5630 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5631 // GIR_Coverage, 3804, 5632 GIR_Done, 5633 // Label 366: @12360 5634 GIM_Try, /*On fail goto*//*Label 367*/ 12393, // Rule ID 1893 // 5635 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 5636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 5637 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 5638 // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Xm, -1:{ *:[i64] }) => (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Xm) 5639 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrr, 5640 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5641 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, 5642 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Xm 5643 GIR_EraseFromParent, /*InsnID*/0, 5644 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5645 // GIR_Coverage, 1893, 5646 GIR_Done, 5647 // Label 367: @12393 5648 GIM_Try, /*On fail goto*//*Label 368*/ 12414, // Rule ID 108 // 5649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 5650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 5651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 5652 // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (EORXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) 5653 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORXrr, 5654 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5655 // GIR_Coverage, 108, 5656 GIR_Done, 5657 // Label 368: @12414 5658 GIM_Try, /*On fail goto*//*Label 369*/ 12437, // Rule ID 2381 // 5659 GIM_CheckFeatures, GIFBS_HasNEON, 5660 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 5661 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5662 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 5663 // (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) => (EORv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) 5664 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv8i8, 5665 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5666 // GIR_Coverage, 2381, 5667 GIR_Done, 5668 // Label 369: @12437 5669 GIM_Reject, 5670 // Label 363: @12438 5671 GIM_Reject, 5672 // Label 349: @12439 5673 GIM_Try, /*On fail goto*//*Label 370*/ 12470, // Rule ID 2380 // 5674 GIM_CheckFeatures, GIFBS_HasNEON, 5675 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 5676 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 5677 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 5678 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5679 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 5680 // (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (EORv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) 5681 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv8i8, 5682 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5683 // GIR_Coverage, 2380, 5684 GIR_Done, 5685 // Label 370: @12470 5686 GIM_Reject, 5687 // Label 350: @12471 5688 GIM_Try, /*On fail goto*//*Label 371*/ 12502, // Rule ID 2384 // 5689 GIM_CheckFeatures, GIFBS_HasNEON, 5690 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 5691 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 5692 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 5693 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 5694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 5695 // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (EORv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) 5696 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv16i8, 5697 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5698 // GIR_Coverage, 2384, 5699 GIR_Done, 5700 // Label 371: @12502 5701 GIM_Reject, 5702 // Label 351: @12503 5703 GIM_Try, /*On fail goto*//*Label 372*/ 12534, // Rule ID 2379 // 5704 GIM_CheckFeatures, GIFBS_HasNEON, 5705 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 5706 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 5707 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 5708 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 5710 // (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (EORv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) 5711 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv8i8, 5712 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5713 // GIR_Coverage, 2379, 5714 GIR_Done, 5715 // Label 372: @12534 5716 GIM_Reject, 5717 // Label 352: @12535 5718 GIM_Try, /*On fail goto*//*Label 373*/ 12566, // Rule ID 2383 // 5719 GIM_CheckFeatures, GIFBS_HasNEON, 5720 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 5721 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5722 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 5723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 5724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 5725 // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (EORv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) 5726 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv16i8, 5727 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5728 // GIR_Coverage, 2383, 5729 GIR_Done, 5730 // Label 373: @12566 5731 GIM_Reject, 5732 // Label 353: @12567 5733 GIM_Try, /*On fail goto*//*Label 374*/ 12598, // Rule ID 1180 // 5734 GIM_CheckFeatures, GIFBS_HasNEON, 5735 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 5736 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 5737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 5738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 5740 // (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (EORv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 5741 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv8i8, 5742 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5743 // GIR_Coverage, 1180, 5744 GIR_Done, 5745 // Label 374: @12598 5746 GIM_Reject, 5747 // Label 354: @12599 5748 GIM_Try, /*On fail goto*//*Label 375*/ 12630, // Rule ID 2382 // 5749 GIM_CheckFeatures, GIFBS_HasNEON, 5750 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 5751 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 5753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 5754 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 5755 // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (EORv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) 5756 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv16i8, 5757 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5758 // GIR_Coverage, 2382, 5759 GIR_Done, 5760 // Label 375: @12630 5761 GIM_Reject, 5762 // Label 355: @12631 5763 GIM_Try, /*On fail goto*//*Label 376*/ 12662, // Rule ID 1181 // 5764 GIM_CheckFeatures, GIFBS_HasNEON, 5765 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 5766 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5767 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 5768 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 5769 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 5770 // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (EORv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 5771 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv16i8, 5772 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5773 // GIR_Coverage, 1181, 5774 GIR_Done, 5775 // Label 376: @12662 5776 GIM_Reject, 5777 // Label 356: @12663 5778 GIM_Reject, 5779 // Label 8: @12664 5780 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 387*/ 20156, 5781 /*GILLT_s32*//*Label 377*/ 12680, 5782 /*GILLT_s64*//*Label 378*/ 12726, 5783 /*GILLT_s128*//*Label 379*/ 14302, 5784 /*GILLT_v2s32*//*Label 380*/ 14974, 5785 /*GILLT_v2s64*//*Label 381*/ 15869, 5786 /*GILLT_v4s16*//*Label 382*/ 16650, 5787 /*GILLT_v4s32*//*Label 383*/ 17545, 5788 /*GILLT_v8s8*//*Label 384*/ 18390, 5789 /*GILLT_v8s16*//*Label 385*/ 18863, 5790 /*GILLT_v16s8*//*Label 386*/ 19708, 5791 // Label 377: @12680 5792 GIM_Try, /*On fail goto*//*Label 388*/ 12725, 5793 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 5794 GIM_Try, /*On fail goto*//*Label 389*/ 12705, // Rule ID 3210 // 5795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 5796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 5797 // (bitconvert:{ *:[f32] } GPR32:{ *:[i32] }:$Xn) => (COPY_TO_REGCLASS:{ *:[f32] } GPR32:{ *:[i32] }:$Xn, FPR32:{ *:[i32] }) 5798 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 5799 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR32*/5, 5800 // GIR_Coverage, 3210, 5801 GIR_Done, 5802 // Label 389: @12705 5803 GIM_Try, /*On fail goto*//*Label 390*/ 12724, // Rule ID 3211 // 5804 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 5805 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 5806 // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Xn) => (COPY_TO_REGCLASS:{ *:[i32] } FPR32:{ *:[f32] }:$Xn, GPR32:{ *:[i32] }) 5807 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 5808 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/6, 5809 // GIR_Coverage, 3211, 5810 GIR_Done, 5811 // Label 390: @12724 5812 GIM_Reject, 5813 // Label 388: @12725 5814 GIM_Reject, 5815 // Label 378: @12726 5816 GIM_Try, /*On fail goto*//*Label 391*/ 12751, // Rule ID 3188 // 5817 GIM_CheckFeatures, GIFBS_IsLE, 5818 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 5819 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 5820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5821 // (bitconvert:{ *:[i64] } V64:{ *:[v8i8] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v8i8] }:$Vn, GPR64:{ *:[i32] }) 5822 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 5823 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/17, 5824 // GIR_Coverage, 3188, 5825 GIR_Done, 5826 // Label 391: @12751 5827 GIM_Try, /*On fail goto*//*Label 392*/ 12776, // Rule ID 3189 // 5828 GIM_CheckFeatures, GIFBS_IsLE, 5829 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 5830 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 5831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5832 // (bitconvert:{ *:[i64] } V64:{ *:[v4i16] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4i16] }:$Vn, GPR64:{ *:[i32] }) 5833 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 5834 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/17, 5835 // GIR_Coverage, 3189, 5836 GIR_Done, 5837 // Label 392: @12776 5838 GIM_Try, /*On fail goto*//*Label 393*/ 12801, // Rule ID 3190 // 5839 GIM_CheckFeatures, GIFBS_IsLE, 5840 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 5841 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 5842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5843 // (bitconvert:{ *:[i64] } V64:{ *:[v2i32] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2i32] }:$Vn, GPR64:{ *:[i32] }) 5844 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 5845 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/17, 5846 // GIR_Coverage, 3190, 5847 GIR_Done, 5848 // Label 393: @12801 5849 GIM_Try, /*On fail goto*//*Label 394*/ 12826, // Rule ID 3191 // 5850 GIM_CheckFeatures, GIFBS_IsLE, 5851 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 5852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 5853 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5854 // (bitconvert:{ *:[i64] } V64:{ *:[v4f16] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4f16] }:$Vn, GPR64:{ *:[i32] }) 5855 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 5856 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/17, 5857 // GIR_Coverage, 3191, 5858 GIR_Done, 5859 // Label 394: @12826 5860 GIM_Try, /*On fail goto*//*Label 395*/ 12851, // Rule ID 3192 // 5861 GIM_CheckFeatures, GIFBS_IsLE, 5862 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 5863 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 5864 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5865 // (bitconvert:{ *:[i64] } V64:{ *:[v2f32] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2f32] }:$Vn, GPR64:{ *:[i32] }) 5866 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 5867 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/17, 5868 // GIR_Coverage, 3192, 5869 GIR_Done, 5870 // Label 395: @12851 5871 GIM_Try, /*On fail goto*//*Label 396*/ 12876, // Rule ID 3193 // 5872 GIM_CheckFeatures, GIFBS_IsLE, 5873 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 5874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 5875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5876 // (bitconvert:{ *:[i64] } V64:{ *:[v1f64] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1f64] }:$Vn, GPR64:{ *:[i32] }) 5877 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 5878 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/17, 5879 // GIR_Coverage, 3193, 5880 GIR_Done, 5881 // Label 396: @12876 5882 GIM_Try, /*On fail goto*//*Label 397*/ 12924, // Rule ID 3199 // 5883 GIM_CheckFeatures, GIFBS_IsBE, 5884 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 5885 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 5886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5887 // (bitconvert:{ *:[i64] } V64:{ *:[v8i8] }:$Vn) => (REV64v8i8:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v8i8] }:$Vn, GPR64:{ *:[i32] })) 5888 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 5889 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 5890 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5891 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn 5892 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v8i8, 5894 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5895 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5896 GIR_EraseFromParent, /*InsnID*/0, 5897 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5898 // GIR_Coverage, 3199, 5899 GIR_Done, 5900 // Label 397: @12924 5901 GIM_Try, /*On fail goto*//*Label 398*/ 12972, // Rule ID 3200 // 5902 GIM_CheckFeatures, GIFBS_IsBE, 5903 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 5904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 5905 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5906 // (bitconvert:{ *:[i64] } V64:{ *:[v4i16] }:$Vn) => (REV64v4i16:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4i16] }:$Vn, GPR64:{ *:[i32] })) 5907 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 5908 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 5909 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5910 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn 5911 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5912 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, 5913 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5914 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5915 GIR_EraseFromParent, /*InsnID*/0, 5916 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5917 // GIR_Coverage, 3200, 5918 GIR_Done, 5919 // Label 398: @12972 5920 GIM_Try, /*On fail goto*//*Label 399*/ 13020, // Rule ID 3201 // 5921 GIM_CheckFeatures, GIFBS_IsBE, 5922 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 5923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 5924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5925 // (bitconvert:{ *:[i64] } V64:{ *:[v2i32] }:$Vn) => (REV64v2i32:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2i32] }:$Vn, GPR64:{ *:[i32] })) 5926 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 5927 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 5928 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5929 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn 5930 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5931 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32, 5932 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5933 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5934 GIR_EraseFromParent, /*InsnID*/0, 5935 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5936 // GIR_Coverage, 3201, 5937 GIR_Done, 5938 // Label 399: @13020 5939 GIM_Try, /*On fail goto*//*Label 400*/ 13068, // Rule ID 3202 // 5940 GIM_CheckFeatures, GIFBS_IsBE, 5941 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 5942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 5943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5944 // (bitconvert:{ *:[i64] } V64:{ *:[v4f16] }:$Vn) => (REV64v4i16:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4f16] }:$Vn, GPR64:{ *:[i32] })) 5945 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 5946 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 5947 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5948 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn 5949 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5950 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, 5951 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5952 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5953 GIR_EraseFromParent, /*InsnID*/0, 5954 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5955 // GIR_Coverage, 3202, 5956 GIR_Done, 5957 // Label 400: @13068 5958 GIM_Try, /*On fail goto*//*Label 401*/ 13116, // Rule ID 3203 // 5959 GIM_CheckFeatures, GIFBS_IsBE, 5960 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 5961 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 5962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 5963 // (bitconvert:{ *:[i64] } V64:{ *:[v2f32] }:$Vn) => (REV64v2i32:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2f32] }:$Vn, GPR64:{ *:[i32] })) 5964 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 5965 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 5966 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5967 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn 5968 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5969 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32, 5970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 5971 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5972 GIR_EraseFromParent, /*InsnID*/0, 5973 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5974 // GIR_Coverage, 3203, 5975 GIR_Done, 5976 // Label 401: @13116 5977 GIM_Try, /*On fail goto*//*Label 402*/ 13139, // Rule ID 3204 // 5978 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 5979 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 5980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 5981 // (bitconvert:{ *:[v1i64] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v1i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) 5982 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 5983 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 5984 // GIR_Coverage, 3204, 5985 GIR_Done, 5986 // Label 402: @13139 5987 GIM_Try, /*On fail goto*//*Label 403*/ 13162, // Rule ID 3205 // 5988 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 5989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 5990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 5991 // (bitconvert:{ *:[v1f64] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v1f64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) 5992 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 5993 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 5994 // GIR_Coverage, 3205, 5995 GIR_Done, 5996 // Label 403: @13162 5997 GIM_Try, /*On fail goto*//*Label 404*/ 13185, // Rule ID 3206 // 5998 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 5999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 6000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6001 // (bitconvert:{ *:[i64] } V64:{ *:[v1i64] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1i64] }:$Vn, GPR64:{ *:[i32] }) 6002 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 6003 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/17, 6004 // GIR_Coverage, 3206, 6005 GIR_Done, 6006 // Label 404: @13185 6007 GIM_Try, /*On fail goto*//*Label 405*/ 13208, // Rule ID 3212 // 6008 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6009 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6010 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 6011 // (bitconvert:{ *:[f64] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[f64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) 6012 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 6013 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6014 // GIR_Coverage, 3212, 6015 GIR_Done, 6016 // Label 405: @13208 6017 GIM_Try, /*On fail goto*//*Label 406*/ 13231, // Rule ID 3213 // 6018 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 6020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6021 // (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[i64] } FPR64:{ *:[f64] }:$Xn, GPR64:{ *:[i32] }) 6022 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 6023 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/17, 6024 // GIR_Coverage, 3213, 6025 GIR_Done, 6026 // Label 406: @13231 6027 GIM_Try, /*On fail goto*//*Label 407*/ 13254, // Rule ID 3214 // 6028 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 6030 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6031 // (bitconvert:{ *:[i64] } V64:{ *:[v1f64] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1f64] }:$Vn, GPR64:{ *:[i32] }) 6032 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 6033 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/17, 6034 // GIR_Coverage, 3214, 6035 GIR_Done, 6036 // Label 407: @13254 6037 GIM_Try, /*On fail goto*//*Label 408*/ 13288, // Rule ID 3215 // 6038 GIM_CheckFeatures, GIFBS_IsLE, 6039 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 6040 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6041 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6042 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v1i64] }:$src 6043 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6045 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6046 GIR_EraseFromParent, /*InsnID*/0, 6047 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6048 // GIR_Coverage, 3215, 6049 GIR_Done, 6050 // Label 408: @13288 6051 GIM_Try, /*On fail goto*//*Label 409*/ 13322, // Rule ID 3216 // 6052 GIM_CheckFeatures, GIFBS_IsLE, 6053 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 6054 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6056 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v1i64] }:$src 6057 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6058 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6059 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6060 GIR_EraseFromParent, /*InsnID*/0, 6061 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6062 // GIR_Coverage, 3216, 6063 GIR_Done, 6064 // Label 409: @13322 6065 GIM_Try, /*On fail goto*//*Label 410*/ 13356, // Rule ID 3217 // 6066 GIM_CheckFeatures, GIFBS_IsLE, 6067 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 6068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6070 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v1i64] }:$src 6071 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6072 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6074 GIR_EraseFromParent, /*InsnID*/0, 6075 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6076 // GIR_Coverage, 3217, 6077 GIR_Done, 6078 // Label 410: @13356 6079 GIM_Try, /*On fail goto*//*Label 411*/ 13390, // Rule ID 3218 // 6080 GIM_CheckFeatures, GIFBS_IsLE, 6081 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 6082 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6084 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v1i64] }:$src 6085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6087 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6088 GIR_EraseFromParent, /*InsnID*/0, 6089 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6090 // GIR_Coverage, 3218, 6091 GIR_Done, 6092 // Label 411: @13390 6093 GIM_Try, /*On fail goto*//*Label 412*/ 13424, // Rule ID 3219 // 6094 GIM_CheckFeatures, GIFBS_IsLE, 6095 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 6096 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6097 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6098 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v1i64] }:$src 6099 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6101 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6102 GIR_EraseFromParent, /*InsnID*/0, 6103 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6104 // GIR_Coverage, 3219, 6105 GIR_Done, 6106 // Label 412: @13424 6107 GIM_Try, /*On fail goto*//*Label 413*/ 13447, // Rule ID 3220 // 6108 GIM_CheckFeatures, GIFBS_IsBE, 6109 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 6110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6112 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src) => (REV64v2i32:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src) 6113 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, 6114 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6115 // GIR_Coverage, 3220, 6116 GIR_Done, 6117 // Label 413: @13447 6118 GIM_Try, /*On fail goto*//*Label 414*/ 13470, // Rule ID 3221 // 6119 GIM_CheckFeatures, GIFBS_IsBE, 6120 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 6121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6122 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6123 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src) => (REV64v4i16:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src) 6124 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, 6125 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6126 // GIR_Coverage, 3221, 6127 GIR_Done, 6128 // Label 414: @13470 6129 GIM_Try, /*On fail goto*//*Label 415*/ 13493, // Rule ID 3222 // 6130 GIM_CheckFeatures, GIFBS_IsBE, 6131 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 6132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6134 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src) => (REV64v8i8:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src) 6135 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, 6136 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6137 // GIR_Coverage, 3222, 6138 GIR_Done, 6139 // Label 415: @13493 6140 GIM_Try, /*On fail goto*//*Label 416*/ 13516, // Rule ID 3223 // 6141 GIM_CheckFeatures, GIFBS_IsBE, 6142 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 6143 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6145 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src) => (REV64v4i16:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src) 6146 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, 6147 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6148 // GIR_Coverage, 3223, 6149 GIR_Done, 6150 // Label 416: @13516 6151 GIM_Try, /*On fail goto*//*Label 417*/ 13539, // Rule ID 3224 // 6152 GIM_CheckFeatures, GIFBS_IsBE, 6153 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 6154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6156 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src) => (REV64v2i32:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src) 6157 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, 6158 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6159 // GIR_Coverage, 3224, 6160 GIR_Done, 6161 // Label 417: @13539 6162 GIM_Try, /*On fail goto*//*Label 418*/ 13571, // Rule ID 3225 // 6163 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6164 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6166 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v1i64] }:$src 6167 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6168 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6169 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6170 GIR_EraseFromParent, /*InsnID*/0, 6171 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6172 // GIR_Coverage, 3225, 6173 GIR_Done, 6174 // Label 418: @13571 6175 GIM_Try, /*On fail goto*//*Label 419*/ 13603, // Rule ID 3226 // 6176 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6179 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v1i64] }:$src 6180 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6181 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6182 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6183 GIR_EraseFromParent, /*InsnID*/0, 6184 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6185 // GIR_Coverage, 3226, 6186 GIR_Done, 6187 // Label 419: @13603 6188 GIM_Try, /*On fail goto*//*Label 420*/ 13637, // Rule ID 3280 // 6189 GIM_CheckFeatures, GIFBS_IsLE, 6190 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 6191 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6192 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6193 // (bitconvert:{ *:[f64] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[f64] }:$src 6194 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6195 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6196 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6197 GIR_EraseFromParent, /*InsnID*/0, 6198 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6199 // GIR_Coverage, 3280, 6200 GIR_Done, 6201 // Label 420: @13637 6202 GIM_Try, /*On fail goto*//*Label 421*/ 13671, // Rule ID 3281 // 6203 GIM_CheckFeatures, GIFBS_IsLE, 6204 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 6205 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6207 // (bitconvert:{ *:[f64] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[f64] }:$src 6208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6211 GIR_EraseFromParent, /*InsnID*/0, 6212 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6213 // GIR_Coverage, 3281, 6214 GIR_Done, 6215 // Label 421: @13671 6216 GIM_Try, /*On fail goto*//*Label 422*/ 13705, // Rule ID 3282 // 6217 GIM_CheckFeatures, GIFBS_IsLE, 6218 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 6219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6221 // (bitconvert:{ *:[f64] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[f64] }:$src 6222 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6225 GIR_EraseFromParent, /*InsnID*/0, 6226 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6227 // GIR_Coverage, 3282, 6228 GIR_Done, 6229 // Label 422: @13705 6230 GIM_Try, /*On fail goto*//*Label 423*/ 13739, // Rule ID 3283 // 6231 GIM_CheckFeatures, GIFBS_IsLE, 6232 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 6233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6235 // (bitconvert:{ *:[f64] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[f64] }:$src 6236 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6239 GIR_EraseFromParent, /*InsnID*/0, 6240 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6241 // GIR_Coverage, 3283, 6242 GIR_Done, 6243 // Label 423: @13739 6244 GIM_Try, /*On fail goto*//*Label 424*/ 13773, // Rule ID 3284 // 6245 GIM_CheckFeatures, GIFBS_IsLE, 6246 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 6247 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6248 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6249 // (bitconvert:{ *:[f64] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[f64] }:$src 6250 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6251 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6252 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6253 GIR_EraseFromParent, /*InsnID*/0, 6254 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6255 // GIR_Coverage, 3284, 6256 GIR_Done, 6257 // Label 424: @13773 6258 GIM_Try, /*On fail goto*//*Label 425*/ 13796, // Rule ID 3285 // 6259 GIM_CheckFeatures, GIFBS_IsBE, 6260 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 6261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6263 // (bitconvert:{ *:[f64] } FPR64:{ *:[v2i32] }:$src) => (REV64v2i32:{ *:[f64] } FPR64:{ *:[v2i32] }:$src) 6264 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, 6265 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6266 // GIR_Coverage, 3285, 6267 GIR_Done, 6268 // Label 425: @13796 6269 GIM_Try, /*On fail goto*//*Label 426*/ 13819, // Rule ID 3286 // 6270 GIM_CheckFeatures, GIFBS_IsBE, 6271 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 6272 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6274 // (bitconvert:{ *:[f64] } FPR64:{ *:[v4i16] }:$src) => (REV64v4i16:{ *:[f64] } FPR64:{ *:[v4i16] }:$src) 6275 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, 6276 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6277 // GIR_Coverage, 3286, 6278 GIR_Done, 6279 // Label 426: @13819 6280 GIM_Try, /*On fail goto*//*Label 427*/ 13842, // Rule ID 3287 // 6281 GIM_CheckFeatures, GIFBS_IsBE, 6282 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 6283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6285 // (bitconvert:{ *:[f64] } FPR64:{ *:[v2f32] }:$src) => (REV64v2i32:{ *:[f64] } FPR64:{ *:[v2f32] }:$src) 6286 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, 6287 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6288 // GIR_Coverage, 3287, 6289 GIR_Done, 6290 // Label 427: @13842 6291 GIM_Try, /*On fail goto*//*Label 428*/ 13865, // Rule ID 3288 // 6292 GIM_CheckFeatures, GIFBS_IsBE, 6293 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 6294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6295 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6296 // (bitconvert:{ *:[f64] } FPR64:{ *:[v8i8] }:$src) => (REV64v8i8:{ *:[f64] } FPR64:{ *:[v8i8] }:$src) 6297 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, 6298 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6299 // GIR_Coverage, 3288, 6300 GIR_Done, 6301 // Label 428: @13865 6302 GIM_Try, /*On fail goto*//*Label 429*/ 13888, // Rule ID 3289 // 6303 GIM_CheckFeatures, GIFBS_IsBE, 6304 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 6305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6307 // (bitconvert:{ *:[f64] } FPR64:{ *:[v4f16] }:$src) => (REV64v4i16:{ *:[f64] } FPR64:{ *:[v4f16] }:$src) 6308 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, 6309 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6310 // GIR_Coverage, 3289, 6311 GIR_Done, 6312 // Label 429: @13888 6313 GIM_Try, /*On fail goto*//*Label 430*/ 13920, // Rule ID 3290 // 6314 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6315 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6317 // (bitconvert:{ *:[f64] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[f64] }:$src 6318 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6319 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6321 GIR_EraseFromParent, /*InsnID*/0, 6322 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6323 // GIR_Coverage, 3290, 6324 GIR_Done, 6325 // Label 430: @13920 6326 GIM_Try, /*On fail goto*//*Label 431*/ 13952, // Rule ID 3291 // 6327 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6330 // (bitconvert:{ *:[f64] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[f64] }:$src 6331 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6332 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6334 GIR_EraseFromParent, /*InsnID*/0, 6335 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6336 // GIR_Coverage, 3291, 6337 GIR_Done, 6338 // Label 431: @13952 6339 GIM_Try, /*On fail goto*//*Label 432*/ 13986, // Rule ID 3292 // 6340 GIM_CheckFeatures, GIFBS_IsLE, 6341 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 6342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6343 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6344 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v1f64] }:$src 6345 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6346 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6347 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6348 GIR_EraseFromParent, /*InsnID*/0, 6349 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6350 // GIR_Coverage, 3292, 6351 GIR_Done, 6352 // Label 432: @13986 6353 GIM_Try, /*On fail goto*//*Label 433*/ 14020, // Rule ID 3293 // 6354 GIM_CheckFeatures, GIFBS_IsLE, 6355 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 6356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6358 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v1f64] }:$src 6359 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6360 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6361 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6362 GIR_EraseFromParent, /*InsnID*/0, 6363 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6364 // GIR_Coverage, 3293, 6365 GIR_Done, 6366 // Label 433: @14020 6367 GIM_Try, /*On fail goto*//*Label 434*/ 14054, // Rule ID 3294 // 6368 GIM_CheckFeatures, GIFBS_IsLE, 6369 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 6370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6372 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v1f64] }:$src 6373 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6374 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6375 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6376 GIR_EraseFromParent, /*InsnID*/0, 6377 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6378 // GIR_Coverage, 3294, 6379 GIR_Done, 6380 // Label 434: @14054 6381 GIM_Try, /*On fail goto*//*Label 435*/ 14088, // Rule ID 3295 // 6382 GIM_CheckFeatures, GIFBS_IsLE, 6383 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 6384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6386 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v1f64] }:$src 6387 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6389 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6390 GIR_EraseFromParent, /*InsnID*/0, 6391 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6392 // GIR_Coverage, 3295, 6393 GIR_Done, 6394 // Label 435: @14088 6395 GIM_Try, /*On fail goto*//*Label 436*/ 14122, // Rule ID 3296 // 6396 GIM_CheckFeatures, GIFBS_IsLE, 6397 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 6398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6400 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v1f64] }:$src 6401 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6404 GIR_EraseFromParent, /*InsnID*/0, 6405 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6406 // GIR_Coverage, 3296, 6407 GIR_Done, 6408 // Label 436: @14122 6409 GIM_Try, /*On fail goto*//*Label 437*/ 14145, // Rule ID 3297 // 6410 GIM_CheckFeatures, GIFBS_IsBE, 6411 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 6412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6414 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src) => (REV64v2i32:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src) 6415 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, 6416 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6417 // GIR_Coverage, 3297, 6418 GIR_Done, 6419 // Label 437: @14145 6420 GIM_Try, /*On fail goto*//*Label 438*/ 14168, // Rule ID 3298 // 6421 GIM_CheckFeatures, GIFBS_IsBE, 6422 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 6423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6425 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src) => (REV64v4i16:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src) 6426 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, 6427 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6428 // GIR_Coverage, 3298, 6429 GIR_Done, 6430 // Label 438: @14168 6431 GIM_Try, /*On fail goto*//*Label 439*/ 14191, // Rule ID 3299 // 6432 GIM_CheckFeatures, GIFBS_IsBE, 6433 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 6434 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6436 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src) => (REV64v8i8:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src) 6437 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, 6438 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6439 // GIR_Coverage, 3299, 6440 GIR_Done, 6441 // Label 439: @14191 6442 GIM_Try, /*On fail goto*//*Label 440*/ 14214, // Rule ID 3300 // 6443 GIM_CheckFeatures, GIFBS_IsBE, 6444 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 6445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6447 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src) => (REV64v2i32:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src) 6448 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, 6449 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6450 // GIR_Coverage, 3300, 6451 GIR_Done, 6452 // Label 440: @14214 6453 GIM_Try, /*On fail goto*//*Label 441*/ 14237, // Rule ID 3301 // 6454 GIM_CheckFeatures, GIFBS_IsBE, 6455 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 6456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6458 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src) => (REV64v4i16:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src) 6459 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, 6460 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6461 // GIR_Coverage, 3301, 6462 GIR_Done, 6463 // Label 441: @14237 6464 GIM_Try, /*On fail goto*//*Label 442*/ 14269, // Rule ID 3302 // 6465 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6468 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v1f64] }:$src 6469 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6470 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6471 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6472 GIR_EraseFromParent, /*InsnID*/0, 6473 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6474 // GIR_Coverage, 3302, 6475 GIR_Done, 6476 // Label 442: @14269 6477 GIM_Try, /*On fail goto*//*Label 443*/ 14301, // Rule ID 3303 // 6478 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6481 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v1f64] }:$src 6482 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6483 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6485 GIR_EraseFromParent, /*InsnID*/0, 6486 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6487 // GIR_Coverage, 3303, 6488 GIR_Done, 6489 // Label 443: @14301 6490 GIM_Reject, 6491 // Label 379: @14302 6492 GIM_Try, /*On fail goto*//*Label 444*/ 14336, // Rule ID 3317 // 6493 GIM_CheckFeatures, GIFBS_IsLE, 6494 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 6495 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 6496 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 6497 // (bitconvert:{ *:[f128] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[f128] }:$src 6498 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6500 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6501 GIR_EraseFromParent, /*InsnID*/0, 6502 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 6503 // GIR_Coverage, 3317, 6504 GIR_Done, 6505 // Label 444: @14336 6506 GIM_Try, /*On fail goto*//*Label 445*/ 14370, // Rule ID 3318 // 6507 GIM_CheckFeatures, GIFBS_IsLE, 6508 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 6509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 6510 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 6511 // (bitconvert:{ *:[f128] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[f128] }:$src 6512 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6513 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6514 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6515 GIR_EraseFromParent, /*InsnID*/0, 6516 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 6517 // GIR_Coverage, 3318, 6518 GIR_Done, 6519 // Label 445: @14370 6520 GIM_Try, /*On fail goto*//*Label 446*/ 14404, // Rule ID 3319 // 6521 GIM_CheckFeatures, GIFBS_IsLE, 6522 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 6523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 6524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 6525 // (bitconvert:{ *:[f128] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[f128] }:$src 6526 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6528 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6529 GIR_EraseFromParent, /*InsnID*/0, 6530 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 6531 // GIR_Coverage, 3319, 6532 GIR_Done, 6533 // Label 446: @14404 6534 GIM_Try, /*On fail goto*//*Label 447*/ 14438, // Rule ID 3320 // 6535 GIM_CheckFeatures, GIFBS_IsLE, 6536 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 6537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 6538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 6539 // (bitconvert:{ *:[f128] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[f128] }:$src 6540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6541 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6543 GIR_EraseFromParent, /*InsnID*/0, 6544 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 6545 // GIR_Coverage, 3320, 6546 GIR_Done, 6547 // Label 447: @14438 6548 GIM_Try, /*On fail goto*//*Label 448*/ 14472, // Rule ID 3321 // 6549 GIM_CheckFeatures, GIFBS_IsLE, 6550 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 6551 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 6552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 6553 // (bitconvert:{ *:[f128] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[f128] }:$src 6554 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6555 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6556 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6557 GIR_EraseFromParent, /*InsnID*/0, 6558 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 6559 // GIR_Coverage, 3321, 6560 GIR_Done, 6561 // Label 448: @14472 6562 GIM_Try, /*On fail goto*//*Label 449*/ 14506, // Rule ID 3322 // 6563 GIM_CheckFeatures, GIFBS_IsLE, 6564 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 6565 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 6566 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 6567 // (bitconvert:{ *:[f128] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[f128] }:$src 6568 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6569 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6570 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6571 GIR_EraseFromParent, /*InsnID*/0, 6572 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 6573 // GIR_Coverage, 3322, 6574 GIR_Done, 6575 // Label 449: @14506 6576 GIM_Try, /*On fail goto*//*Label 450*/ 14540, // Rule ID 3323 // 6577 GIM_CheckFeatures, GIFBS_IsLE, 6578 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 6579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 6580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 6581 // (bitconvert:{ *:[f128] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[f128] }:$src 6582 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6583 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6584 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6585 GIR_EraseFromParent, /*InsnID*/0, 6586 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 6587 // GIR_Coverage, 3323, 6588 GIR_Done, 6589 // Label 450: @14540 6590 GIM_Try, /*On fail goto*//*Label 451*/ 14579, // Rule ID 3324 // 6591 GIM_CheckFeatures, GIFBS_IsBE, 6592 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 6593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 6594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 6595 // (bitconvert:{ *:[f128] } FPR128:{ *:[v2i64] }:$src) => (EXTv16i8:{ *:[f128] } FPR128:{ *:[v2i64] }:$src, FPR128:{ *:[v2i64] }:$src, 8:{ *:[i32] }) 6596 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, 6597 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 6598 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6599 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6600 GIR_AddImm, /*InsnID*/0, /*Imm*/8, 6601 GIR_EraseFromParent, /*InsnID*/0, 6602 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6603 // GIR_Coverage, 3324, 6604 GIR_Done, 6605 // Label 451: @14579 6606 GIM_Try, /*On fail goto*//*Label 452*/ 14650, // Rule ID 3325 // 6607 GIM_CheckFeatures, GIFBS_IsBE, 6608 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 6609 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 6610 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 6611 // (bitconvert:{ *:[f128] } FPR128:{ *:[v4i32] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4i32] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4i32] }:$src), 8:{ *:[i32] }) 6612 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, 6613 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, 6614 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32, 6615 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6616 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 6617 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6618 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32, 6619 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6620 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 6621 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6622 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, 6623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 6624 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6625 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 6626 GIR_AddImm, /*InsnID*/0, /*Imm*/8, 6627 GIR_EraseFromParent, /*InsnID*/0, 6628 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6629 // GIR_Coverage, 3325, 6630 GIR_Done, 6631 // Label 452: @14650 6632 GIM_Try, /*On fail goto*//*Label 453*/ 14721, // Rule ID 3326 // 6633 GIM_CheckFeatures, GIFBS_IsBE, 6634 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 6635 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 6636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 6637 // (bitconvert:{ *:[f128] } FPR128:{ *:[v8i16] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8i16] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8i16] }:$src), 8:{ *:[i32] }) 6638 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, 6639 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, 6640 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, 6641 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6642 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 6643 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6644 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, 6645 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6646 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 6647 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6648 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, 6649 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 6650 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6651 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 6652 GIR_AddImm, /*InsnID*/0, /*Imm*/8, 6653 GIR_EraseFromParent, /*InsnID*/0, 6654 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6655 // GIR_Coverage, 3326, 6656 GIR_Done, 6657 // Label 453: @14721 6658 GIM_Try, /*On fail goto*//*Label 454*/ 14792, // Rule ID 3327 // 6659 GIM_CheckFeatures, GIFBS_IsBE, 6660 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 6661 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 6662 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 6663 // (bitconvert:{ *:[f128] } FPR128:{ *:[v8f16] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8f16] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8f16] }:$src), 8:{ *:[i32] }) 6664 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, 6665 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, 6666 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, 6667 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6668 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 6669 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6670 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, 6671 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6672 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 6673 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6674 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, 6675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 6676 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6677 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 6678 GIR_AddImm, /*InsnID*/0, /*Imm*/8, 6679 GIR_EraseFromParent, /*InsnID*/0, 6680 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6681 // GIR_Coverage, 3327, 6682 GIR_Done, 6683 // Label 454: @14792 6684 GIM_Try, /*On fail goto*//*Label 455*/ 14831, // Rule ID 3328 // 6685 GIM_CheckFeatures, GIFBS_IsBE, 6686 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 6687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 6688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 6689 // (bitconvert:{ *:[f128] } FPR128:{ *:[v2f64] }:$src) => (EXTv16i8:{ *:[f128] } FPR128:{ *:[v2f64] }:$src, FPR128:{ *:[v2f64] }:$src, 8:{ *:[i32] }) 6690 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, 6691 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 6692 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6693 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6694 GIR_AddImm, /*InsnID*/0, /*Imm*/8, 6695 GIR_EraseFromParent, /*InsnID*/0, 6696 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6697 // GIR_Coverage, 3328, 6698 GIR_Done, 6699 // Label 455: @14831 6700 GIM_Try, /*On fail goto*//*Label 456*/ 14902, // Rule ID 3329 // 6701 GIM_CheckFeatures, GIFBS_IsBE, 6702 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 6703 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 6704 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 6705 // (bitconvert:{ *:[f128] } FPR128:{ *:[v4f32] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4f32] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4f32] }:$src), 8:{ *:[i32] }) 6706 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, 6707 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, 6708 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32, 6709 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6710 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 6711 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6712 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32, 6713 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6714 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 6715 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6716 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, 6717 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 6718 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6719 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 6720 GIR_AddImm, /*InsnID*/0, /*Imm*/8, 6721 GIR_EraseFromParent, /*InsnID*/0, 6722 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6723 // GIR_Coverage, 3329, 6724 GIR_Done, 6725 // Label 456: @14902 6726 GIM_Try, /*On fail goto*//*Label 457*/ 14973, // Rule ID 3330 // 6727 GIM_CheckFeatures, GIFBS_IsBE, 6728 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 6729 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 6730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 6731 // (bitconvert:{ *:[f128] } FPR128:{ *:[v16i8] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v16i8:{ *:[f128] } FPR128:{ *:[v16i8] }:$src), (REV64v16i8:{ *:[f128] } FPR128:{ *:[v16i8] }:$src), 8:{ *:[i32] }) 6732 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, 6733 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, 6734 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v16i8, 6735 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6736 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 6737 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6738 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v16i8, 6739 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6740 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 6741 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6742 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, 6743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 6744 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6745 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 6746 GIR_AddImm, /*InsnID*/0, /*Imm*/8, 6747 GIR_EraseFromParent, /*InsnID*/0, 6748 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6749 // GIR_Coverage, 3330, 6750 GIR_Done, 6751 // Label 457: @14973 6752 GIM_Reject, 6753 // Label 380: @14974 6754 GIM_Try, /*On fail goto*//*Label 458*/ 14999, // Rule ID 3185 // 6755 GIM_CheckFeatures, GIFBS_IsLE, 6756 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 6759 // (bitconvert:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) 6760 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 6761 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6762 // GIR_Coverage, 3185, 6763 GIR_Done, 6764 // Label 458: @14999 6765 GIM_Try, /*On fail goto*//*Label 459*/ 15024, // Rule ID 3187 // 6766 GIM_CheckFeatures, GIFBS_IsLE, 6767 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6768 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6769 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 6770 // (bitconvert:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) 6771 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 6772 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6773 // GIR_Coverage, 3187, 6774 GIR_Done, 6775 // Label 459: @15024 6776 GIM_Try, /*On fail goto*//*Label 460*/ 15072, // Rule ID 3196 // 6777 GIM_CheckFeatures, GIFBS_IsBE, 6778 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 6781 // (bitconvert:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn) => (REV64v2i32:{ *:[v2i32] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) 6782 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 6783 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 6784 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6785 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn 6786 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6787 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32, 6788 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 6789 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6790 GIR_EraseFromParent, /*InsnID*/0, 6791 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6792 // GIR_Coverage, 3196, 6793 GIR_Done, 6794 // Label 460: @15072 6795 GIM_Try, /*On fail goto*//*Label 461*/ 15120, // Rule ID 3198 // 6796 GIM_CheckFeatures, GIFBS_IsBE, 6797 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 6800 // (bitconvert:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn) => (REV64v2i32:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) 6801 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 6802 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 6803 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6804 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn 6805 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6806 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32, 6807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 6808 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6809 GIR_EraseFromParent, /*InsnID*/0, 6810 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6811 // GIR_Coverage, 3198, 6812 GIR_Done, 6813 // Label 461: @15120 6814 GIM_Try, /*On fail goto*//*Label 462*/ 15154, // Rule ID 3227 // 6815 GIM_CheckFeatures, GIFBS_IsLE, 6816 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6818 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6819 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v2i32] }:$src 6820 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6821 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6822 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6823 GIR_EraseFromParent, /*InsnID*/0, 6824 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6825 // GIR_Coverage, 3227, 6826 GIR_Done, 6827 // Label 462: @15154 6828 GIM_Try, /*On fail goto*//*Label 463*/ 15188, // Rule ID 3228 // 6829 GIM_CheckFeatures, GIFBS_IsLE, 6830 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 6831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6832 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6833 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v2i32] }:$src 6834 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6835 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6836 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6837 GIR_EraseFromParent, /*InsnID*/0, 6838 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6839 // GIR_Coverage, 3228, 6840 GIR_Done, 6841 // Label 463: @15188 6842 GIM_Try, /*On fail goto*//*Label 464*/ 15222, // Rule ID 3229 // 6843 GIM_CheckFeatures, GIFBS_IsLE, 6844 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 6845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6847 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v2i32] }:$src 6848 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6849 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6851 GIR_EraseFromParent, /*InsnID*/0, 6852 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6853 // GIR_Coverage, 3229, 6854 GIR_Done, 6855 // Label 464: @15222 6856 GIM_Try, /*On fail goto*//*Label 465*/ 15256, // Rule ID 3230 // 6857 GIM_CheckFeatures, GIFBS_IsLE, 6858 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6861 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v2i32] }:$src 6862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6863 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6865 GIR_EraseFromParent, /*InsnID*/0, 6866 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6867 // GIR_Coverage, 3230, 6868 GIR_Done, 6869 // Label 465: @15256 6870 GIM_Try, /*On fail goto*//*Label 466*/ 15290, // Rule ID 3231 // 6871 GIM_CheckFeatures, GIFBS_IsLE, 6872 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6875 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v2i32] }:$src 6876 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6879 GIR_EraseFromParent, /*InsnID*/0, 6880 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6881 // GIR_Coverage, 3231, 6882 GIR_Done, 6883 // Label 466: @15290 6884 GIM_Try, /*On fail goto*//*Label 467*/ 15324, // Rule ID 3232 // 6885 GIM_CheckFeatures, GIFBS_IsLE, 6886 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 6887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6888 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6889 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v2i32] }:$src 6890 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6891 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6892 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6893 GIR_EraseFromParent, /*InsnID*/0, 6894 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6895 // GIR_Coverage, 3232, 6896 GIR_Done, 6897 // Label 467: @15324 6898 GIM_Try, /*On fail goto*//*Label 468*/ 15347, // Rule ID 3233 // 6899 GIM_CheckFeatures, GIFBS_IsBE, 6900 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6903 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src) => (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src) 6904 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, 6905 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6906 // GIR_Coverage, 3233, 6907 GIR_Done, 6908 // Label 468: @15347 6909 GIM_Try, /*On fail goto*//*Label 469*/ 15370, // Rule ID 3234 // 6910 GIM_CheckFeatures, GIFBS_IsBE, 6911 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 6912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6913 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6914 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src) => (REV32v4i16:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src) 6915 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, 6916 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6917 // GIR_Coverage, 3234, 6918 GIR_Done, 6919 // Label 469: @15370 6920 GIM_Try, /*On fail goto*//*Label 470*/ 15393, // Rule ID 3235 // 6921 GIM_CheckFeatures, GIFBS_IsBE, 6922 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 6923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6925 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src) => (REV32v8i8:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src) 6926 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i8, 6927 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6928 // GIR_Coverage, 3235, 6929 GIR_Done, 6930 // Label 470: @15393 6931 GIM_Try, /*On fail goto*//*Label 471*/ 15416, // Rule ID 3236 // 6932 GIM_CheckFeatures, GIFBS_IsBE, 6933 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6936 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[f64] }:$src) => (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[f64] }:$src) 6937 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, 6938 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6939 // GIR_Coverage, 3236, 6940 GIR_Done, 6941 // Label 471: @15416 6942 GIM_Try, /*On fail goto*//*Label 472*/ 15439, // Rule ID 3237 // 6943 GIM_CheckFeatures, GIFBS_IsBE, 6944 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6945 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6946 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6947 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src) => (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src) 6948 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, 6949 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6950 // GIR_Coverage, 3237, 6951 GIR_Done, 6952 // Label 472: @15439 6953 GIM_Try, /*On fail goto*//*Label 473*/ 15462, // Rule ID 3238 // 6954 GIM_CheckFeatures, GIFBS_IsBE, 6955 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 6956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6958 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src) => (REV32v4i16:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src) 6959 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, 6960 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6961 // GIR_Coverage, 3238, 6962 GIR_Done, 6963 // Label 473: @15462 6964 GIM_Try, /*On fail goto*//*Label 474*/ 15494, // Rule ID 3239 // 6965 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 6966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6968 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v2i32] }:$src 6969 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6971 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6972 GIR_EraseFromParent, /*InsnID*/0, 6973 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6974 // GIR_Coverage, 3239, 6975 GIR_Done, 6976 // Label 474: @15494 6977 GIM_Try, /*On fail goto*//*Label 475*/ 15528, // Rule ID 3304 // 6978 GIM_CheckFeatures, GIFBS_IsLE, 6979 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6982 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v2f32] }:$src 6983 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6984 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6985 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6986 GIR_EraseFromParent, /*InsnID*/0, 6987 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 6988 // GIR_Coverage, 3304, 6989 GIR_Done, 6990 // Label 475: @15528 6991 GIM_Try, /*On fail goto*//*Label 476*/ 15562, // Rule ID 3305 // 6992 GIM_CheckFeatures, GIFBS_IsLE, 6993 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 6994 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 6995 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 6996 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v2f32] }:$src 6997 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6998 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6999 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7000 GIR_EraseFromParent, /*InsnID*/0, 7001 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7002 // GIR_Coverage, 3305, 7003 GIR_Done, 7004 // Label 476: @15562 7005 GIM_Try, /*On fail goto*//*Label 477*/ 15596, // Rule ID 3306 // 7006 GIM_CheckFeatures, GIFBS_IsLE, 7007 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 7008 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7009 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7010 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v2f32] }:$src 7011 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7012 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7014 GIR_EraseFromParent, /*InsnID*/0, 7015 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7016 // GIR_Coverage, 3306, 7017 GIR_Done, 7018 // Label 477: @15596 7019 GIM_Try, /*On fail goto*//*Label 478*/ 15630, // Rule ID 3307 // 7020 GIM_CheckFeatures, GIFBS_IsLE, 7021 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7023 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7024 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v2f32] }:$src 7025 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7027 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7028 GIR_EraseFromParent, /*InsnID*/0, 7029 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7030 // GIR_Coverage, 3307, 7031 GIR_Done, 7032 // Label 478: @15630 7033 GIM_Try, /*On fail goto*//*Label 479*/ 15664, // Rule ID 3308 // 7034 GIM_CheckFeatures, GIFBS_IsLE, 7035 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7038 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v2f32] }:$src 7039 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7040 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7041 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7042 GIR_EraseFromParent, /*InsnID*/0, 7043 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7044 // GIR_Coverage, 3308, 7045 GIR_Done, 7046 // Label 479: @15664 7047 GIM_Try, /*On fail goto*//*Label 480*/ 15698, // Rule ID 3309 // 7048 GIM_CheckFeatures, GIFBS_IsLE, 7049 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 7050 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7051 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7052 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v2f32] }:$src 7053 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7056 GIR_EraseFromParent, /*InsnID*/0, 7057 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7058 // GIR_Coverage, 3309, 7059 GIR_Done, 7060 // Label 480: @15698 7061 GIM_Try, /*On fail goto*//*Label 481*/ 15721, // Rule ID 3310 // 7062 GIM_CheckFeatures, GIFBS_IsBE, 7063 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7065 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7066 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src) => (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src) 7067 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, 7068 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7069 // GIR_Coverage, 3310, 7070 GIR_Done, 7071 // Label 481: @15721 7072 GIM_Try, /*On fail goto*//*Label 482*/ 15744, // Rule ID 3311 // 7073 GIM_CheckFeatures, GIFBS_IsBE, 7074 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 7075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7076 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7077 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src) => (REV32v4i16:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src) 7078 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, 7079 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7080 // GIR_Coverage, 3311, 7081 GIR_Done, 7082 // Label 482: @15744 7083 GIM_Try, /*On fail goto*//*Label 483*/ 15767, // Rule ID 3312 // 7084 GIM_CheckFeatures, GIFBS_IsBE, 7085 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 7086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7088 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src) => (REV32v8i8:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src) 7089 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i8, 7090 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7091 // GIR_Coverage, 3312, 7092 GIR_Done, 7093 // Label 483: @15767 7094 GIM_Try, /*On fail goto*//*Label 484*/ 15790, // Rule ID 3313 // 7095 GIM_CheckFeatures, GIFBS_IsBE, 7096 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7097 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7098 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7099 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src) => (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src) 7100 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, 7101 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7102 // GIR_Coverage, 3313, 7103 GIR_Done, 7104 // Label 484: @15790 7105 GIM_Try, /*On fail goto*//*Label 485*/ 15813, // Rule ID 3314 // 7106 GIM_CheckFeatures, GIFBS_IsBE, 7107 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7110 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[f64] }:$src) => (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[f64] }:$src) 7111 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, 7112 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7113 // GIR_Coverage, 3314, 7114 GIR_Done, 7115 // Label 485: @15813 7116 GIM_Try, /*On fail goto*//*Label 486*/ 15836, // Rule ID 3315 // 7117 GIM_CheckFeatures, GIFBS_IsBE, 7118 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 7119 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7120 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7121 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src) => (REV32v4i16:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src) 7122 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, 7123 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7124 // GIR_Coverage, 3315, 7125 GIR_Done, 7126 // Label 486: @15836 7127 GIM_Try, /*On fail goto*//*Label 487*/ 15868, // Rule ID 3316 // 7128 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 7129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7131 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v2f32] }:$src 7132 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7135 GIR_EraseFromParent, /*InsnID*/0, 7136 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7137 // GIR_Coverage, 3316, 7138 GIR_Done, 7139 // Label 487: @15868 7140 GIM_Reject, 7141 // Label 381: @15869 7142 GIM_Try, /*On fail goto*//*Label 488*/ 15903, // Rule ID 3331 // 7143 GIM_CheckFeatures, GIFBS_IsLE, 7144 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 7145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7146 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7147 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v2f64] }:$src 7148 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7149 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7150 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7151 GIR_EraseFromParent, /*InsnID*/0, 7152 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7153 // GIR_Coverage, 3331, 7154 GIR_Done, 7155 // Label 488: @15903 7156 GIM_Try, /*On fail goto*//*Label 489*/ 15937, // Rule ID 3332 // 7157 GIM_CheckFeatures, GIFBS_IsLE, 7158 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 7159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7161 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v2f64] }:$src 7162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7165 GIR_EraseFromParent, /*InsnID*/0, 7166 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7167 // GIR_Coverage, 3332, 7168 GIR_Done, 7169 // Label 489: @15937 7170 GIM_Try, /*On fail goto*//*Label 490*/ 15971, // Rule ID 3333 // 7171 GIM_CheckFeatures, GIFBS_IsLE, 7172 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 7173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7175 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v2f64] }:$src 7176 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7177 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7178 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7179 GIR_EraseFromParent, /*InsnID*/0, 7180 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7181 // GIR_Coverage, 3333, 7182 GIR_Done, 7183 // Label 490: @15971 7184 GIM_Try, /*On fail goto*//*Label 491*/ 16005, // Rule ID 3334 // 7185 GIM_CheckFeatures, GIFBS_IsLE, 7186 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 7187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7189 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v2f64] }:$src 7190 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7191 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7192 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7193 GIR_EraseFromParent, /*InsnID*/0, 7194 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7195 // GIR_Coverage, 3334, 7196 GIR_Done, 7197 // Label 491: @16005 7198 GIM_Try, /*On fail goto*//*Label 492*/ 16039, // Rule ID 3335 // 7199 GIM_CheckFeatures, GIFBS_IsLE, 7200 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 7201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7202 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7203 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v2f64] }:$src 7204 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7206 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7207 GIR_EraseFromParent, /*InsnID*/0, 7208 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7209 // GIR_Coverage, 3335, 7210 GIR_Done, 7211 // Label 492: @16039 7212 GIM_Try, /*On fail goto*//*Label 493*/ 16073, // Rule ID 3336 // 7213 GIM_CheckFeatures, GIFBS_IsLE, 7214 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 7215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7217 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v2f64] }:$src 7218 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7219 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7220 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7221 GIR_EraseFromParent, /*InsnID*/0, 7222 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7223 // GIR_Coverage, 3336, 7224 GIR_Done, 7225 // Label 493: @16073 7226 GIM_Try, /*On fail goto*//*Label 494*/ 16112, // Rule ID 3337 // 7227 GIM_CheckFeatures, GIFBS_IsBE, 7228 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 7229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7230 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7231 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v2f64] } FPR128:{ *:[f128] }:$src, FPR128:{ *:[f128] }:$src, 8:{ *:[i32] }) 7232 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, 7233 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 7234 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7235 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7236 GIR_AddImm, /*InsnID*/0, /*Imm*/8, 7237 GIR_EraseFromParent, /*InsnID*/0, 7238 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7239 // GIR_Coverage, 3337, 7240 GIR_Done, 7241 // Label 494: @16112 7242 GIM_Try, /*On fail goto*//*Label 495*/ 16135, // Rule ID 3338 // 7243 GIM_CheckFeatures, GIFBS_IsBE, 7244 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 7245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7247 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src) => (REV64v4i32:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src) 7248 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, 7249 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7250 // GIR_Coverage, 3338, 7251 GIR_Done, 7252 // Label 495: @16135 7253 GIM_Try, /*On fail goto*//*Label 496*/ 16158, // Rule ID 3339 // 7254 GIM_CheckFeatures, GIFBS_IsBE, 7255 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 7256 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7257 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7258 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src) => (REV64v8i16:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src) 7259 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, 7260 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7261 // GIR_Coverage, 3339, 7262 GIR_Done, 7263 // Label 496: @16158 7264 GIM_Try, /*On fail goto*//*Label 497*/ 16181, // Rule ID 3340 // 7265 GIM_CheckFeatures, GIFBS_IsBE, 7266 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 7267 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7268 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7269 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src) => (REV64v8i16:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src) 7270 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, 7271 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7272 // GIR_Coverage, 3340, 7273 GIR_Done, 7274 // Label 497: @16181 7275 GIM_Try, /*On fail goto*//*Label 498*/ 16204, // Rule ID 3341 // 7276 GIM_CheckFeatures, GIFBS_IsBE, 7277 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 7278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7280 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src) => (REV64v16i8:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src) 7281 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v16i8, 7282 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7283 // GIR_Coverage, 3341, 7284 GIR_Done, 7285 // Label 498: @16204 7286 GIM_Try, /*On fail goto*//*Label 499*/ 16227, // Rule ID 3342 // 7287 GIM_CheckFeatures, GIFBS_IsBE, 7288 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 7289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7291 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src) => (REV64v4i32:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src) 7292 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, 7293 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7294 // GIR_Coverage, 3342, 7295 GIR_Done, 7296 // Label 499: @16227 7297 GIM_Try, /*On fail goto*//*Label 500*/ 16259, // Rule ID 3343 // 7298 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 7299 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7300 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7301 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v2f64] }:$src 7302 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7303 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7304 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7305 GIR_EraseFromParent, /*InsnID*/0, 7306 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7307 // GIR_Coverage, 3343, 7308 GIR_Done, 7309 // Label 500: @16259 7310 GIM_Try, /*On fail goto*//*Label 501*/ 16293, // Rule ID 3357 // 7311 GIM_CheckFeatures, GIFBS_IsLE, 7312 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 7313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7314 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7315 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v2i64] }:$src 7316 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7317 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7318 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7319 GIR_EraseFromParent, /*InsnID*/0, 7320 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7321 // GIR_Coverage, 3357, 7322 GIR_Done, 7323 // Label 501: @16293 7324 GIM_Try, /*On fail goto*//*Label 502*/ 16327, // Rule ID 3358 // 7325 GIM_CheckFeatures, GIFBS_IsLE, 7326 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 7327 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7329 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v2i64] }:$src 7330 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7331 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7332 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7333 GIR_EraseFromParent, /*InsnID*/0, 7334 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7335 // GIR_Coverage, 3358, 7336 GIR_Done, 7337 // Label 502: @16327 7338 GIM_Try, /*On fail goto*//*Label 503*/ 16361, // Rule ID 3359 // 7339 GIM_CheckFeatures, GIFBS_IsLE, 7340 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 7341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7343 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v2i64] }:$src 7344 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7345 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7346 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7347 GIR_EraseFromParent, /*InsnID*/0, 7348 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7349 // GIR_Coverage, 3359, 7350 GIR_Done, 7351 // Label 503: @16361 7352 GIM_Try, /*On fail goto*//*Label 504*/ 16395, // Rule ID 3360 // 7353 GIM_CheckFeatures, GIFBS_IsLE, 7354 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 7355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7357 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v2i64] }:$src 7358 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7359 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7360 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7361 GIR_EraseFromParent, /*InsnID*/0, 7362 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7363 // GIR_Coverage, 3360, 7364 GIR_Done, 7365 // Label 504: @16395 7366 GIM_Try, /*On fail goto*//*Label 505*/ 16429, // Rule ID 3361 // 7367 GIM_CheckFeatures, GIFBS_IsLE, 7368 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 7369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7371 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v2i64] }:$src 7372 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7373 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7374 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7375 GIR_EraseFromParent, /*InsnID*/0, 7376 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7377 // GIR_Coverage, 3361, 7378 GIR_Done, 7379 // Label 505: @16429 7380 GIM_Try, /*On fail goto*//*Label 506*/ 16463, // Rule ID 3362 // 7381 GIM_CheckFeatures, GIFBS_IsLE, 7382 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 7383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7385 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v2i64] }:$src 7386 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7387 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7389 GIR_EraseFromParent, /*InsnID*/0, 7390 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7391 // GIR_Coverage, 3362, 7392 GIR_Done, 7393 // Label 506: @16463 7394 GIM_Try, /*On fail goto*//*Label 507*/ 16502, // Rule ID 3363 // 7395 GIM_CheckFeatures, GIFBS_IsBE, 7396 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 7397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7399 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v2i64] } FPR128:{ *:[f128] }:$src, FPR128:{ *:[f128] }:$src, 8:{ *:[i32] }) 7400 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, 7401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 7402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7404 GIR_AddImm, /*InsnID*/0, /*Imm*/8, 7405 GIR_EraseFromParent, /*InsnID*/0, 7406 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7407 // GIR_Coverage, 3363, 7408 GIR_Done, 7409 // Label 507: @16502 7410 GIM_Try, /*On fail goto*//*Label 508*/ 16525, // Rule ID 3364 // 7411 GIM_CheckFeatures, GIFBS_IsBE, 7412 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 7413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7415 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src) => (REV64v4i32:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src) 7416 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, 7417 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7418 // GIR_Coverage, 3364, 7419 GIR_Done, 7420 // Label 508: @16525 7421 GIM_Try, /*On fail goto*//*Label 509*/ 16548, // Rule ID 3365 // 7422 GIM_CheckFeatures, GIFBS_IsBE, 7423 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 7424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7426 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src) => (REV64v8i16:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src) 7427 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, 7428 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7429 // GIR_Coverage, 3365, 7430 GIR_Done, 7431 // Label 509: @16548 7432 GIM_Try, /*On fail goto*//*Label 510*/ 16571, // Rule ID 3366 // 7433 GIM_CheckFeatures, GIFBS_IsBE, 7434 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 7435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7437 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src) => (REV64v16i8:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src) 7438 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v16i8, 7439 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7440 // GIR_Coverage, 3366, 7441 GIR_Done, 7442 // Label 510: @16571 7443 GIM_Try, /*On fail goto*//*Label 511*/ 16594, // Rule ID 3367 // 7444 GIM_CheckFeatures, GIFBS_IsBE, 7445 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 7446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7447 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7448 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src) => (REV64v4i32:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src) 7449 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, 7450 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7451 // GIR_Coverage, 3367, 7452 GIR_Done, 7453 // Label 511: @16594 7454 GIM_Try, /*On fail goto*//*Label 512*/ 16617, // Rule ID 3368 // 7455 GIM_CheckFeatures, GIFBS_IsBE, 7456 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 7457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7458 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7459 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src) => (REV64v8i16:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src) 7460 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, 7461 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7462 // GIR_Coverage, 3368, 7463 GIR_Done, 7464 // Label 512: @16617 7465 GIM_Try, /*On fail goto*//*Label 513*/ 16649, // Rule ID 3369 // 7466 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 7467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7469 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v2i64] }:$src 7470 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7471 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7472 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7473 GIR_EraseFromParent, /*InsnID*/0, 7474 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7475 // GIR_Coverage, 3369, 7476 GIR_Done, 7477 // Label 513: @16649 7478 GIM_Reject, 7479 // Label 382: @16650 7480 GIM_Try, /*On fail goto*//*Label 514*/ 16675, // Rule ID 3184 // 7481 GIM_CheckFeatures, GIFBS_IsLE, 7482 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7483 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7484 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 7485 // (bitconvert:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) 7486 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 7487 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7488 // GIR_Coverage, 3184, 7489 GIR_Done, 7490 // Label 514: @16675 7491 GIM_Try, /*On fail goto*//*Label 515*/ 16700, // Rule ID 3186 // 7492 GIM_CheckFeatures, GIFBS_IsLE, 7493 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7495 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 7496 // (bitconvert:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) 7497 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 7498 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7499 // GIR_Coverage, 3186, 7500 GIR_Done, 7501 // Label 515: @16700 7502 GIM_Try, /*On fail goto*//*Label 516*/ 16748, // Rule ID 3195 // 7503 GIM_CheckFeatures, GIFBS_IsBE, 7504 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7505 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7506 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 7507 // (bitconvert:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn) => (REV64v4i16:{ *:[v4i16] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) 7508 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 7509 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 7510 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7511 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn 7512 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7513 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, 7514 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 7515 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7516 GIR_EraseFromParent, /*InsnID*/0, 7517 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7518 // GIR_Coverage, 3195, 7519 GIR_Done, 7520 // Label 516: @16748 7521 GIM_Try, /*On fail goto*//*Label 517*/ 16796, // Rule ID 3197 // 7522 GIM_CheckFeatures, GIFBS_IsBE, 7523 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 7526 // (bitconvert:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn) => (REV64v4i16:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) 7527 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 7528 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 7529 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7530 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn 7531 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7532 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, 7533 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 7534 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7535 GIR_EraseFromParent, /*InsnID*/0, 7536 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7537 // GIR_Coverage, 3197, 7538 GIR_Done, 7539 // Label 517: @16796 7540 GIM_Try, /*On fail goto*//*Label 518*/ 16830, // Rule ID 3240 // 7541 GIM_CheckFeatures, GIFBS_IsLE, 7542 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7543 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7544 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7545 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v4i16] }:$src 7546 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7547 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7548 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7549 GIR_EraseFromParent, /*InsnID*/0, 7550 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7551 // GIR_Coverage, 3240, 7552 GIR_Done, 7553 // Label 518: @16830 7554 GIM_Try, /*On fail goto*//*Label 519*/ 16864, // Rule ID 3241 // 7555 GIM_CheckFeatures, GIFBS_IsLE, 7556 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 7557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7558 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7559 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v4i16] }:$src 7560 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7563 GIR_EraseFromParent, /*InsnID*/0, 7564 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7565 // GIR_Coverage, 3241, 7566 GIR_Done, 7567 // Label 519: @16864 7568 GIM_Try, /*On fail goto*//*Label 520*/ 16898, // Rule ID 3242 // 7569 GIM_CheckFeatures, GIFBS_IsLE, 7570 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 7571 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7572 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7573 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v4i16] }:$src 7574 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7575 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7576 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7577 GIR_EraseFromParent, /*InsnID*/0, 7578 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7579 // GIR_Coverage, 3242, 7580 GIR_Done, 7581 // Label 520: @16898 7582 GIM_Try, /*On fail goto*//*Label 521*/ 16932, // Rule ID 3243 // 7583 GIM_CheckFeatures, GIFBS_IsLE, 7584 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7587 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v4i16] }:$src 7588 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7589 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7590 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7591 GIR_EraseFromParent, /*InsnID*/0, 7592 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7593 // GIR_Coverage, 3243, 7594 GIR_Done, 7595 // Label 521: @16932 7596 GIM_Try, /*On fail goto*//*Label 522*/ 16966, // Rule ID 3244 // 7597 GIM_CheckFeatures, GIFBS_IsLE, 7598 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 7599 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7600 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7601 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v4i16] }:$src 7602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7605 GIR_EraseFromParent, /*InsnID*/0, 7606 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7607 // GIR_Coverage, 3244, 7608 GIR_Done, 7609 // Label 522: @16966 7610 GIM_Try, /*On fail goto*//*Label 523*/ 17000, // Rule ID 3245 // 7611 GIM_CheckFeatures, GIFBS_IsLE, 7612 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7615 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v4i16] }:$src 7616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7617 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7619 GIR_EraseFromParent, /*InsnID*/0, 7620 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7621 // GIR_Coverage, 3245, 7622 GIR_Done, 7623 // Label 523: @17000 7624 GIM_Try, /*On fail goto*//*Label 524*/ 17023, // Rule ID 3246 // 7625 GIM_CheckFeatures, GIFBS_IsBE, 7626 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7629 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src) => (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src) 7630 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, 7631 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7632 // GIR_Coverage, 3246, 7633 GIR_Done, 7634 // Label 524: @17023 7635 GIM_Try, /*On fail goto*//*Label 525*/ 17046, // Rule ID 3247 // 7636 GIM_CheckFeatures, GIFBS_IsBE, 7637 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 7638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7640 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src) => (REV32v4i16:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src) 7641 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, 7642 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7643 // GIR_Coverage, 3247, 7644 GIR_Done, 7645 // Label 525: @17046 7646 GIM_Try, /*On fail goto*//*Label 526*/ 17069, // Rule ID 3248 // 7647 GIM_CheckFeatures, GIFBS_IsBE, 7648 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 7649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7651 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src) => (REV16v8i8:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src) 7652 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, 7653 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7654 // GIR_Coverage, 3248, 7655 GIR_Done, 7656 // Label 526: @17069 7657 GIM_Try, /*On fail goto*//*Label 527*/ 17092, // Rule ID 3249 // 7658 GIM_CheckFeatures, GIFBS_IsBE, 7659 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7660 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7661 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7662 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[f64] }:$src) => (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[f64] }:$src) 7663 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, 7664 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7665 // GIR_Coverage, 3249, 7666 GIR_Done, 7667 // Label 527: @17092 7668 GIM_Try, /*On fail goto*//*Label 528*/ 17115, // Rule ID 3250 // 7669 GIM_CheckFeatures, GIFBS_IsBE, 7670 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 7671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7673 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src) => (REV32v4i16:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src) 7674 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, 7675 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7676 // GIR_Coverage, 3250, 7677 GIR_Done, 7678 // Label 528: @17115 7679 GIM_Try, /*On fail goto*//*Label 529*/ 17138, // Rule ID 3251 // 7680 GIM_CheckFeatures, GIFBS_IsBE, 7681 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7684 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src) => (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src) 7685 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, 7686 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7687 // GIR_Coverage, 3251, 7688 GIR_Done, 7689 // Label 529: @17138 7690 GIM_Try, /*On fail goto*//*Label 530*/ 17170, // Rule ID 3252 // 7691 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 7692 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7693 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7694 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v4i16] }:$src 7695 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7696 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7697 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7698 GIR_EraseFromParent, /*InsnID*/0, 7699 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7700 // GIR_Coverage, 3252, 7701 GIR_Done, 7702 // Label 530: @17170 7703 GIM_Try, /*On fail goto*//*Label 531*/ 17204, // Rule ID 3253 // 7704 GIM_CheckFeatures, GIFBS_IsLE, 7705 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7706 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7707 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7708 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v4f16] }:$src 7709 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7710 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7711 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7712 GIR_EraseFromParent, /*InsnID*/0, 7713 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7714 // GIR_Coverage, 3253, 7715 GIR_Done, 7716 // Label 531: @17204 7717 GIM_Try, /*On fail goto*//*Label 532*/ 17238, // Rule ID 3254 // 7718 GIM_CheckFeatures, GIFBS_IsLE, 7719 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 7720 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7722 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v4f16] }:$src 7723 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7724 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7725 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7726 GIR_EraseFromParent, /*InsnID*/0, 7727 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7728 // GIR_Coverage, 3254, 7729 GIR_Done, 7730 // Label 532: @17238 7731 GIM_Try, /*On fail goto*//*Label 533*/ 17272, // Rule ID 3255 // 7732 GIM_CheckFeatures, GIFBS_IsLE, 7733 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 7734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7736 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v4f16] }:$src 7737 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7738 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7739 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7740 GIR_EraseFromParent, /*InsnID*/0, 7741 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7742 // GIR_Coverage, 3255, 7743 GIR_Done, 7744 // Label 533: @17272 7745 GIM_Try, /*On fail goto*//*Label 534*/ 17306, // Rule ID 3256 // 7746 GIM_CheckFeatures, GIFBS_IsLE, 7747 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7748 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7750 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v4f16] }:$src 7751 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7754 GIR_EraseFromParent, /*InsnID*/0, 7755 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7756 // GIR_Coverage, 3256, 7757 GIR_Done, 7758 // Label 534: @17306 7759 GIM_Try, /*On fail goto*//*Label 535*/ 17340, // Rule ID 3257 // 7760 GIM_CheckFeatures, GIFBS_IsLE, 7761 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 7762 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7763 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7764 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v4f16] }:$src 7765 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7766 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7767 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7768 GIR_EraseFromParent, /*InsnID*/0, 7769 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7770 // GIR_Coverage, 3257, 7771 GIR_Done, 7772 // Label 535: @17340 7773 GIM_Try, /*On fail goto*//*Label 536*/ 17374, // Rule ID 3258 // 7774 GIM_CheckFeatures, GIFBS_IsLE, 7775 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7776 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7778 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v4f16] }:$src 7779 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7780 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7781 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7782 GIR_EraseFromParent, /*InsnID*/0, 7783 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7784 // GIR_Coverage, 3258, 7785 GIR_Done, 7786 // Label 536: @17374 7787 GIM_Try, /*On fail goto*//*Label 537*/ 17397, // Rule ID 3259 // 7788 GIM_CheckFeatures, GIFBS_IsBE, 7789 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7790 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7791 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7792 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src) => (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src) 7793 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, 7794 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7795 // GIR_Coverage, 3259, 7796 GIR_Done, 7797 // Label 537: @17397 7798 GIM_Try, /*On fail goto*//*Label 538*/ 17420, // Rule ID 3260 // 7799 GIM_CheckFeatures, GIFBS_IsBE, 7800 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 7801 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7802 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7803 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src) => (REV32v4i16:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src) 7804 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, 7805 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7806 // GIR_Coverage, 3260, 7807 GIR_Done, 7808 // Label 538: @17420 7809 GIM_Try, /*On fail goto*//*Label 539*/ 17443, // Rule ID 3261 // 7810 GIM_CheckFeatures, GIFBS_IsBE, 7811 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 7812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7813 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7814 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src) => (REV16v8i8:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src) 7815 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, 7816 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7817 // GIR_Coverage, 3261, 7818 GIR_Done, 7819 // Label 539: @17443 7820 GIM_Try, /*On fail goto*//*Label 540*/ 17466, // Rule ID 3262 // 7821 GIM_CheckFeatures, GIFBS_IsBE, 7822 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7823 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7824 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7825 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[f64] }:$src) => (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[f64] }:$src) 7826 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, 7827 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7828 // GIR_Coverage, 3262, 7829 GIR_Done, 7830 // Label 540: @17466 7831 GIM_Try, /*On fail goto*//*Label 541*/ 17489, // Rule ID 3263 // 7832 GIM_CheckFeatures, GIFBS_IsBE, 7833 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 7834 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7835 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7836 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src) => (REV32v4i16:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src) 7837 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, 7838 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7839 // GIR_Coverage, 3263, 7840 GIR_Done, 7841 // Label 541: @17489 7842 GIM_Try, /*On fail goto*//*Label 542*/ 17512, // Rule ID 3264 // 7843 GIM_CheckFeatures, GIFBS_IsBE, 7844 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7847 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src) => (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src) 7848 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, 7849 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7850 // GIR_Coverage, 3264, 7851 GIR_Done, 7852 // Label 542: @17512 7853 GIM_Try, /*On fail goto*//*Label 543*/ 17544, // Rule ID 3265 // 7854 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 7855 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 7856 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 7857 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v4f16] }:$src 7858 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7861 GIR_EraseFromParent, /*InsnID*/0, 7862 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 7863 // GIR_Coverage, 3265, 7864 GIR_Done, 7865 // Label 543: @17544 7866 GIM_Reject, 7867 // Label 383: @17545 7868 GIM_Try, /*On fail goto*//*Label 544*/ 17579, // Rule ID 3344 // 7869 GIM_CheckFeatures, GIFBS_IsLE, 7870 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 7871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7873 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v4f32] }:$src 7874 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7875 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7876 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7877 GIR_EraseFromParent, /*InsnID*/0, 7878 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7879 // GIR_Coverage, 3344, 7880 GIR_Done, 7881 // Label 544: @17579 7882 GIM_Try, /*On fail goto*//*Label 545*/ 17613, // Rule ID 3345 // 7883 GIM_CheckFeatures, GIFBS_IsLE, 7884 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 7885 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7887 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v4f32] }:$src 7888 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7891 GIR_EraseFromParent, /*InsnID*/0, 7892 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7893 // GIR_Coverage, 3345, 7894 GIR_Done, 7895 // Label 545: @17613 7896 GIM_Try, /*On fail goto*//*Label 546*/ 17647, // Rule ID 3346 // 7897 GIM_CheckFeatures, GIFBS_IsLE, 7898 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 7899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7901 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v4f32] }:$src 7902 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7904 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7905 GIR_EraseFromParent, /*InsnID*/0, 7906 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7907 // GIR_Coverage, 3346, 7908 GIR_Done, 7909 // Label 546: @17647 7910 GIM_Try, /*On fail goto*//*Label 547*/ 17681, // Rule ID 3347 // 7911 GIM_CheckFeatures, GIFBS_IsLE, 7912 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 7913 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7914 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7915 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v4f32] }:$src 7916 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7917 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7918 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7919 GIR_EraseFromParent, /*InsnID*/0, 7920 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7921 // GIR_Coverage, 3347, 7922 GIR_Done, 7923 // Label 547: @17681 7924 GIM_Try, /*On fail goto*//*Label 548*/ 17715, // Rule ID 3348 // 7925 GIM_CheckFeatures, GIFBS_IsLE, 7926 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 7927 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7928 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7929 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v4f32] }:$src 7930 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7931 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7932 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7933 GIR_EraseFromParent, /*InsnID*/0, 7934 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7935 // GIR_Coverage, 3348, 7936 GIR_Done, 7937 // Label 548: @17715 7938 GIM_Try, /*On fail goto*//*Label 549*/ 17749, // Rule ID 3349 // 7939 GIM_CheckFeatures, GIFBS_IsLE, 7940 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 7941 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7943 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v4f32] }:$src 7944 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7947 GIR_EraseFromParent, /*InsnID*/0, 7948 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 7949 // GIR_Coverage, 3349, 7950 GIR_Done, 7951 // Label 549: @17749 7952 GIM_Try, /*On fail goto*//*Label 550*/ 17820, // Rule ID 3350 // 7953 GIM_CheckFeatures, GIFBS_IsBE, 7954 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 7955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7957 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v4f32] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) 7958 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, 7959 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, 7960 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32, 7961 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 7962 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 7963 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 7964 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32, 7965 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7966 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 7967 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7968 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, 7969 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 7970 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7971 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 7972 GIR_AddImm, /*InsnID*/0, /*Imm*/8, 7973 GIR_EraseFromParent, /*InsnID*/0, 7974 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7975 // GIR_Coverage, 3350, 7976 GIR_Done, 7977 // Label 550: @17820 7978 GIM_Try, /*On fail goto*//*Label 551*/ 17843, // Rule ID 3351 // 7979 GIM_CheckFeatures, GIFBS_IsBE, 7980 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 7981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7983 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src) => (REV32v8i16:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src) 7984 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, 7985 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7986 // GIR_Coverage, 3351, 7987 GIR_Done, 7988 // Label 551: @17843 7989 GIM_Try, /*On fail goto*//*Label 552*/ 17866, // Rule ID 3352 // 7990 GIM_CheckFeatures, GIFBS_IsBE, 7991 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 7992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 7993 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 7994 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src) => (REV32v8i16:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src) 7995 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, 7996 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7997 // GIR_Coverage, 3352, 7998 GIR_Done, 7999 // Label 552: @17866 8000 GIM_Try, /*On fail goto*//*Label 553*/ 17889, // Rule ID 3353 // 8001 GIM_CheckFeatures, GIFBS_IsBE, 8002 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 8003 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8005 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src) => (REV32v16i8:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src) 8006 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v16i8, 8007 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8008 // GIR_Coverage, 3353, 8009 GIR_Done, 8010 // Label 553: @17889 8011 GIM_Try, /*On fail goto*//*Label 554*/ 17912, // Rule ID 3354 // 8012 GIM_CheckFeatures, GIFBS_IsBE, 8013 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 8014 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8016 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src) => (REV64v4i32:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src) 8017 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, 8018 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8019 // GIR_Coverage, 3354, 8020 GIR_Done, 8021 // Label 554: @17912 8022 GIM_Try, /*On fail goto*//*Label 555*/ 17935, // Rule ID 3355 // 8023 GIM_CheckFeatures, GIFBS_IsBE, 8024 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 8025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8027 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src) => (REV64v4i32:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src) 8028 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, 8029 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8030 // GIR_Coverage, 3355, 8031 GIR_Done, 8032 // Label 555: @17935 8033 GIM_Try, /*On fail goto*//*Label 556*/ 17967, // Rule ID 3356 // 8034 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 8035 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8037 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v4f32] }:$src 8038 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8039 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8040 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8041 GIR_EraseFromParent, /*InsnID*/0, 8042 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8043 // GIR_Coverage, 3356, 8044 GIR_Done, 8045 // Label 556: @17967 8046 GIM_Try, /*On fail goto*//*Label 557*/ 18001, // Rule ID 3370 // 8047 GIM_CheckFeatures, GIFBS_IsLE, 8048 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 8049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8050 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8051 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v4i32] }:$src 8052 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8053 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8055 GIR_EraseFromParent, /*InsnID*/0, 8056 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8057 // GIR_Coverage, 3370, 8058 GIR_Done, 8059 // Label 557: @18001 8060 GIM_Try, /*On fail goto*//*Label 558*/ 18035, // Rule ID 3371 // 8061 GIM_CheckFeatures, GIFBS_IsLE, 8062 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 8063 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8065 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v4i32] }:$src 8066 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8067 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8069 GIR_EraseFromParent, /*InsnID*/0, 8070 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8071 // GIR_Coverage, 3371, 8072 GIR_Done, 8073 // Label 558: @18035 8074 GIM_Try, /*On fail goto*//*Label 559*/ 18069, // Rule ID 3372 // 8075 GIM_CheckFeatures, GIFBS_IsLE, 8076 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 8077 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8079 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v4i32] }:$src 8080 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8081 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8083 GIR_EraseFromParent, /*InsnID*/0, 8084 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8085 // GIR_Coverage, 3372, 8086 GIR_Done, 8087 // Label 559: @18069 8088 GIM_Try, /*On fail goto*//*Label 560*/ 18103, // Rule ID 3373 // 8089 GIM_CheckFeatures, GIFBS_IsLE, 8090 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 8091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8092 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8093 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v4i32] }:$src 8094 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8095 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8096 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8097 GIR_EraseFromParent, /*InsnID*/0, 8098 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8099 // GIR_Coverage, 3373, 8100 GIR_Done, 8101 // Label 560: @18103 8102 GIM_Try, /*On fail goto*//*Label 561*/ 18137, // Rule ID 3374 // 8103 GIM_CheckFeatures, GIFBS_IsLE, 8104 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 8105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8107 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v4i32] }:$src 8108 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8109 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8110 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8111 GIR_EraseFromParent, /*InsnID*/0, 8112 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8113 // GIR_Coverage, 3374, 8114 GIR_Done, 8115 // Label 561: @18137 8116 GIM_Try, /*On fail goto*//*Label 562*/ 18171, // Rule ID 3375 // 8117 GIM_CheckFeatures, GIFBS_IsLE, 8118 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 8119 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8120 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8121 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v4i32] }:$src 8122 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8123 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8124 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8125 GIR_EraseFromParent, /*InsnID*/0, 8126 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8127 // GIR_Coverage, 3375, 8128 GIR_Done, 8129 // Label 562: @18171 8130 GIM_Try, /*On fail goto*//*Label 563*/ 18242, // Rule ID 3376 // 8131 GIM_CheckFeatures, GIFBS_IsBE, 8132 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 8133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8134 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8135 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v4i32] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) 8136 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, 8137 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, 8138 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32, 8139 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 8140 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 8141 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 8142 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32, 8143 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 8144 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 8145 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 8146 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, 8147 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 8148 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 8149 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 8150 GIR_AddImm, /*InsnID*/0, /*Imm*/8, 8151 GIR_EraseFromParent, /*InsnID*/0, 8152 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8153 // GIR_Coverage, 3376, 8154 GIR_Done, 8155 // Label 563: @18242 8156 GIM_Try, /*On fail goto*//*Label 564*/ 18265, // Rule ID 3377 // 8157 GIM_CheckFeatures, GIFBS_IsBE, 8158 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 8159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8161 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src) => (REV64v4i32:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src) 8162 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, 8163 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8164 // GIR_Coverage, 3377, 8165 GIR_Done, 8166 // Label 564: @18265 8167 GIM_Try, /*On fail goto*//*Label 565*/ 18288, // Rule ID 3378 // 8168 GIM_CheckFeatures, GIFBS_IsBE, 8169 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 8170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8171 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8172 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src) => (REV32v8i16:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src) 8173 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, 8174 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8175 // GIR_Coverage, 3378, 8176 GIR_Done, 8177 // Label 565: @18288 8178 GIM_Try, /*On fail goto*//*Label 566*/ 18311, // Rule ID 3379 // 8179 GIM_CheckFeatures, GIFBS_IsBE, 8180 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 8181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8183 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src) => (REV32v16i8:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src) 8184 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v16i8, 8185 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8186 // GIR_Coverage, 3379, 8187 GIR_Done, 8188 // Label 566: @18311 8189 GIM_Try, /*On fail goto*//*Label 567*/ 18334, // Rule ID 3380 // 8190 GIM_CheckFeatures, GIFBS_IsBE, 8191 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 8192 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8193 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8194 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src) => (REV64v4i32:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src) 8195 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, 8196 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8197 // GIR_Coverage, 3380, 8198 GIR_Done, 8199 // Label 567: @18334 8200 GIM_Try, /*On fail goto*//*Label 568*/ 18357, // Rule ID 3381 // 8201 GIM_CheckFeatures, GIFBS_IsBE, 8202 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 8203 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8204 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8205 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src) => (REV32v8i16:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src) 8206 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, 8207 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8208 // GIR_Coverage, 3381, 8209 GIR_Done, 8210 // Label 568: @18357 8211 GIM_Try, /*On fail goto*//*Label 569*/ 18389, // Rule ID 3382 // 8212 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 8213 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8215 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v4i32] }:$src 8216 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8217 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8218 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8219 GIR_EraseFromParent, /*InsnID*/0, 8220 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8221 // GIR_Coverage, 3382, 8222 GIR_Done, 8223 // Label 569: @18389 8224 GIM_Reject, 8225 // Label 384: @18390 8226 GIM_Try, /*On fail goto*//*Label 570*/ 18415, // Rule ID 3183 // 8227 GIM_CheckFeatures, GIFBS_IsLE, 8228 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 8229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 8230 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 8231 // (bitconvert:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) 8232 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 8233 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 8234 // GIR_Coverage, 3183, 8235 GIR_Done, 8236 // Label 570: @18415 8237 GIM_Try, /*On fail goto*//*Label 571*/ 18463, // Rule ID 3194 // 8238 GIM_CheckFeatures, GIFBS_IsBE, 8239 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 8240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 8241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 8242 // (bitconvert:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn) => (REV64v8i8:{ *:[v8i8] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) 8243 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 8244 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 8245 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 8246 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn 8247 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 8248 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v8i8, 8249 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 8250 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 8251 GIR_EraseFromParent, /*InsnID*/0, 8252 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8253 // GIR_Coverage, 3194, 8254 GIR_Done, 8255 // Label 571: @18463 8256 GIM_Try, /*On fail goto*//*Label 572*/ 18497, // Rule ID 3266 // 8257 GIM_CheckFeatures, GIFBS_IsLE, 8258 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 8259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 8260 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 8261 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v8i8] }:$src 8262 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8263 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8264 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8265 GIR_EraseFromParent, /*InsnID*/0, 8266 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 8267 // GIR_Coverage, 3266, 8268 GIR_Done, 8269 // Label 572: @18497 8270 GIM_Try, /*On fail goto*//*Label 573*/ 18531, // Rule ID 3267 // 8271 GIM_CheckFeatures, GIFBS_IsLE, 8272 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 8273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 8274 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 8275 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v8i8] }:$src 8276 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8278 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8279 GIR_EraseFromParent, /*InsnID*/0, 8280 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 8281 // GIR_Coverage, 3267, 8282 GIR_Done, 8283 // Label 573: @18531 8284 GIM_Try, /*On fail goto*//*Label 574*/ 18565, // Rule ID 3268 // 8285 GIM_CheckFeatures, GIFBS_IsLE, 8286 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 8287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 8288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 8289 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v8i8] }:$src 8290 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8293 GIR_EraseFromParent, /*InsnID*/0, 8294 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 8295 // GIR_Coverage, 3268, 8296 GIR_Done, 8297 // Label 574: @18565 8298 GIM_Try, /*On fail goto*//*Label 575*/ 18599, // Rule ID 3269 // 8299 GIM_CheckFeatures, GIFBS_IsLE, 8300 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 8301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 8302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 8303 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v8i8] }:$src 8304 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8305 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8306 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8307 GIR_EraseFromParent, /*InsnID*/0, 8308 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 8309 // GIR_Coverage, 3269, 8310 GIR_Done, 8311 // Label 575: @18599 8312 GIM_Try, /*On fail goto*//*Label 576*/ 18633, // Rule ID 3270 // 8313 GIM_CheckFeatures, GIFBS_IsLE, 8314 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 8315 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 8316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 8317 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v8i8] }:$src 8318 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8319 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8321 GIR_EraseFromParent, /*InsnID*/0, 8322 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 8323 // GIR_Coverage, 3270, 8324 GIR_Done, 8325 // Label 576: @18633 8326 GIM_Try, /*On fail goto*//*Label 577*/ 18667, // Rule ID 3271 // 8327 GIM_CheckFeatures, GIFBS_IsLE, 8328 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 8329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 8330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 8331 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v8i8] }:$src 8332 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8334 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8335 GIR_EraseFromParent, /*InsnID*/0, 8336 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 8337 // GIR_Coverage, 3271, 8338 GIR_Done, 8339 // Label 577: @18667 8340 GIM_Try, /*On fail goto*//*Label 578*/ 18701, // Rule ID 3272 // 8341 GIM_CheckFeatures, GIFBS_IsLE, 8342 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 8343 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 8344 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 8345 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v8i8] }:$src 8346 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8347 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8348 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8349 GIR_EraseFromParent, /*InsnID*/0, 8350 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, 8351 // GIR_Coverage, 3272, 8352 GIR_Done, 8353 // Label 578: @18701 8354 GIM_Try, /*On fail goto*//*Label 579*/ 18724, // Rule ID 3273 // 8355 GIM_CheckFeatures, GIFBS_IsBE, 8356 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 8357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 8358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 8359 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src) => (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src) 8360 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, 8361 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8362 // GIR_Coverage, 3273, 8363 GIR_Done, 8364 // Label 579: @18724 8365 GIM_Try, /*On fail goto*//*Label 580*/ 18747, // Rule ID 3274 // 8366 GIM_CheckFeatures, GIFBS_IsBE, 8367 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 8368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 8369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 8370 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src) => (REV32v8i8:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src) 8371 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i8, 8372 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8373 // GIR_Coverage, 3274, 8374 GIR_Done, 8375 // Label 580: @18747 8376 GIM_Try, /*On fail goto*//*Label 581*/ 18770, // Rule ID 3275 // 8377 GIM_CheckFeatures, GIFBS_IsBE, 8378 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 8379 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 8380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 8381 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src) => (REV16v8i8:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src) 8382 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, 8383 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8384 // GIR_Coverage, 3275, 8385 GIR_Done, 8386 // Label 581: @18770 8387 GIM_Try, /*On fail goto*//*Label 582*/ 18793, // Rule ID 3276 // 8388 GIM_CheckFeatures, GIFBS_IsBE, 8389 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 8390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 8391 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 8392 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[f64] }:$src) => (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[f64] }:$src) 8393 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, 8394 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8395 // GIR_Coverage, 3276, 8396 GIR_Done, 8397 // Label 582: @18793 8398 GIM_Try, /*On fail goto*//*Label 583*/ 18816, // Rule ID 3277 // 8399 GIM_CheckFeatures, GIFBS_IsBE, 8400 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 8401 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 8402 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 8403 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src) => (REV32v8i8:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src) 8404 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i8, 8405 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8406 // GIR_Coverage, 3277, 8407 GIR_Done, 8408 // Label 583: @18816 8409 GIM_Try, /*On fail goto*//*Label 584*/ 18839, // Rule ID 3278 // 8410 GIM_CheckFeatures, GIFBS_IsBE, 8411 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 8412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 8413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 8414 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src) => (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src) 8415 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, 8416 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8417 // GIR_Coverage, 3278, 8418 GIR_Done, 8419 // Label 584: @18839 8420 GIM_Try, /*On fail goto*//*Label 585*/ 18862, // Rule ID 3279 // 8421 GIM_CheckFeatures, GIFBS_IsBE, 8422 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 8423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 8424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 8425 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src) => (REV16v8i8:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src) 8426 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, 8427 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8428 // GIR_Coverage, 3279, 8429 GIR_Done, 8430 // Label 585: @18862 8431 GIM_Reject, 8432 // Label 385: @18863 8433 GIM_Try, /*On fail goto*//*Label 586*/ 18897, // Rule ID 3383 // 8434 GIM_CheckFeatures, GIFBS_IsLE, 8435 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 8436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8438 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v8i16] }:$src 8439 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8441 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8442 GIR_EraseFromParent, /*InsnID*/0, 8443 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8444 // GIR_Coverage, 3383, 8445 GIR_Done, 8446 // Label 586: @18897 8447 GIM_Try, /*On fail goto*//*Label 587*/ 18931, // Rule ID 3384 // 8448 GIM_CheckFeatures, GIFBS_IsLE, 8449 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 8450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8451 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8452 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v8i16] }:$src 8453 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8454 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8456 GIR_EraseFromParent, /*InsnID*/0, 8457 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8458 // GIR_Coverage, 3384, 8459 GIR_Done, 8460 // Label 587: @18931 8461 GIM_Try, /*On fail goto*//*Label 588*/ 18965, // Rule ID 3385 // 8462 GIM_CheckFeatures, GIFBS_IsLE, 8463 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 8464 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8466 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v8i16] }:$src 8467 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8468 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8469 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8470 GIR_EraseFromParent, /*InsnID*/0, 8471 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8472 // GIR_Coverage, 3385, 8473 GIR_Done, 8474 // Label 588: @18965 8475 GIM_Try, /*On fail goto*//*Label 589*/ 18999, // Rule ID 3386 // 8476 GIM_CheckFeatures, GIFBS_IsLE, 8477 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 8478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8480 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v8i16] }:$src 8481 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8482 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8483 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8484 GIR_EraseFromParent, /*InsnID*/0, 8485 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8486 // GIR_Coverage, 3386, 8487 GIR_Done, 8488 // Label 589: @18999 8489 GIM_Try, /*On fail goto*//*Label 590*/ 19033, // Rule ID 3387 // 8490 GIM_CheckFeatures, GIFBS_IsLE, 8491 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 8492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8494 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v8i16] }:$src 8495 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8496 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8497 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8498 GIR_EraseFromParent, /*InsnID*/0, 8499 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8500 // GIR_Coverage, 3387, 8501 GIR_Done, 8502 // Label 590: @19033 8503 GIM_Try, /*On fail goto*//*Label 591*/ 19067, // Rule ID 3388 // 8504 GIM_CheckFeatures, GIFBS_IsLE, 8505 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 8506 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8507 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8508 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v8i16] }:$src 8509 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8510 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8511 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8512 GIR_EraseFromParent, /*InsnID*/0, 8513 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8514 // GIR_Coverage, 3388, 8515 GIR_Done, 8516 // Label 591: @19067 8517 GIM_Try, /*On fail goto*//*Label 592*/ 19138, // Rule ID 3389 // 8518 GIM_CheckFeatures, GIFBS_IsBE, 8519 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 8520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8522 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v8i16] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) 8523 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, 8524 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, 8525 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, 8526 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 8527 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 8528 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 8529 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, 8530 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 8531 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 8532 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 8533 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, 8534 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 8535 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 8536 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 8537 GIR_AddImm, /*InsnID*/0, /*Imm*/8, 8538 GIR_EraseFromParent, /*InsnID*/0, 8539 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8540 // GIR_Coverage, 3389, 8541 GIR_Done, 8542 // Label 592: @19138 8543 GIM_Try, /*On fail goto*//*Label 593*/ 19161, // Rule ID 3390 // 8544 GIM_CheckFeatures, GIFBS_IsBE, 8545 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 8546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8548 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src) => (REV64v8i16:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src) 8549 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, 8550 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8551 // GIR_Coverage, 3390, 8552 GIR_Done, 8553 // Label 593: @19161 8554 GIM_Try, /*On fail goto*//*Label 594*/ 19184, // Rule ID 3391 // 8555 GIM_CheckFeatures, GIFBS_IsBE, 8556 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 8557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8558 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8559 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src) => (REV32v8i16:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src) 8560 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, 8561 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8562 // GIR_Coverage, 3391, 8563 GIR_Done, 8564 // Label 594: @19184 8565 GIM_Try, /*On fail goto*//*Label 595*/ 19207, // Rule ID 3392 // 8566 GIM_CheckFeatures, GIFBS_IsBE, 8567 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 8568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8569 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8570 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src) => (REV16v16i8:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src) 8571 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, 8572 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8573 // GIR_Coverage, 3392, 8574 GIR_Done, 8575 // Label 595: @19207 8576 GIM_Try, /*On fail goto*//*Label 596*/ 19230, // Rule ID 3393 // 8577 GIM_CheckFeatures, GIFBS_IsBE, 8578 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 8579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8581 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src) => (REV64v8i16:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src) 8582 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, 8583 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8584 // GIR_Coverage, 3393, 8585 GIR_Done, 8586 // Label 596: @19230 8587 GIM_Try, /*On fail goto*//*Label 597*/ 19253, // Rule ID 3394 // 8588 GIM_CheckFeatures, GIFBS_IsBE, 8589 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 8590 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8591 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8592 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src) => (REV32v8i16:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src) 8593 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, 8594 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8595 // GIR_Coverage, 3394, 8596 GIR_Done, 8597 // Label 597: @19253 8598 GIM_Try, /*On fail goto*//*Label 598*/ 19285, // Rule ID 3395 // 8599 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 8600 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8602 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v8i16] }:$src 8603 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8606 GIR_EraseFromParent, /*InsnID*/0, 8607 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8608 // GIR_Coverage, 3395, 8609 GIR_Done, 8610 // Label 598: @19285 8611 GIM_Try, /*On fail goto*//*Label 599*/ 19319, // Rule ID 3396 // 8612 GIM_CheckFeatures, GIFBS_IsLE, 8613 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 8614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8616 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v8f16] }:$src 8617 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8620 GIR_EraseFromParent, /*InsnID*/0, 8621 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8622 // GIR_Coverage, 3396, 8623 GIR_Done, 8624 // Label 599: @19319 8625 GIM_Try, /*On fail goto*//*Label 600*/ 19353, // Rule ID 3397 // 8626 GIM_CheckFeatures, GIFBS_IsLE, 8627 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 8628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8630 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v8f16] }:$src 8631 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8632 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8633 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8634 GIR_EraseFromParent, /*InsnID*/0, 8635 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8636 // GIR_Coverage, 3397, 8637 GIR_Done, 8638 // Label 600: @19353 8639 GIM_Try, /*On fail goto*//*Label 601*/ 19387, // Rule ID 3398 // 8640 GIM_CheckFeatures, GIFBS_IsLE, 8641 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 8642 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8643 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8644 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v8f16] }:$src 8645 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8646 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8647 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8648 GIR_EraseFromParent, /*InsnID*/0, 8649 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8650 // GIR_Coverage, 3398, 8651 GIR_Done, 8652 // Label 601: @19387 8653 GIM_Try, /*On fail goto*//*Label 602*/ 19421, // Rule ID 3399 // 8654 GIM_CheckFeatures, GIFBS_IsLE, 8655 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 8656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8658 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v8f16] }:$src 8659 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8660 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8661 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8662 GIR_EraseFromParent, /*InsnID*/0, 8663 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8664 // GIR_Coverage, 3399, 8665 GIR_Done, 8666 // Label 602: @19421 8667 GIM_Try, /*On fail goto*//*Label 603*/ 19455, // Rule ID 3400 // 8668 GIM_CheckFeatures, GIFBS_IsLE, 8669 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 8670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8672 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v8f16] }:$src 8673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8676 GIR_EraseFromParent, /*InsnID*/0, 8677 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8678 // GIR_Coverage, 3400, 8679 GIR_Done, 8680 // Label 603: @19455 8681 GIM_Try, /*On fail goto*//*Label 604*/ 19489, // Rule ID 3401 // 8682 GIM_CheckFeatures, GIFBS_IsLE, 8683 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 8684 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8685 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8686 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v8f16] }:$src 8687 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8690 GIR_EraseFromParent, /*InsnID*/0, 8691 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8692 // GIR_Coverage, 3401, 8693 GIR_Done, 8694 // Label 604: @19489 8695 GIM_Try, /*On fail goto*//*Label 605*/ 19560, // Rule ID 3402 // 8696 GIM_CheckFeatures, GIFBS_IsBE, 8697 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 8698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8700 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v8f16] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) 8701 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, 8702 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, 8703 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, 8704 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 8705 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 8706 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 8707 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, 8708 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 8709 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 8710 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 8711 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, 8712 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 8713 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 8714 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 8715 GIR_AddImm, /*InsnID*/0, /*Imm*/8, 8716 GIR_EraseFromParent, /*InsnID*/0, 8717 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8718 // GIR_Coverage, 3402, 8719 GIR_Done, 8720 // Label 605: @19560 8721 GIM_Try, /*On fail goto*//*Label 606*/ 19583, // Rule ID 3403 // 8722 GIM_CheckFeatures, GIFBS_IsBE, 8723 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 8724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8726 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src) => (REV64v8i16:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src) 8727 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, 8728 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8729 // GIR_Coverage, 3403, 8730 GIR_Done, 8731 // Label 606: @19583 8732 GIM_Try, /*On fail goto*//*Label 607*/ 19606, // Rule ID 3404 // 8733 GIM_CheckFeatures, GIFBS_IsBE, 8734 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 8735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8737 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src) => (REV32v8i16:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src) 8738 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, 8739 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8740 // GIR_Coverage, 3404, 8741 GIR_Done, 8742 // Label 607: @19606 8743 GIM_Try, /*On fail goto*//*Label 608*/ 19629, // Rule ID 3405 // 8744 GIM_CheckFeatures, GIFBS_IsBE, 8745 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 8746 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8747 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8748 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src) => (REV16v16i8:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src) 8749 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, 8750 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8751 // GIR_Coverage, 3405, 8752 GIR_Done, 8753 // Label 608: @19629 8754 GIM_Try, /*On fail goto*//*Label 609*/ 19652, // Rule ID 3406 // 8755 GIM_CheckFeatures, GIFBS_IsBE, 8756 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 8757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8759 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src) => (REV64v8i16:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src) 8760 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, 8761 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8762 // GIR_Coverage, 3406, 8763 GIR_Done, 8764 // Label 609: @19652 8765 GIM_Try, /*On fail goto*//*Label 610*/ 19675, // Rule ID 3407 // 8766 GIM_CheckFeatures, GIFBS_IsBE, 8767 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 8768 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8769 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8770 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src) => (REV32v8i16:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src) 8771 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, 8772 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8773 // GIR_Coverage, 3407, 8774 GIR_Done, 8775 // Label 610: @19675 8776 GIM_Try, /*On fail goto*//*Label 611*/ 19707, // Rule ID 3408 // 8777 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 8778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8780 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v8f16] }:$src 8781 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8782 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8783 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8784 GIR_EraseFromParent, /*InsnID*/0, 8785 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8786 // GIR_Coverage, 3408, 8787 GIR_Done, 8788 // Label 611: @19707 8789 GIM_Reject, 8790 // Label 386: @19708 8791 GIM_Try, /*On fail goto*//*Label 612*/ 19742, // Rule ID 3409 // 8792 GIM_CheckFeatures, GIFBS_IsLE, 8793 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 8794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8796 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v16i8] }:$src 8797 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8798 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8800 GIR_EraseFromParent, /*InsnID*/0, 8801 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8802 // GIR_Coverage, 3409, 8803 GIR_Done, 8804 // Label 612: @19742 8805 GIM_Try, /*On fail goto*//*Label 613*/ 19776, // Rule ID 3410 // 8806 GIM_CheckFeatures, GIFBS_IsLE, 8807 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 8808 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8809 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8810 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v16i8] }:$src 8811 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8814 GIR_EraseFromParent, /*InsnID*/0, 8815 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8816 // GIR_Coverage, 3410, 8817 GIR_Done, 8818 // Label 613: @19776 8819 GIM_Try, /*On fail goto*//*Label 614*/ 19810, // Rule ID 3411 // 8820 GIM_CheckFeatures, GIFBS_IsLE, 8821 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 8822 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8823 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8824 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v16i8] }:$src 8825 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8826 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8828 GIR_EraseFromParent, /*InsnID*/0, 8829 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8830 // GIR_Coverage, 3411, 8831 GIR_Done, 8832 // Label 614: @19810 8833 GIM_Try, /*On fail goto*//*Label 615*/ 19844, // Rule ID 3412 // 8834 GIM_CheckFeatures, GIFBS_IsLE, 8835 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 8836 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8838 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v16i8] }:$src 8839 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8840 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8841 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8842 GIR_EraseFromParent, /*InsnID*/0, 8843 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8844 // GIR_Coverage, 3412, 8845 GIR_Done, 8846 // Label 615: @19844 8847 GIM_Try, /*On fail goto*//*Label 616*/ 19878, // Rule ID 3413 // 8848 GIM_CheckFeatures, GIFBS_IsLE, 8849 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 8850 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8852 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v16i8] }:$src 8853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8854 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8855 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8856 GIR_EraseFromParent, /*InsnID*/0, 8857 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8858 // GIR_Coverage, 3413, 8859 GIR_Done, 8860 // Label 616: @19878 8861 GIM_Try, /*On fail goto*//*Label 617*/ 19912, // Rule ID 3414 // 8862 GIM_CheckFeatures, GIFBS_IsLE, 8863 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 8864 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8865 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8866 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v16i8] }:$src 8867 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8868 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8869 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8870 GIR_EraseFromParent, /*InsnID*/0, 8871 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8872 // GIR_Coverage, 3414, 8873 GIR_Done, 8874 // Label 617: @19912 8875 GIM_Try, /*On fail goto*//*Label 618*/ 19946, // Rule ID 3415 // 8876 GIM_CheckFeatures, GIFBS_IsLE, 8877 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 8878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8879 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8880 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v16i8] }:$src 8881 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8883 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8884 GIR_EraseFromParent, /*InsnID*/0, 8885 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/30, 8886 // GIR_Coverage, 3415, 8887 GIR_Done, 8888 // Label 618: @19946 8889 GIM_Try, /*On fail goto*//*Label 619*/ 20017, // Rule ID 3416 // 8890 GIM_CheckFeatures, GIFBS_IsBE, 8891 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, 8892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8894 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v16i8] } (REV64v16i8:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v16i8:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) 8895 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, 8896 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, 8897 GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v16i8, 8898 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 8899 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 8900 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 8901 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v16i8, 8902 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 8903 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 8904 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 8905 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, 8906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 8907 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 8908 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 8909 GIR_AddImm, /*InsnID*/0, /*Imm*/8, 8910 GIR_EraseFromParent, /*InsnID*/0, 8911 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8912 // GIR_Coverage, 3416, 8913 GIR_Done, 8914 // Label 619: @20017 8915 GIM_Try, /*On fail goto*//*Label 620*/ 20040, // Rule ID 3417 // 8916 GIM_CheckFeatures, GIFBS_IsBE, 8917 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 8918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8920 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src) => (REV64v16i8:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src) 8921 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v16i8, 8922 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8923 // GIR_Coverage, 3417, 8924 GIR_Done, 8925 // Label 620: @20040 8926 GIM_Try, /*On fail goto*//*Label 621*/ 20063, // Rule ID 3418 // 8927 GIM_CheckFeatures, GIFBS_IsBE, 8928 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 8929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8931 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src) => (REV32v16i8:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src) 8932 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v16i8, 8933 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8934 // GIR_Coverage, 3418, 8935 GIR_Done, 8936 // Label 621: @20063 8937 GIM_Try, /*On fail goto*//*Label 622*/ 20086, // Rule ID 3419 // 8938 GIM_CheckFeatures, GIFBS_IsBE, 8939 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 8940 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8941 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8942 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src) => (REV16v16i8:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src) 8943 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, 8944 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8945 // GIR_Coverage, 3419, 8946 GIR_Done, 8947 // Label 622: @20086 8948 GIM_Try, /*On fail goto*//*Label 623*/ 20109, // Rule ID 3420 // 8949 GIM_CheckFeatures, GIFBS_IsBE, 8950 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 8951 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8952 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8953 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src) => (REV64v16i8:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src) 8954 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v16i8, 8955 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8956 // GIR_Coverage, 3420, 8957 GIR_Done, 8958 // Label 623: @20109 8959 GIM_Try, /*On fail goto*//*Label 624*/ 20132, // Rule ID 3421 // 8960 GIM_CheckFeatures, GIFBS_IsBE, 8961 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 8962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8963 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8964 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src) => (REV32v16i8:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src) 8965 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v16i8, 8966 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8967 // GIR_Coverage, 3421, 8968 GIR_Done, 8969 // Label 624: @20132 8970 GIM_Try, /*On fail goto*//*Label 625*/ 20155, // Rule ID 3422 // 8971 GIM_CheckFeatures, GIFBS_IsBE, 8972 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 8973 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 8974 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 8975 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src) => (REV16v16i8:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src) 8976 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, 8977 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8978 // GIR_Coverage, 3422, 8979 GIR_Done, 8980 // Label 625: @20155 8981 GIM_Reject, 8982 // Label 387: @20156 8983 GIM_Reject, 8984 // Label 9: @20157 8985 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 11, /*)*//*default:*//*Label 637*/ 22212, 8986 /*GILLT_s16*//*Label 626*/ 20174, 8987 /*GILLT_s32*//*Label 627*/ 20255, 8988 /*GILLT_s64*//*Label 628*/ 20740, 8989 /*GILLT_s128*//*Label 629*/ 21084, 8990 /*GILLT_v2s32*//*Label 630*/ 21196, 8991 /*GILLT_v2s64*//*Label 631*/ 21360, 8992 /*GILLT_v4s16*//*Label 632*/ 21524, 8993 /*GILLT_v4s32*//*Label 633*/ 21688, 8994 /*GILLT_v8s8*//*Label 634*/ 21852, 8995 /*GILLT_v8s16*//*Label 635*/ 21950, 8996 /*GILLT_v16s8*//*Label 636*/ 22114, 8997 // Label 626: @20174 8998 GIM_Try, /*On fail goto*//*Label 638*/ 20254, 8999 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9000 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9001 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 9002 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9003 GIM_Try, /*On fail goto*//*Label 639*/ 20222, // Rule ID 194 // 9004 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, 9005 // (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRHui:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) 9006 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHui, 9007 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9008 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9009 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9010 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9011 GIR_EraseFromParent, /*InsnID*/0, 9012 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9013 // GIR_Coverage, 194, 9014 GIR_Done, 9015 // Label 639: @20222 9016 GIM_Try, /*On fail goto*//*Label 640*/ 20253, // Rule ID 209 // 9017 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, 9018 // (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURHi:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) 9019 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHi, 9020 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9021 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9022 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9023 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9024 GIR_EraseFromParent, /*InsnID*/0, 9025 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9026 // GIR_Coverage, 209, 9027 GIR_Done, 9028 // Label 640: @20253 9029 GIM_Reject, 9030 // Label 638: @20254 9031 GIM_Reject, 9032 // Label 627: @20255 9033 GIM_Try, /*On fail goto*//*Label 641*/ 20301, // Rule ID 192 // 9034 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9035 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 9037 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9038 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, 9039 // (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) 9040 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWui, 9041 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9042 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9043 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9044 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9045 GIR_EraseFromParent, /*InsnID*/0, 9046 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9047 // GIR_Coverage, 192, 9048 GIR_Done, 9049 // Label 641: @20301 9050 GIM_Try, /*On fail goto*//*Label 642*/ 20347, // Rule ID 195 // 9051 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9052 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9053 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 9054 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9055 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, 9056 // (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRSui:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) 9057 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSui, 9058 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9059 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9060 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9061 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9062 GIR_EraseFromParent, /*InsnID*/0, 9063 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9064 // GIR_Coverage, 195, 9065 GIR_Done, 9066 // Label 642: @20347 9067 GIM_Try, /*On fail goto*//*Label 643*/ 20393, // Rule ID 207 // 9068 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9069 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9070 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 9071 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9072 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, 9073 // (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) 9074 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURWi, 9075 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9076 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9077 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9078 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9079 GIR_EraseFromParent, /*InsnID*/0, 9080 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9081 // GIR_Coverage, 207, 9082 GIR_Done, 9083 // Label 643: @20393 9084 GIM_Try, /*On fail goto*//*Label 644*/ 20439, // Rule ID 210 // 9085 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9086 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 9088 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9089 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, 9090 // (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURSi:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) 9091 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSi, 9092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9093 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9094 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9095 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9096 GIR_EraseFromParent, /*InsnID*/0, 9097 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9098 // GIR_Coverage, 210, 9099 GIR_Done, 9100 // Label 644: @20439 9101 GIM_Try, /*On fail goto*//*Label 645*/ 20489, // Rule ID 2041 // 9102 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9103 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 9104 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 9106 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9107 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, 9108 // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) 9109 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHui, 9110 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9111 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9112 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9113 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9114 GIR_EraseFromParent, /*InsnID*/0, 9115 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9116 // GIR_Coverage, 2041, 9117 GIR_Done, 9118 // Label 645: @20489 9119 GIM_Try, /*On fail goto*//*Label 646*/ 20539, // Rule ID 2042 // 9120 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9121 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 9122 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9123 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 9124 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9125 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, 9126 // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) 9127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, 9128 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9129 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9130 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9131 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9132 GIR_EraseFromParent, /*InsnID*/0, 9133 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9134 // GIR_Coverage, 2042, 9135 GIR_Done, 9136 // Label 646: @20539 9137 GIM_Try, /*On fail goto*//*Label 647*/ 20589, // Rule ID 2043 // 9138 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9139 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 9140 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9141 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 9142 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9143 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, 9144 // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) 9145 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, 9146 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9147 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9148 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9149 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9150 GIR_EraseFromParent, /*InsnID*/0, 9151 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9152 // GIR_Coverage, 2043, 9153 GIR_Done, 9154 // Label 647: @20589 9155 GIM_Try, /*On fail goto*//*Label 648*/ 20639, // Rule ID 2063 // 9156 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9157 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 9158 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 9160 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9161 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, 9162 // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 9163 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi, 9164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9165 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9166 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9167 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9168 GIR_EraseFromParent, /*InsnID*/0, 9169 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9170 // GIR_Coverage, 2063, 9171 GIR_Done, 9172 // Label 648: @20639 9173 GIM_Try, /*On fail goto*//*Label 649*/ 20689, // Rule ID 2064 // 9174 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9175 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 9176 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 9178 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9179 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, 9180 // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 9181 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, 9182 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9183 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9184 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9185 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9186 GIR_EraseFromParent, /*InsnID*/0, 9187 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9188 // GIR_Coverage, 2064, 9189 GIR_Done, 9190 // Label 649: @20689 9191 GIM_Try, /*On fail goto*//*Label 650*/ 20739, // Rule ID 2065 // 9192 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9193 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 9194 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 9196 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9197 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, 9198 // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 9199 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, 9200 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9201 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9202 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9203 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9204 GIR_EraseFromParent, /*InsnID*/0, 9205 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9206 // GIR_Coverage, 2065, 9207 GIR_Done, 9208 // Label 650: @20739 9209 GIM_Reject, 9210 // Label 628: @20740 9211 GIM_Try, /*On fail goto*//*Label 651*/ 21083, 9212 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9213 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9214 GIM_Try, /*On fail goto*//*Label 652*/ 20788, // Rule ID 191 // 9215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 9216 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9217 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, 9218 // (ld:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) 9219 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXui, 9220 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9221 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9222 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9223 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9224 GIR_EraseFromParent, /*InsnID*/0, 9225 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9226 // GIR_Coverage, 191, 9227 GIR_Done, 9228 // Label 652: @20788 9229 GIM_Try, /*On fail goto*//*Label 653*/ 20827, // Rule ID 196 // 9230 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 9231 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9232 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, 9233 // (ld:{ *:[f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) 9234 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, 9235 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9236 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9237 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9238 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9239 GIR_EraseFromParent, /*InsnID*/0, 9240 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9241 // GIR_Coverage, 196, 9242 GIR_Done, 9243 // Label 653: @20827 9244 GIM_Try, /*On fail goto*//*Label 654*/ 20866, // Rule ID 206 // 9245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 9246 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9247 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, 9248 // (ld:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) 9249 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURXi, 9250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9251 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9252 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9253 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9254 GIR_EraseFromParent, /*InsnID*/0, 9255 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9256 // GIR_Coverage, 206, 9257 GIR_Done, 9258 // Label 654: @20866 9259 GIM_Try, /*On fail goto*//*Label 655*/ 20905, // Rule ID 211 // 9260 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 9261 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9262 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, 9263 // (ld:{ *:[f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) 9264 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, 9265 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9266 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9267 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9268 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9269 GIR_EraseFromParent, /*InsnID*/0, 9270 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9271 // GIR_Coverage, 211, 9272 GIR_Done, 9273 // Label 655: @20905 9274 GIM_Try, /*On fail goto*//*Label 656*/ 20944, // Rule ID 2027 // 9275 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 9276 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9277 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, 9278 // (ld:{ *:[v1f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) 9279 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, 9280 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9281 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9282 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9283 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9284 GIR_EraseFromParent, /*InsnID*/0, 9285 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9286 // GIR_Coverage, 2027, 9287 GIR_Done, 9288 // Label 656: @20944 9289 GIM_Try, /*On fail goto*//*Label 657*/ 20983, // Rule ID 2028 // 9290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 9291 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9292 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, 9293 // (ld:{ *:[v1i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) 9294 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, 9295 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9296 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9297 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9298 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9299 GIR_EraseFromParent, /*InsnID*/0, 9300 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9301 // GIR_Coverage, 2028, 9302 GIR_Done, 9303 // Label 657: @20983 9304 GIM_Try, /*On fail goto*//*Label 658*/ 21022, // Rule ID 2054 // 9305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 9306 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9307 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, 9308 // (ld:{ *:[v1f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 9309 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, 9310 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9311 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9312 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9313 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9314 GIR_EraseFromParent, /*InsnID*/0, 9315 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9316 // GIR_Coverage, 2054, 9317 GIR_Done, 9318 // Label 658: @21022 9319 GIM_Try, /*On fail goto*//*Label 659*/ 21061, // Rule ID 2055 // 9320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 9321 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9322 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, 9323 // (ld:{ *:[v1i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 9324 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, 9325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9326 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9327 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9328 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9329 GIR_EraseFromParent, /*InsnID*/0, 9330 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9331 // GIR_Coverage, 2055, 9332 GIR_Done, 9333 // Label 659: @21061 9334 GIM_Try, /*On fail goto*//*Label 660*/ 21082, // Rule ID 3012 // 9335 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 9336 // MIs[0] Rn 9337 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 9338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 9339 // (ld:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev1d:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn) 9340 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev1d, 9341 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9342 // GIR_Coverage, 3012, 9343 GIR_Done, 9344 // Label 660: @21082 9345 GIM_Reject, 9346 // Label 651: @21083 9347 GIM_Reject, 9348 // Label 629: @21084 9349 GIM_Try, /*On fail goto*//*Label 661*/ 21195, 9350 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9351 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9352 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 9353 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9354 GIM_Try, /*On fail goto*//*Label 662*/ 21132, // Rule ID 197 // 9355 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, 9356 // (ld:{ *:[f128] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) 9357 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, 9358 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9359 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9360 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9361 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9362 GIR_EraseFromParent, /*InsnID*/0, 9363 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9364 // GIR_Coverage, 197, 9365 GIR_Done, 9366 // Label 662: @21132 9367 GIM_Try, /*On fail goto*//*Label 663*/ 21163, // Rule ID 212 // 9368 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, 9369 // (ld:{ *:[f128] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) 9370 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, 9371 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9372 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9373 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9374 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9375 GIR_EraseFromParent, /*InsnID*/0, 9376 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9377 // GIR_Coverage, 212, 9378 GIR_Done, 9379 // Label 663: @21163 9380 GIM_Try, /*On fail goto*//*Label 664*/ 21194, // Rule ID 2036 // 9381 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, 9382 // (ld:{ *:[f128] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) 9383 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, 9384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9385 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9386 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9387 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9388 GIR_EraseFromParent, /*InsnID*/0, 9389 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9390 // GIR_Coverage, 2036, 9391 GIR_Done, 9392 // Label 664: @21194 9393 GIM_Reject, 9394 // Label 661: @21195 9395 GIM_Reject, 9396 // Label 630: @21196 9397 GIM_Try, /*On fail goto*//*Label 665*/ 21359, 9398 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9399 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9400 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 9401 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9402 GIM_Try, /*On fail goto*//*Label 666*/ 21246, // Rule ID 2022 // 9403 GIM_CheckFeatures, GIFBS_IsLE, 9404 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, 9405 // (ld:{ *:[v2f32] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) 9406 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, 9407 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9408 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9409 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9410 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9411 GIR_EraseFromParent, /*InsnID*/0, 9412 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9413 // GIR_Coverage, 2022, 9414 GIR_Done, 9415 // Label 666: @21246 9416 GIM_Try, /*On fail goto*//*Label 667*/ 21279, // Rule ID 2025 // 9417 GIM_CheckFeatures, GIFBS_IsLE, 9418 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, 9419 // (ld:{ *:[v2i32] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) 9420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, 9421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9422 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9423 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9424 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9425 GIR_EraseFromParent, /*InsnID*/0, 9426 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9427 // GIR_Coverage, 2025, 9428 GIR_Done, 9429 // Label 667: @21279 9430 GIM_Try, /*On fail goto*//*Label 668*/ 21312, // Rule ID 2049 // 9431 GIM_CheckFeatures, GIFBS_IsLE, 9432 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, 9433 // (ld:{ *:[v2f32] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 9434 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, 9435 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9436 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9437 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9438 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9439 GIR_EraseFromParent, /*InsnID*/0, 9440 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9441 // GIR_Coverage, 2049, 9442 GIR_Done, 9443 // Label 668: @21312 9444 GIM_Try, /*On fail goto*//*Label 669*/ 21345, // Rule ID 2050 // 9445 GIM_CheckFeatures, GIFBS_IsLE, 9446 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, 9447 // (ld:{ *:[v2i32] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 9448 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, 9449 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9450 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9451 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9452 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9453 GIR_EraseFromParent, /*InsnID*/0, 9454 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9455 // GIR_Coverage, 2050, 9456 GIR_Done, 9457 // Label 669: @21345 9458 GIM_Try, /*On fail goto*//*Label 670*/ 21358, // Rule ID 3011 // 9459 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 9460 // (ld:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev2s:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn) 9461 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev2s, 9462 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9463 // GIR_Coverage, 3011, 9464 GIR_Done, 9465 // Label 670: @21358 9466 GIM_Reject, 9467 // Label 665: @21359 9468 GIM_Reject, 9469 // Label 631: @21360 9470 GIM_Try, /*On fail goto*//*Label 671*/ 21523, 9471 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9472 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 9474 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9475 GIM_Try, /*On fail goto*//*Label 672*/ 21410, // Rule ID 2030 // 9476 GIM_CheckFeatures, GIFBS_IsLE, 9477 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, 9478 // (ld:{ *:[v2f64] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) 9479 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, 9480 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9481 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9482 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9483 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9484 GIR_EraseFromParent, /*InsnID*/0, 9485 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9486 // GIR_Coverage, 2030, 9487 GIR_Done, 9488 // Label 672: @21410 9489 GIM_Try, /*On fail goto*//*Label 673*/ 21443, // Rule ID 2034 // 9490 GIM_CheckFeatures, GIFBS_IsLE, 9491 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, 9492 // (ld:{ *:[v2i64] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) 9493 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, 9494 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9495 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9496 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9497 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9498 GIR_EraseFromParent, /*InsnID*/0, 9499 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9500 // GIR_Coverage, 2034, 9501 GIR_Done, 9502 // Label 673: @21443 9503 GIM_Try, /*On fail goto*//*Label 674*/ 21476, // Rule ID 2056 // 9504 GIM_CheckFeatures, GIFBS_IsLE, 9505 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, 9506 // (ld:{ *:[v2f64] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 9507 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, 9508 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9509 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9510 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9511 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9512 GIR_EraseFromParent, /*InsnID*/0, 9513 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9514 // GIR_Coverage, 2056, 9515 GIR_Done, 9516 // Label 674: @21476 9517 GIM_Try, /*On fail goto*//*Label 675*/ 21509, // Rule ID 2057 // 9518 GIM_CheckFeatures, GIFBS_IsLE, 9519 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, 9520 // (ld:{ *:[v2i64] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 9521 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, 9522 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9523 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9524 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9525 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9526 GIR_EraseFromParent, /*InsnID*/0, 9527 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9528 // GIR_Coverage, 2057, 9529 GIR_Done, 9530 // Label 675: @21509 9531 GIM_Try, /*On fail goto*//*Label 676*/ 21522, // Rule ID 3008 // 9532 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 9533 // (ld:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev2d:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn) 9534 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev2d, 9535 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9536 // GIR_Coverage, 3008, 9537 GIR_Done, 9538 // Label 676: @21522 9539 GIM_Reject, 9540 // Label 671: @21523 9541 GIM_Reject, 9542 // Label 632: @21524 9543 GIM_Try, /*On fail goto*//*Label 677*/ 21687, 9544 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9545 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 9547 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9548 GIM_Try, /*On fail goto*//*Label 678*/ 21574, // Rule ID 2024 // 9549 GIM_CheckFeatures, GIFBS_IsLE, 9550 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, 9551 // (ld:{ *:[v4i16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) 9552 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, 9553 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9554 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9555 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9556 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9557 GIR_EraseFromParent, /*InsnID*/0, 9558 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9559 // GIR_Coverage, 2024, 9560 GIR_Done, 9561 // Label 678: @21574 9562 GIM_Try, /*On fail goto*//*Label 679*/ 21607, // Rule ID 2026 // 9563 GIM_CheckFeatures, GIFBS_IsLE, 9564 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, 9565 // (ld:{ *:[v4f16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) 9566 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, 9567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9568 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9569 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9570 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9571 GIR_EraseFromParent, /*InsnID*/0, 9572 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9573 // GIR_Coverage, 2026, 9574 GIR_Done, 9575 // Label 679: @21607 9576 GIM_Try, /*On fail goto*//*Label 680*/ 21640, // Rule ID 2051 // 9577 GIM_CheckFeatures, GIFBS_IsLE, 9578 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, 9579 // (ld:{ *:[v4i16] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 9580 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, 9581 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9582 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9583 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9584 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9585 GIR_EraseFromParent, /*InsnID*/0, 9586 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9587 // GIR_Coverage, 2051, 9588 GIR_Done, 9589 // Label 680: @21640 9590 GIM_Try, /*On fail goto*//*Label 681*/ 21673, // Rule ID 2053 // 9591 GIM_CheckFeatures, GIFBS_IsLE, 9592 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, 9593 // (ld:{ *:[v4f16] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 9594 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, 9595 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9596 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9597 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9598 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9599 GIR_EraseFromParent, /*InsnID*/0, 9600 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9601 // GIR_Coverage, 2053, 9602 GIR_Done, 9603 // Label 681: @21673 9604 GIM_Try, /*On fail goto*//*Label 682*/ 21686, // Rule ID 3010 // 9605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 9606 // (ld:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev4h:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn) 9607 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev4h, 9608 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9609 // GIR_Coverage, 3010, 9610 GIR_Done, 9611 // Label 682: @21686 9612 GIM_Reject, 9613 // Label 677: @21687 9614 GIM_Reject, 9615 // Label 633: @21688 9616 GIM_Try, /*On fail goto*//*Label 683*/ 21851, 9617 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9618 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 9620 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9621 GIM_Try, /*On fail goto*//*Label 684*/ 21738, // Rule ID 2029 // 9622 GIM_CheckFeatures, GIFBS_IsLE, 9623 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, 9624 // (ld:{ *:[v4f32] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) 9625 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, 9626 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9627 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9628 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9629 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9630 GIR_EraseFromParent, /*InsnID*/0, 9631 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9632 // GIR_Coverage, 2029, 9633 GIR_Done, 9634 // Label 684: @21738 9635 GIM_Try, /*On fail goto*//*Label 685*/ 21771, // Rule ID 2033 // 9636 GIM_CheckFeatures, GIFBS_IsLE, 9637 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, 9638 // (ld:{ *:[v4i32] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) 9639 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, 9640 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9641 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9642 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9643 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9644 GIR_EraseFromParent, /*InsnID*/0, 9645 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9646 // GIR_Coverage, 2033, 9647 GIR_Done, 9648 // Label 685: @21771 9649 GIM_Try, /*On fail goto*//*Label 686*/ 21804, // Rule ID 2058 // 9650 GIM_CheckFeatures, GIFBS_IsLE, 9651 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, 9652 // (ld:{ *:[v4f32] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 9653 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, 9654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9655 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9656 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9657 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9658 GIR_EraseFromParent, /*InsnID*/0, 9659 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9660 // GIR_Coverage, 2058, 9661 GIR_Done, 9662 // Label 686: @21804 9663 GIM_Try, /*On fail goto*//*Label 687*/ 21837, // Rule ID 2059 // 9664 GIM_CheckFeatures, GIFBS_IsLE, 9665 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, 9666 // (ld:{ *:[v4i32] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 9667 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, 9668 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9669 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9670 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9671 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9672 GIR_EraseFromParent, /*InsnID*/0, 9673 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9674 // GIR_Coverage, 2059, 9675 GIR_Done, 9676 // Label 687: @21837 9677 GIM_Try, /*On fail goto*//*Label 688*/ 21850, // Rule ID 3007 // 9678 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 9679 // (ld:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev4s:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn) 9680 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev4s, 9681 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9682 // GIR_Coverage, 3007, 9683 GIR_Done, 9684 // Label 688: @21850 9685 GIM_Reject, 9686 // Label 683: @21851 9687 GIM_Reject, 9688 // Label 634: @21852 9689 GIM_Try, /*On fail goto*//*Label 689*/ 21949, 9690 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9691 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9692 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 9693 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9694 GIM_Try, /*On fail goto*//*Label 690*/ 21902, // Rule ID 2023 // 9695 GIM_CheckFeatures, GIFBS_IsLE, 9696 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, 9697 // (ld:{ *:[v8i8] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) 9698 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, 9699 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9700 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9701 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9702 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9703 GIR_EraseFromParent, /*InsnID*/0, 9704 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9705 // GIR_Coverage, 2023, 9706 GIR_Done, 9707 // Label 690: @21902 9708 GIM_Try, /*On fail goto*//*Label 691*/ 21935, // Rule ID 2052 // 9709 GIM_CheckFeatures, GIFBS_IsLE, 9710 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, 9711 // (ld:{ *:[v8i8] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 9712 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, 9713 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9714 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9715 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9716 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9717 GIR_EraseFromParent, /*InsnID*/0, 9718 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9719 // GIR_Coverage, 2052, 9720 GIR_Done, 9721 // Label 691: @21935 9722 GIM_Try, /*On fail goto*//*Label 692*/ 21948, // Rule ID 3009 // 9723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 9724 // (ld:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev8b:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn) 9725 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev8b, 9726 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9727 // GIR_Coverage, 3009, 9728 GIR_Done, 9729 // Label 692: @21948 9730 GIM_Reject, 9731 // Label 689: @21949 9732 GIM_Reject, 9733 // Label 635: @21950 9734 GIM_Try, /*On fail goto*//*Label 693*/ 22113, 9735 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9736 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 9738 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9739 GIM_Try, /*On fail goto*//*Label 694*/ 22000, // Rule ID 2032 // 9740 GIM_CheckFeatures, GIFBS_IsLE, 9741 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, 9742 // (ld:{ *:[v8i16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) 9743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, 9744 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9745 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9746 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9747 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9748 GIR_EraseFromParent, /*InsnID*/0, 9749 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9750 // GIR_Coverage, 2032, 9751 GIR_Done, 9752 // Label 694: @22000 9753 GIM_Try, /*On fail goto*//*Label 695*/ 22033, // Rule ID 2035 // 9754 GIM_CheckFeatures, GIFBS_IsLE, 9755 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, 9756 // (ld:{ *:[v8f16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) 9757 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, 9758 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9759 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9760 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9761 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9762 GIR_EraseFromParent, /*InsnID*/0, 9763 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9764 // GIR_Coverage, 2035, 9765 GIR_Done, 9766 // Label 695: @22033 9767 GIM_Try, /*On fail goto*//*Label 696*/ 22066, // Rule ID 2060 // 9768 GIM_CheckFeatures, GIFBS_IsLE, 9769 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, 9770 // (ld:{ *:[v8i16] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 9771 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, 9772 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9773 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9774 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9775 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9776 GIR_EraseFromParent, /*InsnID*/0, 9777 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9778 // GIR_Coverage, 2060, 9779 GIR_Done, 9780 // Label 696: @22066 9781 GIM_Try, /*On fail goto*//*Label 697*/ 22099, // Rule ID 2062 // 9782 GIM_CheckFeatures, GIFBS_IsLE, 9783 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, 9784 // (ld:{ *:[v8f16] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 9785 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, 9786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9787 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9788 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9789 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9790 GIR_EraseFromParent, /*InsnID*/0, 9791 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9792 // GIR_Coverage, 2062, 9793 GIR_Done, 9794 // Label 697: @22099 9795 GIM_Try, /*On fail goto*//*Label 698*/ 22112, // Rule ID 3006 // 9796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 9797 // (ld:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev8h:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn) 9798 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev8h, 9799 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9800 // GIR_Coverage, 3006, 9801 GIR_Done, 9802 // Label 698: @22112 9803 GIM_Reject, 9804 // Label 693: @22113 9805 GIM_Reject, 9806 // Label 636: @22114 9807 GIM_Try, /*On fail goto*//*Label 699*/ 22211, 9808 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 9809 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 9811 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9812 GIM_Try, /*On fail goto*//*Label 700*/ 22164, // Rule ID 2031 // 9813 GIM_CheckFeatures, GIFBS_IsLE, 9814 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, 9815 // (ld:{ *:[v16i8] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) 9816 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, 9817 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9818 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9819 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9820 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9821 GIR_EraseFromParent, /*InsnID*/0, 9822 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9823 // GIR_Coverage, 2031, 9824 GIR_Done, 9825 // Label 700: @22164 9826 GIM_Try, /*On fail goto*//*Label 701*/ 22197, // Rule ID 2061 // 9827 GIM_CheckFeatures, GIFBS_IsLE, 9828 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, 9829 // (ld:{ *:[v16i8] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 9830 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, 9831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9832 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9833 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9834 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9835 GIR_EraseFromParent, /*InsnID*/0, 9836 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9837 // GIR_Coverage, 2061, 9838 GIR_Done, 9839 // Label 701: @22197 9840 GIM_Try, /*On fail goto*//*Label 702*/ 22210, // Rule ID 3005 // 9841 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 9842 // (ld:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev16b:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn) 9843 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev16b, 9844 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9845 // GIR_Coverage, 3005, 9846 GIR_Done, 9847 // Label 702: @22210 9848 GIM_Reject, 9849 // Label 699: @22211 9850 GIM_Reject, 9851 // Label 637: @22212 9852 GIM_Reject, 9853 // Label 10: @22213 9854 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 705*/ 22683, 9855 /*GILLT_s32*//*Label 703*/ 22221, 9856 /*GILLT_s64*//*Label 704*/ 22406, 9857 // Label 703: @22221 9858 GIM_Try, /*On fail goto*//*Label 706*/ 22267, // Rule ID 200 // 9859 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 9860 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 9862 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9863 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, 9864 // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDRSHWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) 9865 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHWui, 9866 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9867 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9868 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9869 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9870 GIR_EraseFromParent, /*InsnID*/0, 9871 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9872 // GIR_Coverage, 200, 9873 GIR_Done, 9874 // Label 706: @22267 9875 GIM_Try, /*On fail goto*//*Label 707*/ 22313, // Rule ID 202 // 9876 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 9877 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 9879 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9880 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, 9881 // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDRSBWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) 9882 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBWui, 9883 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9884 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9885 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9886 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9887 GIR_EraseFromParent, /*InsnID*/0, 9888 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9889 // GIR_Coverage, 202, 9890 GIR_Done, 9891 // Label 707: @22313 9892 GIM_Try, /*On fail goto*//*Label 708*/ 22359, // Rule ID 215 // 9893 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 9894 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9895 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 9896 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9897 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, 9898 // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDURSHWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) 9899 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSHWi, 9900 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9901 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9902 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9903 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9904 GIR_EraseFromParent, /*InsnID*/0, 9905 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9906 // GIR_Coverage, 215, 9907 GIR_Done, 9908 // Label 708: @22359 9909 GIM_Try, /*On fail goto*//*Label 709*/ 22405, // Rule ID 217 // 9910 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 9911 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 9913 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9914 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, 9915 // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDURSBWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) 9916 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSBWi, 9917 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9918 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9919 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9920 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9921 GIR_EraseFromParent, /*InsnID*/0, 9922 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9923 // GIR_Coverage, 217, 9924 GIR_Done, 9925 // Label 709: @22405 9926 GIM_Reject, 9927 // Label 704: @22406 9928 GIM_Try, /*On fail goto*//*Label 710*/ 22452, // Rule ID 201 // 9929 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 9930 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 9932 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9933 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, 9934 // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDRSHXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) 9935 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHXui, 9936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9937 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9938 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9939 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9940 GIR_EraseFromParent, /*InsnID*/0, 9941 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9942 // GIR_Coverage, 201, 9943 GIR_Done, 9944 // Label 710: @22452 9945 GIM_Try, /*On fail goto*//*Label 711*/ 22498, // Rule ID 203 // 9946 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 9947 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 9949 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9950 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, 9951 // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDRSBXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) 9952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBXui, 9953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9954 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9955 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9956 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9957 GIR_EraseFromParent, /*InsnID*/0, 9958 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9959 // GIR_Coverage, 203, 9960 GIR_Done, 9961 // Label 711: @22498 9962 GIM_Try, /*On fail goto*//*Label 712*/ 22544, // Rule ID 204 // 9963 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 9964 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9965 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 9966 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9967 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, 9968 // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LDRSWui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) 9969 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSWui, 9970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9971 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9972 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9973 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9974 GIR_EraseFromParent, /*InsnID*/0, 9975 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9976 // GIR_Coverage, 204, 9977 GIR_Done, 9978 // Label 712: @22544 9979 GIM_Try, /*On fail goto*//*Label 713*/ 22590, // Rule ID 216 // 9980 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 9981 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 9983 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 9984 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, 9985 // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDURSHXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) 9986 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSHXi, 9987 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 9988 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 9989 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 9990 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9991 GIR_EraseFromParent, /*InsnID*/0, 9992 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9993 // GIR_Coverage, 216, 9994 GIR_Done, 9995 // Label 713: @22590 9996 GIM_Try, /*On fail goto*//*Label 714*/ 22636, // Rule ID 218 // 9997 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 9998 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 9999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 10000 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10001 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, 10002 // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDURSBXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) 10003 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSBXi, 10004 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10005 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10006 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10007 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10008 GIR_EraseFromParent, /*InsnID*/0, 10009 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10010 // GIR_Coverage, 218, 10011 GIR_Done, 10012 // Label 714: @22636 10013 GIM_Try, /*On fail goto*//*Label 715*/ 22682, // Rule ID 219 // 10014 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 10015 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 10016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 10017 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10018 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, 10019 // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LDURSWi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) 10020 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSWi, 10021 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10022 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10023 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10024 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10025 GIR_EraseFromParent, /*InsnID*/0, 10026 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10027 // GIR_Coverage, 219, 10028 GIR_Done, 10029 // Label 715: @22682 10030 GIM_Reject, 10031 // Label 705: @22683 10032 GIM_Reject, 10033 // Label 11: @22684 10034 GIM_Try, /*On fail goto*//*Label 716*/ 23035, 10035 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 10036 GIM_Try, /*On fail goto*//*Label 717*/ 22736, // Rule ID 198 // 10037 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 10038 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 10039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 10040 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10041 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, 10042 // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) 10043 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHui, 10044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10045 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10046 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10047 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10048 GIR_EraseFromParent, /*InsnID*/0, 10049 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10050 // GIR_Coverage, 198, 10051 GIR_Done, 10052 // Label 717: @22736 10053 GIM_Try, /*On fail goto*//*Label 718*/ 22782, // Rule ID 199 // 10054 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 10055 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 10056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 10057 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10058 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, 10059 // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) 10060 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, 10061 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10062 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10063 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10064 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10065 GIR_EraseFromParent, /*InsnID*/0, 10066 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10067 // GIR_Coverage, 199, 10068 GIR_Done, 10069 // Label 718: @22782 10070 GIM_Try, /*On fail goto*//*Label 719*/ 22828, // Rule ID 213 // 10071 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 10072 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 10073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 10074 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10075 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, 10076 // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) 10077 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi, 10078 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10079 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10080 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10081 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10082 GIR_EraseFromParent, /*InsnID*/0, 10083 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10084 // GIR_Coverage, 213, 10085 GIR_Done, 10086 // Label 719: @22828 10087 GIM_Try, /*On fail goto*//*Label 720*/ 22908, 10088 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 10089 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 10090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 10091 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10092 GIM_Try, /*On fail goto*//*Label 721*/ 22876, // Rule ID 214 // 10093 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, 10094 // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) 10095 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, 10096 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10097 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10098 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10099 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10100 GIR_EraseFromParent, /*InsnID*/0, 10101 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10102 // GIR_Coverage, 214, 10103 GIR_Done, 10104 // Label 721: @22876 10105 GIM_Try, /*On fail goto*//*Label 722*/ 22907, // Rule ID 2039 // 10106 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, 10107 // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) 10108 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, 10109 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10110 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10111 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10112 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10113 GIR_EraseFromParent, /*InsnID*/0, 10114 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10115 // GIR_Coverage, 2039, 10116 GIR_Done, 10117 // Label 722: @22907 10118 GIM_Reject, 10119 // Label 720: @22908 10120 GIM_Try, /*On fail goto*//*Label 723*/ 22954, // Rule ID 2070 // 10121 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 10122 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 10123 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 10124 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10125 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, 10126 // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 10127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi, 10128 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10129 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10130 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10131 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10132 GIR_EraseFromParent, /*InsnID*/0, 10133 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10134 // GIR_Coverage, 2070, 10135 GIR_Done, 10136 // Label 723: @22954 10137 GIM_Try, /*On fail goto*//*Label 724*/ 23034, 10138 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 10139 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 10140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 10141 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10142 GIM_Try, /*On fail goto*//*Label 725*/ 23002, // Rule ID 2071 // 10143 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, 10144 // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 10145 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, 10146 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10147 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10148 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10149 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10150 GIR_EraseFromParent, /*InsnID*/0, 10151 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10152 // GIR_Coverage, 2071, 10153 GIR_Done, 10154 // Label 725: @23002 10155 GIM_Try, /*On fail goto*//*Label 726*/ 23033, // Rule ID 2072 // 10156 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, 10157 // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 10158 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, 10159 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10160 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10161 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10162 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10163 GIR_EraseFromParent, /*InsnID*/0, 10164 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10165 // GIR_Coverage, 2072, 10166 GIR_Done, 10167 // Label 726: @23033 10168 GIM_Reject, 10169 // Label 724: @23034 10170 GIM_Reject, 10171 // Label 716: @23035 10172 GIM_Reject, 10173 // Label 12: @23036 10174 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 11, /*)*//*default:*//*Label 738*/ 24934, 10175 /*GILLT_s16*//*Label 727*/ 23053, 10176 /*GILLT_s32*//*Label 728*/ 23130, 10177 /*GILLT_s64*//*Label 729*/ 23295, 10178 /*GILLT_s128*//*Label 730*/ 23633, 10179 /*GILLT_v2s32*//*Label 731*/ 23741, 10180 /*GILLT_v2s64*//*Label 732*/ 23929, 10181 /*GILLT_v4s16*//*Label 733*/ 24158, 10182 /*GILLT_v4s32*//*Label 734*/ 24346, 10183 /*GILLT_v8s8*//*Label 735*/ 24534, 10184 /*GILLT_v8s16*//*Label 736*/ 24640, 10185 /*GILLT_v16s8*//*Label 737*/ 24828, 10186 // Label 727: @23053 10187 GIM_Try, /*On fail goto*//*Label 739*/ 23129, 10188 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 10189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 10190 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10191 GIM_Try, /*On fail goto*//*Label 740*/ 23097, // Rule ID 240 // 10192 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, 10193 // (st FPR16Op:{ *:[f16] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRHui FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) 10194 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHui, 10195 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10196 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10197 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10198 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10199 GIR_EraseFromParent, /*InsnID*/0, 10200 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10201 // GIR_Coverage, 240, 10202 GIR_Done, 10203 // Label 740: @23097 10204 GIM_Try, /*On fail goto*//*Label 741*/ 23128, // Rule ID 248 // 10205 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, 10206 // (st FPR16Op:{ *:[f16] }:$Rt, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURHi FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) 10207 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURHi, 10208 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10209 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10210 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10211 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10212 GIR_EraseFromParent, /*InsnID*/0, 10213 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10214 // GIR_Coverage, 248, 10215 GIR_Done, 10216 // Label 741: @23128 10217 GIM_Reject, 10218 // Label 739: @23129 10219 GIM_Reject, 10220 // Label 728: @23130 10221 GIM_Try, /*On fail goto*//*Label 742*/ 23294, 10222 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 10223 GIM_Try, /*On fail goto*//*Label 743*/ 23175, // Rule ID 238 // 10224 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 10225 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10226 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, 10227 // (st GPR32z:{ *:[i32] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRWui GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) 10228 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWui, 10229 GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::WZR, // Rt 10230 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10231 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10232 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10233 GIR_EraseFromParent, /*InsnID*/0, 10234 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10235 // GIR_Coverage, 238, 10236 GIR_Done, 10237 // Label 743: @23175 10238 GIM_Try, /*On fail goto*//*Label 744*/ 23214, // Rule ID 241 // 10239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 10240 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10241 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, 10242 // (st FPR32Op:{ *:[f32] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRSui FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) 10243 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRSui, 10244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10245 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10246 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10247 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10248 GIR_EraseFromParent, /*InsnID*/0, 10249 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10250 // GIR_Coverage, 241, 10251 GIR_Done, 10252 // Label 744: @23214 10253 GIM_Try, /*On fail goto*//*Label 745*/ 23254, // Rule ID 246 // 10254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 10255 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10256 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, 10257 // (st GPR32z:{ *:[i32] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURWi GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) 10258 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURWi, 10259 GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::WZR, // Rt 10260 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10261 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10262 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10263 GIR_EraseFromParent, /*InsnID*/0, 10264 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10265 // GIR_Coverage, 246, 10266 GIR_Done, 10267 // Label 745: @23254 10268 GIM_Try, /*On fail goto*//*Label 746*/ 23293, // Rule ID 249 // 10269 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 10270 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10271 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, 10272 // (st FPR32Op:{ *:[f32] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURSi FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) 10273 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURSi, 10274 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10275 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10276 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10277 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10278 GIR_EraseFromParent, /*InsnID*/0, 10279 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10280 // GIR_Coverage, 249, 10281 GIR_Done, 10282 // Label 746: @23293 10283 GIM_Reject, 10284 // Label 742: @23294 10285 GIM_Reject, 10286 // Label 729: @23295 10287 GIM_Try, /*On fail goto*//*Label 747*/ 23632, 10288 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 10289 GIM_Try, /*On fail goto*//*Label 748*/ 23340, // Rule ID 237 // 10290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 10291 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10292 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, 10293 // (st GPR64z:{ *:[i64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRXui GPR64z:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) 10294 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXui, 10295 GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::XZR, // Rt 10296 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10297 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10298 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10299 GIR_EraseFromParent, /*InsnID*/0, 10300 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10301 // GIR_Coverage, 237, 10302 GIR_Done, 10303 // Label 748: @23340 10304 GIM_Try, /*On fail goto*//*Label 749*/ 23379, // Rule ID 242 // 10305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 10306 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10307 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, 10308 // (st FPR64Op:{ *:[f64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) 10309 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, 10310 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10311 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10312 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10313 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10314 GIR_EraseFromParent, /*InsnID*/0, 10315 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10316 // GIR_Coverage, 242, 10317 GIR_Done, 10318 // Label 749: @23379 10319 GIM_Try, /*On fail goto*//*Label 750*/ 23418, // Rule ID 2127 // 10320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 10321 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10322 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, 10323 // (st FPR64:{ *:[v1i64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) 10324 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, 10325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10326 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10327 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10328 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10329 GIR_EraseFromParent, /*InsnID*/0, 10330 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10331 // GIR_Coverage, 2127, 10332 GIR_Done, 10333 // Label 750: @23418 10334 GIM_Try, /*On fail goto*//*Label 751*/ 23457, // Rule ID 2128 // 10335 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 10336 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10337 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, 10338 // (st FPR64:{ *:[v1f64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) 10339 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, 10340 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10341 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10342 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10343 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10344 GIR_EraseFromParent, /*InsnID*/0, 10345 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10346 // GIR_Coverage, 2128, 10347 GIR_Done, 10348 // Label 751: @23457 10349 GIM_Try, /*On fail goto*//*Label 752*/ 23497, // Rule ID 245 // 10350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 10351 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10352 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, 10353 // (st GPR64z:{ *:[i64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURXi GPR64z:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) 10354 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURXi, 10355 GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::XZR, // Rt 10356 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10357 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10358 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10359 GIR_EraseFromParent, /*InsnID*/0, 10360 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10361 // GIR_Coverage, 245, 10362 GIR_Done, 10363 // Label 752: @23497 10364 GIM_Try, /*On fail goto*//*Label 753*/ 23536, // Rule ID 250 // 10365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 10366 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10367 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, 10368 // (st FPR64Op:{ *:[f64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) 10369 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, 10370 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10371 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10372 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10373 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10374 GIR_EraseFromParent, /*InsnID*/0, 10375 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10376 // GIR_Coverage, 250, 10377 GIR_Done, 10378 // Label 753: @23536 10379 GIM_Try, /*On fail goto*//*Label 754*/ 23575, // Rule ID 2151 // 10380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 10381 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10382 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, 10383 // (st FPR64:{ *:[v1f64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 10384 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, 10385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10386 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10387 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10388 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10389 GIR_EraseFromParent, /*InsnID*/0, 10390 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10391 // GIR_Coverage, 2151, 10392 GIR_Done, 10393 // Label 754: @23575 10394 GIM_Try, /*On fail goto*//*Label 755*/ 23614, // Rule ID 2152 // 10395 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 10396 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10397 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, 10398 // (st FPR64:{ *:[v1i64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 10399 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, 10400 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10401 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10402 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10403 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10404 GIR_EraseFromParent, /*InsnID*/0, 10405 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10406 // GIR_Coverage, 2152, 10407 GIR_Done, 10408 // Label 755: @23614 10409 GIM_Try, /*On fail goto*//*Label 756*/ 23631, // Rule ID 3020 // 10410 // MIs[0] Rn 10411 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 10412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 10413 // (st v1i64:{ *:[v1i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev1d v1i64:{ *:[v1i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) 10414 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev1d, 10415 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10416 // GIR_Coverage, 3020, 10417 GIR_Done, 10418 // Label 756: @23631 10419 GIM_Reject, 10420 // Label 747: @23632 10421 GIM_Reject, 10422 // Label 730: @23633 10423 GIM_Try, /*On fail goto*//*Label 757*/ 23740, 10424 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 10425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 10426 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10427 GIM_Try, /*On fail goto*//*Label 758*/ 23677, // Rule ID 2134 // 10428 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, 10429 // (st FPR128:{ *:[f128] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) 10430 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, 10431 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10432 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10433 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10434 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10435 GIR_EraseFromParent, /*InsnID*/0, 10436 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10437 // GIR_Coverage, 2134, 10438 GIR_Done, 10439 // Label 758: @23677 10440 GIM_Try, /*On fail goto*//*Label 759*/ 23708, // Rule ID 2158 // 10441 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, 10442 // (st FPR128:{ *:[f128] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 10443 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, 10444 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10445 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10446 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10447 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10448 GIR_EraseFromParent, /*InsnID*/0, 10449 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10450 // GIR_Coverage, 2158, 10451 GIR_Done, 10452 // Label 759: @23708 10453 GIM_Try, /*On fail goto*//*Label 760*/ 23739, // Rule ID 251 // 10454 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, 10455 // (st FPR128Op:{ *:[f128] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128Op:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) 10456 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, 10457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10458 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10459 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10460 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10461 GIR_EraseFromParent, /*InsnID*/0, 10462 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10463 // GIR_Coverage, 251, 10464 GIR_Done, 10465 // Label 760: @23739 10466 GIM_Reject, 10467 // Label 757: @23740 10468 GIM_Reject, 10469 // Label 731: @23741 10470 GIM_Try, /*On fail goto*//*Label 761*/ 23928, 10471 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 10472 GIM_Try, /*On fail goto*//*Label 762*/ 23787, // Rule ID 2129 // 10473 GIM_CheckFeatures, GIFBS_IsLE, 10474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 10475 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10476 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, 10477 // (st FPR64:{ *:[v2f32] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) 10478 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, 10479 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10480 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10481 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10482 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10483 GIR_EraseFromParent, /*InsnID*/0, 10484 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10485 // GIR_Coverage, 2129, 10486 GIR_Done, 10487 // Label 762: @23787 10488 GIM_Try, /*On fail goto*//*Label 763*/ 23828, // Rule ID 2132 // 10489 GIM_CheckFeatures, GIFBS_IsLE, 10490 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 10491 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10492 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, 10493 // (st FPR64:{ *:[v2i32] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) 10494 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, 10495 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10496 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10497 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10498 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10499 GIR_EraseFromParent, /*InsnID*/0, 10500 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10501 // GIR_Coverage, 2132, 10502 GIR_Done, 10503 // Label 763: @23828 10504 GIM_Try, /*On fail goto*//*Label 764*/ 23869, // Rule ID 2153 // 10505 GIM_CheckFeatures, GIFBS_IsLE, 10506 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 10507 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10508 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, 10509 // (st FPR64:{ *:[v2f32] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 10510 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, 10511 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10512 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10513 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10514 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10515 GIR_EraseFromParent, /*InsnID*/0, 10516 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10517 // GIR_Coverage, 2153, 10518 GIR_Done, 10519 // Label 764: @23869 10520 GIM_Try, /*On fail goto*//*Label 765*/ 23910, // Rule ID 2156 // 10521 GIM_CheckFeatures, GIFBS_IsLE, 10522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 10523 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10524 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, 10525 // (st FPR64:{ *:[v2i32] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 10526 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, 10527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10528 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10529 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10530 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10531 GIR_EraseFromParent, /*InsnID*/0, 10532 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10533 // GIR_Coverage, 2156, 10534 GIR_Done, 10535 // Label 765: @23910 10536 GIM_Try, /*On fail goto*//*Label 766*/ 23927, // Rule ID 3019 // 10537 // MIs[0] Rn 10538 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 10539 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 10540 // (st v2i32:{ *:[v2i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev2s v2i32:{ *:[v2i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) 10541 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev2s, 10542 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10543 // GIR_Coverage, 3019, 10544 GIR_Done, 10545 // Label 766: @23927 10546 GIM_Reject, 10547 // Label 761: @23928 10548 GIM_Reject, 10549 // Label 732: @23929 10550 GIM_Try, /*On fail goto*//*Label 767*/ 24157, 10551 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 10552 GIM_Try, /*On fail goto*//*Label 768*/ 23975, // Rule ID 2136 // 10553 GIM_CheckFeatures, GIFBS_IsLE, 10554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 10555 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10556 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, 10557 // (st FPR128:{ *:[v2f64] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) 10558 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, 10559 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10560 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10561 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10562 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10563 GIR_EraseFromParent, /*InsnID*/0, 10564 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10565 // GIR_Coverage, 2136, 10566 GIR_Done, 10567 // Label 768: @23975 10568 GIM_Try, /*On fail goto*//*Label 769*/ 24016, // Rule ID 2140 // 10569 GIM_CheckFeatures, GIFBS_IsLE, 10570 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 10571 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10572 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, 10573 // (st FPR128:{ *:[v2i64] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) 10574 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, 10575 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10576 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10577 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10578 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10579 GIR_EraseFromParent, /*InsnID*/0, 10580 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10581 // GIR_Coverage, 2140, 10582 GIR_Done, 10583 // Label 769: @24016 10584 GIM_Try, /*On fail goto*//*Label 770*/ 24057, // Rule ID 2160 // 10585 GIM_CheckFeatures, GIFBS_IsLE, 10586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 10587 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10588 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, 10589 // (st FPR128:{ *:[v2f64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 10590 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, 10591 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10592 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10593 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10594 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10595 GIR_EraseFromParent, /*InsnID*/0, 10596 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10597 // GIR_Coverage, 2160, 10598 GIR_Done, 10599 // Label 770: @24057 10600 GIM_Try, /*On fail goto*//*Label 771*/ 24098, // Rule ID 2164 // 10601 GIM_CheckFeatures, GIFBS_IsLE, 10602 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 10603 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10604 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, 10605 // (st FPR128:{ *:[v2i64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 10606 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, 10607 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10608 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10609 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10610 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10611 GIR_EraseFromParent, /*InsnID*/0, 10612 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10613 // GIR_Coverage, 2164, 10614 GIR_Done, 10615 // Label 771: @24098 10616 GIM_Try, /*On fail goto*//*Label 772*/ 24139, // Rule ID 2165 // 10617 GIM_CheckFeatures, GIFBS_IsLE, 10618 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 10619 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10620 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, 10621 // (st FPR128:{ *:[v2f64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 10622 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, 10623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10624 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10625 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10626 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10627 GIR_EraseFromParent, /*InsnID*/0, 10628 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10629 // GIR_Coverage, 2165, 10630 GIR_Done, 10631 // Label 772: @24139 10632 GIM_Try, /*On fail goto*//*Label 773*/ 24156, // Rule ID 3016 // 10633 // MIs[0] Rn 10634 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 10635 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 10636 // (st v2i64:{ *:[v2i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev2d v2i64:{ *:[v2i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) 10637 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev2d, 10638 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10639 // GIR_Coverage, 3016, 10640 GIR_Done, 10641 // Label 773: @24156 10642 GIM_Reject, 10643 // Label 767: @24157 10644 GIM_Reject, 10645 // Label 733: @24158 10646 GIM_Try, /*On fail goto*//*Label 774*/ 24345, 10647 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 10648 GIM_Try, /*On fail goto*//*Label 775*/ 24204, // Rule ID 2131 // 10649 GIM_CheckFeatures, GIFBS_IsLE, 10650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 10651 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10652 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, 10653 // (st FPR64:{ *:[v4i16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) 10654 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, 10655 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10656 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10657 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10658 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10659 GIR_EraseFromParent, /*InsnID*/0, 10660 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10661 // GIR_Coverage, 2131, 10662 GIR_Done, 10663 // Label 775: @24204 10664 GIM_Try, /*On fail goto*//*Label 776*/ 24245, // Rule ID 2133 // 10665 GIM_CheckFeatures, GIFBS_IsLE, 10666 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 10667 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10668 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, 10669 // (st FPR64:{ *:[v4f16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) 10670 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, 10671 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10672 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10673 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10674 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10675 GIR_EraseFromParent, /*InsnID*/0, 10676 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10677 // GIR_Coverage, 2133, 10678 GIR_Done, 10679 // Label 776: @24245 10680 GIM_Try, /*On fail goto*//*Label 777*/ 24286, // Rule ID 2155 // 10681 GIM_CheckFeatures, GIFBS_IsLE, 10682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 10683 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10684 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, 10685 // (st FPR64:{ *:[v4i16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 10686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, 10687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10688 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10689 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10690 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10691 GIR_EraseFromParent, /*InsnID*/0, 10692 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10693 // GIR_Coverage, 2155, 10694 GIR_Done, 10695 // Label 777: @24286 10696 GIM_Try, /*On fail goto*//*Label 778*/ 24327, // Rule ID 2157 // 10697 GIM_CheckFeatures, GIFBS_IsLE, 10698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 10699 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10700 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, 10701 // (st FPR64:{ *:[v4f16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 10702 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, 10703 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10704 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10705 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10706 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10707 GIR_EraseFromParent, /*InsnID*/0, 10708 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10709 // GIR_Coverage, 2157, 10710 GIR_Done, 10711 // Label 778: @24327 10712 GIM_Try, /*On fail goto*//*Label 779*/ 24344, // Rule ID 3018 // 10713 // MIs[0] Rn 10714 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 10715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 10716 // (st v4i16:{ *:[v4i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev4h v4i16:{ *:[v4i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) 10717 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev4h, 10718 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10719 // GIR_Coverage, 3018, 10720 GIR_Done, 10721 // Label 779: @24344 10722 GIM_Reject, 10723 // Label 774: @24345 10724 GIM_Reject, 10725 // Label 734: @24346 10726 GIM_Try, /*On fail goto*//*Label 780*/ 24533, 10727 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 10728 GIM_Try, /*On fail goto*//*Label 781*/ 24392, // Rule ID 2135 // 10729 GIM_CheckFeatures, GIFBS_IsLE, 10730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 10731 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10732 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, 10733 // (st FPR128:{ *:[v4f32] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) 10734 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, 10735 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10736 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10737 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10738 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10739 GIR_EraseFromParent, /*InsnID*/0, 10740 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10741 // GIR_Coverage, 2135, 10742 GIR_Done, 10743 // Label 781: @24392 10744 GIM_Try, /*On fail goto*//*Label 782*/ 24433, // Rule ID 2139 // 10745 GIM_CheckFeatures, GIFBS_IsLE, 10746 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 10747 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10748 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, 10749 // (st FPR128:{ *:[v4i32] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) 10750 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, 10751 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10752 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10753 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10754 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10755 GIR_EraseFromParent, /*InsnID*/0, 10756 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10757 // GIR_Coverage, 2139, 10758 GIR_Done, 10759 // Label 782: @24433 10760 GIM_Try, /*On fail goto*//*Label 783*/ 24474, // Rule ID 2159 // 10761 GIM_CheckFeatures, GIFBS_IsLE, 10762 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 10763 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10764 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, 10765 // (st FPR128:{ *:[v4f32] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 10766 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, 10767 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10768 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10769 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10770 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10771 GIR_EraseFromParent, /*InsnID*/0, 10772 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10773 // GIR_Coverage, 2159, 10774 GIR_Done, 10775 // Label 783: @24474 10776 GIM_Try, /*On fail goto*//*Label 784*/ 24515, // Rule ID 2163 // 10777 GIM_CheckFeatures, GIFBS_IsLE, 10778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 10779 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10780 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, 10781 // (st FPR128:{ *:[v4i32] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 10782 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, 10783 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10784 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10785 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10786 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10787 GIR_EraseFromParent, /*InsnID*/0, 10788 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10789 // GIR_Coverage, 2163, 10790 GIR_Done, 10791 // Label 784: @24515 10792 GIM_Try, /*On fail goto*//*Label 785*/ 24532, // Rule ID 3015 // 10793 // MIs[0] Rn 10794 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 10795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 10796 // (st v4i32:{ *:[v4i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev4s v4i32:{ *:[v4i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) 10797 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev4s, 10798 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10799 // GIR_Coverage, 3015, 10800 GIR_Done, 10801 // Label 785: @24532 10802 GIM_Reject, 10803 // Label 780: @24533 10804 GIM_Reject, 10805 // Label 735: @24534 10806 GIM_Try, /*On fail goto*//*Label 786*/ 24639, 10807 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 10808 GIM_Try, /*On fail goto*//*Label 787*/ 24580, // Rule ID 2130 // 10809 GIM_CheckFeatures, GIFBS_IsLE, 10810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 10811 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10812 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, 10813 // (st FPR64:{ *:[v8i8] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) 10814 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, 10815 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10816 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10817 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10818 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10819 GIR_EraseFromParent, /*InsnID*/0, 10820 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10821 // GIR_Coverage, 2130, 10822 GIR_Done, 10823 // Label 787: @24580 10824 GIM_Try, /*On fail goto*//*Label 788*/ 24621, // Rule ID 2154 // 10825 GIM_CheckFeatures, GIFBS_IsLE, 10826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 10827 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10828 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, 10829 // (st FPR64:{ *:[v8i8] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 10830 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, 10831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10832 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10833 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10834 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10835 GIR_EraseFromParent, /*InsnID*/0, 10836 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10837 // GIR_Coverage, 2154, 10838 GIR_Done, 10839 // Label 788: @24621 10840 GIM_Try, /*On fail goto*//*Label 789*/ 24638, // Rule ID 3017 // 10841 // MIs[0] Rn 10842 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 10843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 10844 // (st v8i8:{ *:[v8i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev8b v8i8:{ *:[v8i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) 10845 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev8b, 10846 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10847 // GIR_Coverage, 3017, 10848 GIR_Done, 10849 // Label 789: @24638 10850 GIM_Reject, 10851 // Label 786: @24639 10852 GIM_Reject, 10853 // Label 736: @24640 10854 GIM_Try, /*On fail goto*//*Label 790*/ 24827, 10855 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 10856 GIM_Try, /*On fail goto*//*Label 791*/ 24686, // Rule ID 2138 // 10857 GIM_CheckFeatures, GIFBS_IsLE, 10858 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 10859 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10860 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, 10861 // (st FPR128:{ *:[v8i16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) 10862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, 10863 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10864 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10865 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10866 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10867 GIR_EraseFromParent, /*InsnID*/0, 10868 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10869 // GIR_Coverage, 2138, 10870 GIR_Done, 10871 // Label 791: @24686 10872 GIM_Try, /*On fail goto*//*Label 792*/ 24727, // Rule ID 2141 // 10873 GIM_CheckFeatures, GIFBS_IsLE, 10874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 10875 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10876 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, 10877 // (st FPR128:{ *:[v8f16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) 10878 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, 10879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10880 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10881 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10882 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10883 GIR_EraseFromParent, /*InsnID*/0, 10884 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10885 // GIR_Coverage, 2141, 10886 GIR_Done, 10887 // Label 792: @24727 10888 GIM_Try, /*On fail goto*//*Label 793*/ 24768, // Rule ID 2162 // 10889 GIM_CheckFeatures, GIFBS_IsLE, 10890 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 10891 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10892 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, 10893 // (st FPR128:{ *:[v8i16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 10894 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, 10895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10896 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10897 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10898 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10899 GIR_EraseFromParent, /*InsnID*/0, 10900 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10901 // GIR_Coverage, 2162, 10902 GIR_Done, 10903 // Label 793: @24768 10904 GIM_Try, /*On fail goto*//*Label 794*/ 24809, // Rule ID 2166 // 10905 GIM_CheckFeatures, GIFBS_IsLE, 10906 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 10907 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10908 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, 10909 // (st FPR128:{ *:[v8f16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 10910 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, 10911 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10912 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10913 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10914 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10915 GIR_EraseFromParent, /*InsnID*/0, 10916 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10917 // GIR_Coverage, 2166, 10918 GIR_Done, 10919 // Label 794: @24809 10920 GIM_Try, /*On fail goto*//*Label 795*/ 24826, // Rule ID 3014 // 10921 // MIs[0] Rn 10922 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 10923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 10924 // (st v8i16:{ *:[v8i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev8h v8i16:{ *:[v8i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) 10925 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev8h, 10926 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10927 // GIR_Coverage, 3014, 10928 GIR_Done, 10929 // Label 795: @24826 10930 GIM_Reject, 10931 // Label 790: @24827 10932 GIM_Reject, 10933 // Label 737: @24828 10934 GIM_Try, /*On fail goto*//*Label 796*/ 24933, 10935 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 10936 GIM_Try, /*On fail goto*//*Label 797*/ 24874, // Rule ID 2137 // 10937 GIM_CheckFeatures, GIFBS_IsLE, 10938 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 10939 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10940 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, 10941 // (st FPR128:{ *:[v16i8] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) 10942 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, 10943 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10944 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10945 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10946 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10947 GIR_EraseFromParent, /*InsnID*/0, 10948 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10949 // GIR_Coverage, 2137, 10950 GIR_Done, 10951 // Label 797: @24874 10952 GIM_Try, /*On fail goto*//*Label 798*/ 24915, // Rule ID 2161 // 10953 GIM_CheckFeatures, GIFBS_IsLE, 10954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 10955 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, 10956 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, 10957 // (st FPR128:{ *:[v16i8] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) 10958 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, 10959 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 10960 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn 10961 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset 10962 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10963 GIR_EraseFromParent, /*InsnID*/0, 10964 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10965 // GIR_Coverage, 2161, 10966 GIR_Done, 10967 // Label 798: @24915 10968 GIM_Try, /*On fail goto*//*Label 799*/ 24932, // Rule ID 3013 // 10969 // MIs[0] Rn 10970 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 10971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 10972 // (st v16i8:{ *:[v16i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev16b v16i8:{ *:[v16i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) 10973 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev16b, 10974 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10975 // GIR_Coverage, 3013, 10976 GIR_Done, 10977 // Label 799: @24932 10978 GIM_Reject, 10979 // Label 796: @24933 10980 GIM_Reject, 10981 // Label 738: @24934 10982 GIM_Reject, 10983 // Label 13: @24935 10984 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 802*/ 26131, 10985 /*GILLT_s32*//*Label 800*/ 24943, 10986 /*GILLT_s64*//*Label 801*/ 25840, 10987 // Label 800: @24943 10988 GIM_Try, /*On fail goto*//*Label 803*/ 25839, 10989 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 10990 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 10991 GIM_Try, /*On fail goto*//*Label 804*/ 25012, // Rule ID 3720 // 10992 GIM_CheckFeatures, GIFBS_HasLSE, 10993 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 10994 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 10995 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 10996 // MIs[0] Rn 10997 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 10998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 10999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 11001 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_monotonic>> => (CASW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11002 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASW, 11003 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11004 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11005 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11006 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11007 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11008 GIR_EraseFromParent, /*InsnID*/0, 11009 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11010 // GIR_Coverage, 3720, 11011 GIR_Done, 11012 // Label 804: @25012 11013 GIM_Try, /*On fail goto*//*Label 805*/ 25071, // Rule ID 3721 // 11014 GIM_CheckFeatures, GIFBS_HasLSE, 11015 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 11016 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 11017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11018 // MIs[0] Rn 11019 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11021 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 11023 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_acquire>> => (CASAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11024 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAW, 11025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11027 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11028 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11029 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11030 GIR_EraseFromParent, /*InsnID*/0, 11031 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11032 // GIR_Coverage, 3721, 11033 GIR_Done, 11034 // Label 805: @25071 11035 GIM_Try, /*On fail goto*//*Label 806*/ 25130, // Rule ID 3722 // 11036 GIM_CheckFeatures, GIFBS_HasLSE, 11037 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 11038 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 11039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11040 // MIs[0] Rn 11041 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 11045 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_release>> => (CASLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11046 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLW, 11047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11051 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11052 GIR_EraseFromParent, /*InsnID*/0, 11053 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11054 // GIR_Coverage, 3722, 11055 GIR_Done, 11056 // Label 806: @25130 11057 GIM_Try, /*On fail goto*//*Label 807*/ 25189, // Rule ID 3723 // 11058 GIM_CheckFeatures, GIFBS_HasLSE, 11059 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 11060 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 11061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11062 // MIs[0] Rn 11063 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11065 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11066 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 11067 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_acq_rel>> => (CASALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11068 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALW, 11069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11070 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11071 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11072 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11073 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11074 GIR_EraseFromParent, /*InsnID*/0, 11075 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11076 // GIR_Coverage, 3723, 11077 GIR_Done, 11078 // Label 807: @25189 11079 GIM_Try, /*On fail goto*//*Label 808*/ 25248, // Rule ID 3724 // 11080 GIM_CheckFeatures, GIFBS_HasLSE, 11081 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 11082 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 11083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11084 // MIs[0] Rn 11085 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 11089 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_seq_cst>> => (CASALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11090 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALW, 11091 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11095 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11096 GIR_EraseFromParent, /*InsnID*/0, 11097 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11098 // GIR_Coverage, 3724, 11099 GIR_Done, 11100 // Label 808: @25248 11101 GIM_Try, /*On fail goto*//*Label 809*/ 25307, // Rule ID 3725 // 11102 GIM_CheckFeatures, GIFBS_HasLSE, 11103 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 11104 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 11105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11106 // MIs[0] Rn 11107 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 11111 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_16>><<P:Predicate_atomic_cmp_swap_16_monotonic>> => (CASH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11112 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASH, 11113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11114 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11117 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11118 GIR_EraseFromParent, /*InsnID*/0, 11119 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11120 // GIR_Coverage, 3725, 11121 GIR_Done, 11122 // Label 809: @25307 11123 GIM_Try, /*On fail goto*//*Label 810*/ 25366, // Rule ID 3726 // 11124 GIM_CheckFeatures, GIFBS_HasLSE, 11125 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 11126 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 11127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11128 // MIs[0] Rn 11129 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 11133 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_16>><<P:Predicate_atomic_cmp_swap_16_acquire>> => (CASAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11134 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAH, 11135 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11138 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11139 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11140 GIR_EraseFromParent, /*InsnID*/0, 11141 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11142 // GIR_Coverage, 3726, 11143 GIR_Done, 11144 // Label 810: @25366 11145 GIM_Try, /*On fail goto*//*Label 811*/ 25425, // Rule ID 3727 // 11146 GIM_CheckFeatures, GIFBS_HasLSE, 11147 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 11148 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 11149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11150 // MIs[0] Rn 11151 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11152 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 11155 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_16>><<P:Predicate_atomic_cmp_swap_16_release>> => (CASLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11156 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLH, 11157 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11158 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11159 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11160 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11161 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11162 GIR_EraseFromParent, /*InsnID*/0, 11163 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11164 // GIR_Coverage, 3727, 11165 GIR_Done, 11166 // Label 811: @25425 11167 GIM_Try, /*On fail goto*//*Label 812*/ 25484, // Rule ID 3728 // 11168 GIM_CheckFeatures, GIFBS_HasLSE, 11169 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 11170 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 11171 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11172 // MIs[0] Rn 11173 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11175 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 11177 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_16>><<P:Predicate_atomic_cmp_swap_16_acq_rel>> => (CASALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11178 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALH, 11179 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11180 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11181 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11182 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11183 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11184 GIR_EraseFromParent, /*InsnID*/0, 11185 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11186 // GIR_Coverage, 3728, 11187 GIR_Done, 11188 // Label 812: @25484 11189 GIM_Try, /*On fail goto*//*Label 813*/ 25543, // Rule ID 3729 // 11190 GIM_CheckFeatures, GIFBS_HasLSE, 11191 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 11192 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 11193 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11194 // MIs[0] Rn 11195 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 11199 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_16>><<P:Predicate_atomic_cmp_swap_16_seq_cst>> => (CASALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11200 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALH, 11201 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11202 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11203 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11205 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11206 GIR_EraseFromParent, /*InsnID*/0, 11207 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11208 // GIR_Coverage, 3729, 11209 GIR_Done, 11210 // Label 813: @25543 11211 GIM_Try, /*On fail goto*//*Label 814*/ 25602, // Rule ID 3730 // 11212 GIM_CheckFeatures, GIFBS_HasLSE, 11213 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 11214 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 11215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11216 // MIs[0] Rn 11217 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 11221 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_8>><<P:Predicate_atomic_cmp_swap_8_monotonic>> => (CASB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11222 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASB, 11223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11226 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11227 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11228 GIR_EraseFromParent, /*InsnID*/0, 11229 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11230 // GIR_Coverage, 3730, 11231 GIR_Done, 11232 // Label 814: @25602 11233 GIM_Try, /*On fail goto*//*Label 815*/ 25661, // Rule ID 3731 // 11234 GIM_CheckFeatures, GIFBS_HasLSE, 11235 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 11236 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 11237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11238 // MIs[0] Rn 11239 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 11243 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_8>><<P:Predicate_atomic_cmp_swap_8_acquire>> => (CASAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11244 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAB, 11245 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11246 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11247 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11248 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11249 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11250 GIR_EraseFromParent, /*InsnID*/0, 11251 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11252 // GIR_Coverage, 3731, 11253 GIR_Done, 11254 // Label 815: @25661 11255 GIM_Try, /*On fail goto*//*Label 816*/ 25720, // Rule ID 3732 // 11256 GIM_CheckFeatures, GIFBS_HasLSE, 11257 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 11258 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 11259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11260 // MIs[0] Rn 11261 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 11265 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_8>><<P:Predicate_atomic_cmp_swap_8_release>> => (CASLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11266 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLB, 11267 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11268 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11271 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11272 GIR_EraseFromParent, /*InsnID*/0, 11273 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11274 // GIR_Coverage, 3732, 11275 GIR_Done, 11276 // Label 816: @25720 11277 GIM_Try, /*On fail goto*//*Label 817*/ 25779, // Rule ID 3733 // 11278 GIM_CheckFeatures, GIFBS_HasLSE, 11279 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 11280 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 11281 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11282 // MIs[0] Rn 11283 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 11287 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_8>><<P:Predicate_atomic_cmp_swap_8_acq_rel>> => (CASALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALB, 11289 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11290 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11293 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11294 GIR_EraseFromParent, /*InsnID*/0, 11295 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11296 // GIR_Coverage, 3733, 11297 GIR_Done, 11298 // Label 817: @25779 11299 GIM_Try, /*On fail goto*//*Label 818*/ 25838, // Rule ID 3734 // 11300 GIM_CheckFeatures, GIFBS_HasLSE, 11301 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 11302 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 11303 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11304 // MIs[0] Rn 11305 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 11309 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_8>><<P:Predicate_atomic_cmp_swap_8_seq_cst>> => (CASALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11310 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALB, 11311 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11312 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11313 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11315 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11316 GIR_EraseFromParent, /*InsnID*/0, 11317 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11318 // GIR_Coverage, 3734, 11319 GIR_Done, 11320 // Label 818: @25838 11321 GIM_Reject, 11322 // Label 803: @25839 11323 GIM_Reject, 11324 // Label 801: @25840 11325 GIM_Try, /*On fail goto*//*Label 819*/ 26130, 11326 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 11327 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 11328 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 11329 GIM_Try, /*On fail goto*//*Label 820*/ 25909, // Rule ID 1821 // 11330 GIM_CheckFeatures, GIFBS_HasLSE, 11331 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 11332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 11333 // MIs[0] Rn 11334 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11335 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 11337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, 11338 // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_monotonic>> => (CASX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11339 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASX, 11340 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11341 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11342 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11343 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11344 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11345 GIR_EraseFromParent, /*InsnID*/0, 11346 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11347 // GIR_Coverage, 1821, 11348 GIR_Done, 11349 // Label 820: @25909 11350 GIM_Try, /*On fail goto*//*Label 821*/ 25964, // Rule ID 1822 // 11351 GIM_CheckFeatures, GIFBS_HasLSE, 11352 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 11353 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 11354 // MIs[0] Rn 11355 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 11358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, 11359 // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_acquire>> => (CASAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11360 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAX, 11361 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11362 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11365 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11366 GIR_EraseFromParent, /*InsnID*/0, 11367 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11368 // GIR_Coverage, 1822, 11369 GIR_Done, 11370 // Label 821: @25964 11371 GIM_Try, /*On fail goto*//*Label 822*/ 26019, // Rule ID 1823 // 11372 GIM_CheckFeatures, GIFBS_HasLSE, 11373 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 11374 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 11375 // MIs[0] Rn 11376 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11377 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11378 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 11379 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, 11380 // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_release>> => (CASLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11381 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLX, 11382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11386 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11387 GIR_EraseFromParent, /*InsnID*/0, 11388 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11389 // GIR_Coverage, 1823, 11390 GIR_Done, 11391 // Label 822: @26019 11392 GIM_Try, /*On fail goto*//*Label 823*/ 26074, // Rule ID 1824 // 11393 GIM_CheckFeatures, GIFBS_HasLSE, 11394 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 11395 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 11396 // MIs[0] Rn 11397 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 11400 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, 11401 // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_acq_rel>> => (CASALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11402 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALX, 11403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11405 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11406 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11407 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11408 GIR_EraseFromParent, /*InsnID*/0, 11409 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11410 // GIR_Coverage, 1824, 11411 GIR_Done, 11412 // Label 823: @26074 11413 GIM_Try, /*On fail goto*//*Label 824*/ 26129, // Rule ID 1825 // 11414 GIM_CheckFeatures, GIFBS_HasLSE, 11415 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 11416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 11417 // MIs[0] Rn 11418 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11420 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 11421 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, 11422 // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_seq_cst>> => (CASALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) 11423 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALX, 11424 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out 11425 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold 11426 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew 11427 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11428 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11429 GIR_EraseFromParent, /*InsnID*/0, 11430 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11431 // GIR_Coverage, 1825, 11432 GIR_Done, 11433 // Label 824: @26129 11434 GIM_Reject, 11435 // Label 819: @26130 11436 GIM_Reject, 11437 // Label 802: @26131 11438 GIM_Reject, 11439 // Label 14: @26132 11440 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 827*/ 27160, 11441 /*GILLT_s32*//*Label 825*/ 26140, 11442 /*GILLT_s64*//*Label 826*/ 26913, 11443 // Label 825: @26140 11444 GIM_Try, /*On fail goto*//*Label 828*/ 26912, 11445 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11446 GIM_Try, /*On fail goto*//*Label 829*/ 26197, // Rule ID 3705 // 11447 GIM_CheckFeatures, GIFBS_HasLSE, 11448 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 11449 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 11450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11451 // MIs[0] Rn 11452 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11453 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11454 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11455 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_monotonic>> => (SWPW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11456 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPW, 11457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11458 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11459 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11460 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11461 GIR_EraseFromParent, /*InsnID*/0, 11462 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11463 // GIR_Coverage, 3705, 11464 GIR_Done, 11465 // Label 829: @26197 11466 GIM_Try, /*On fail goto*//*Label 830*/ 26248, // Rule ID 3706 // 11467 GIM_CheckFeatures, GIFBS_HasLSE, 11468 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 11469 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 11470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11471 // MIs[0] Rn 11472 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11475 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acquire>> => (SWPAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11476 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAW, 11477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11478 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11479 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11480 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11481 GIR_EraseFromParent, /*InsnID*/0, 11482 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11483 // GIR_Coverage, 3706, 11484 GIR_Done, 11485 // Label 830: @26248 11486 GIM_Try, /*On fail goto*//*Label 831*/ 26299, // Rule ID 3707 // 11487 GIM_CheckFeatures, GIFBS_HasLSE, 11488 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 11489 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 11490 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11491 // MIs[0] Rn 11492 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11495 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_release>> => (SWPLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11496 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLW, 11497 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11498 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11500 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11501 GIR_EraseFromParent, /*InsnID*/0, 11502 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11503 // GIR_Coverage, 3707, 11504 GIR_Done, 11505 // Label 831: @26299 11506 GIM_Try, /*On fail goto*//*Label 832*/ 26350, // Rule ID 3708 // 11507 GIM_CheckFeatures, GIFBS_HasLSE, 11508 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 11509 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 11510 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11511 // MIs[0] Rn 11512 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11513 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11514 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11515 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acq_rel>> => (SWPALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11516 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALW, 11517 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11518 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11519 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11520 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11521 GIR_EraseFromParent, /*InsnID*/0, 11522 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11523 // GIR_Coverage, 3708, 11524 GIR_Done, 11525 // Label 832: @26350 11526 GIM_Try, /*On fail goto*//*Label 833*/ 26401, // Rule ID 3709 // 11527 GIM_CheckFeatures, GIFBS_HasLSE, 11528 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 11529 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 11530 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11531 // MIs[0] Rn 11532 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11533 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11534 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11535 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_seq_cst>> => (SWPALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11536 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALW, 11537 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11538 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11539 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11540 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11541 GIR_EraseFromParent, /*InsnID*/0, 11542 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11543 // GIR_Coverage, 3709, 11544 GIR_Done, 11545 // Label 833: @26401 11546 GIM_Try, /*On fail goto*//*Label 834*/ 26452, // Rule ID 3710 // 11547 GIM_CheckFeatures, GIFBS_HasLSE, 11548 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 11549 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 11550 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11551 // MIs[0] Rn 11552 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11555 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_16>><<P:Predicate_atomic_swap_16_monotonic>> => (SWPH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11556 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPH, 11557 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11558 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11559 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11560 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11561 GIR_EraseFromParent, /*InsnID*/0, 11562 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11563 // GIR_Coverage, 3710, 11564 GIR_Done, 11565 // Label 834: @26452 11566 GIM_Try, /*On fail goto*//*Label 835*/ 26503, // Rule ID 3711 // 11567 GIM_CheckFeatures, GIFBS_HasLSE, 11568 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 11569 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 11570 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11571 // MIs[0] Rn 11572 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11575 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_16>><<P:Predicate_atomic_swap_16_acquire>> => (SWPAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11576 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAH, 11577 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11578 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11579 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11580 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11581 GIR_EraseFromParent, /*InsnID*/0, 11582 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11583 // GIR_Coverage, 3711, 11584 GIR_Done, 11585 // Label 835: @26503 11586 GIM_Try, /*On fail goto*//*Label 836*/ 26554, // Rule ID 3712 // 11587 GIM_CheckFeatures, GIFBS_HasLSE, 11588 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 11589 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 11590 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11591 // MIs[0] Rn 11592 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11595 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_16>><<P:Predicate_atomic_swap_16_release>> => (SWPLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11596 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLH, 11597 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11598 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11599 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11600 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11601 GIR_EraseFromParent, /*InsnID*/0, 11602 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11603 // GIR_Coverage, 3712, 11604 GIR_Done, 11605 // Label 836: @26554 11606 GIM_Try, /*On fail goto*//*Label 837*/ 26605, // Rule ID 3713 // 11607 GIM_CheckFeatures, GIFBS_HasLSE, 11608 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 11609 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 11610 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11611 // MIs[0] Rn 11612 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11615 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_16>><<P:Predicate_atomic_swap_16_acq_rel>> => (SWPALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALH, 11617 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11620 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11621 GIR_EraseFromParent, /*InsnID*/0, 11622 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11623 // GIR_Coverage, 3713, 11624 GIR_Done, 11625 // Label 837: @26605 11626 GIM_Try, /*On fail goto*//*Label 838*/ 26656, // Rule ID 3714 // 11627 GIM_CheckFeatures, GIFBS_HasLSE, 11628 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 11629 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 11630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11631 // MIs[0] Rn 11632 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11633 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11634 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11635 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_16>><<P:Predicate_atomic_swap_16_seq_cst>> => (SWPALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11636 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALH, 11637 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11638 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11639 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11640 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11641 GIR_EraseFromParent, /*InsnID*/0, 11642 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11643 // GIR_Coverage, 3714, 11644 GIR_Done, 11645 // Label 838: @26656 11646 GIM_Try, /*On fail goto*//*Label 839*/ 26707, // Rule ID 3715 // 11647 GIM_CheckFeatures, GIFBS_HasLSE, 11648 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 11649 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 11650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11651 // MIs[0] Rn 11652 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11655 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_8>><<P:Predicate_atomic_swap_8_monotonic>> => (SWPB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11656 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPB, 11657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11659 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11660 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11661 GIR_EraseFromParent, /*InsnID*/0, 11662 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11663 // GIR_Coverage, 3715, 11664 GIR_Done, 11665 // Label 839: @26707 11666 GIM_Try, /*On fail goto*//*Label 840*/ 26758, // Rule ID 3716 // 11667 GIM_CheckFeatures, GIFBS_HasLSE, 11668 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 11669 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 11670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11671 // MIs[0] Rn 11672 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11673 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11674 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11675 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_8>><<P:Predicate_atomic_swap_8_acquire>> => (SWPAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11676 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAB, 11677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11679 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11680 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11681 GIR_EraseFromParent, /*InsnID*/0, 11682 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11683 // GIR_Coverage, 3716, 11684 GIR_Done, 11685 // Label 840: @26758 11686 GIM_Try, /*On fail goto*//*Label 841*/ 26809, // Rule ID 3717 // 11687 GIM_CheckFeatures, GIFBS_HasLSE, 11688 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 11689 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 11690 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11691 // MIs[0] Rn 11692 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11693 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11695 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_8>><<P:Predicate_atomic_swap_8_release>> => (SWPLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11696 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLB, 11697 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11698 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11699 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11700 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11701 GIR_EraseFromParent, /*InsnID*/0, 11702 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11703 // GIR_Coverage, 3717, 11704 GIR_Done, 11705 // Label 841: @26809 11706 GIM_Try, /*On fail goto*//*Label 842*/ 26860, // Rule ID 3718 // 11707 GIM_CheckFeatures, GIFBS_HasLSE, 11708 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 11709 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 11710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11711 // MIs[0] Rn 11712 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11715 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_8>><<P:Predicate_atomic_swap_8_acq_rel>> => (SWPALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11716 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALB, 11717 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11718 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11719 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11720 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11721 GIR_EraseFromParent, /*InsnID*/0, 11722 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11723 // GIR_Coverage, 3718, 11724 GIR_Done, 11725 // Label 842: @26860 11726 GIM_Try, /*On fail goto*//*Label 843*/ 26911, // Rule ID 3719 // 11727 GIM_CheckFeatures, GIFBS_HasLSE, 11728 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 11729 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 11730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11731 // MIs[0] Rn 11732 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11735 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_8>><<P:Predicate_atomic_swap_8_seq_cst>> => (SWPALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11736 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALB, 11737 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11738 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11739 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11740 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11741 GIR_EraseFromParent, /*InsnID*/0, 11742 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11743 // GIR_Coverage, 3719, 11744 GIR_Done, 11745 // Label 843: @26911 11746 GIM_Reject, 11747 // Label 828: @26912 11748 GIM_Reject, 11749 // Label 826: @26913 11750 GIM_Try, /*On fail goto*//*Label 844*/ 27159, 11751 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 11752 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 11753 GIM_Try, /*On fail goto*//*Label 845*/ 26970, // Rule ID 3700 // 11754 GIM_CheckFeatures, GIFBS_HasLSE, 11755 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 11756 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 11757 // MIs[0] Rn 11758 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11759 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 11761 // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_monotonic>> => (SWPX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11762 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPX, 11763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11766 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11767 GIR_EraseFromParent, /*InsnID*/0, 11768 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11769 // GIR_Coverage, 3700, 11770 GIR_Done, 11771 // Label 845: @26970 11772 GIM_Try, /*On fail goto*//*Label 846*/ 27017, // Rule ID 3701 // 11773 GIM_CheckFeatures, GIFBS_HasLSE, 11774 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 11775 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 11776 // MIs[0] Rn 11777 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 11780 // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acquire>> => (SWPAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11781 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAX, 11782 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11783 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11785 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11786 GIR_EraseFromParent, /*InsnID*/0, 11787 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11788 // GIR_Coverage, 3701, 11789 GIR_Done, 11790 // Label 846: @27017 11791 GIM_Try, /*On fail goto*//*Label 847*/ 27064, // Rule ID 3702 // 11792 GIM_CheckFeatures, GIFBS_HasLSE, 11793 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 11794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 11795 // MIs[0] Rn 11796 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 11799 // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_release>> => (SWPLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11800 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLX, 11801 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11802 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11803 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11804 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11805 GIR_EraseFromParent, /*InsnID*/0, 11806 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11807 // GIR_Coverage, 3702, 11808 GIR_Done, 11809 // Label 847: @27064 11810 GIM_Try, /*On fail goto*//*Label 848*/ 27111, // Rule ID 3703 // 11811 GIM_CheckFeatures, GIFBS_HasLSE, 11812 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 11813 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 11814 // MIs[0] Rn 11815 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 11818 // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acq_rel>> => (SWPALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11819 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALX, 11820 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11821 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11822 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11823 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11824 GIR_EraseFromParent, /*InsnID*/0, 11825 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11826 // GIR_Coverage, 3703, 11827 GIR_Done, 11828 // Label 848: @27111 11829 GIM_Try, /*On fail goto*//*Label 849*/ 27158, // Rule ID 3704 // 11830 GIM_CheckFeatures, GIFBS_HasLSE, 11831 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 11832 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 11833 // MIs[0] Rn 11834 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11835 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11836 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 11837 // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_seq_cst>> => (SWPALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11838 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALX, 11839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11840 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11841 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11842 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11843 GIR_EraseFromParent, /*InsnID*/0, 11844 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11845 // GIR_Coverage, 3704, 11846 GIR_Done, 11847 // Label 849: @27158 11848 GIM_Reject, 11849 // Label 844: @27159 11850 GIM_Reject, 11851 // Label 827: @27160 11852 GIM_Reject, 11853 // Label 15: @27161 11854 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 852*/ 28189, 11855 /*GILLT_s32*//*Label 850*/ 27169, 11856 /*GILLT_s64*//*Label 851*/ 27942, 11857 // Label 850: @27169 11858 GIM_Try, /*On fail goto*//*Label 853*/ 27941, 11859 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11860 GIM_Try, /*On fail goto*//*Label 854*/ 27226, // Rule ID 3545 // 11861 GIM_CheckFeatures, GIFBS_HasLSE, 11862 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 11863 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 11864 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11865 // MIs[0] Rn 11866 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11867 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11869 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_monotonic>> => (LDADDW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11870 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDW, 11871 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11872 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11873 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11874 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11875 GIR_EraseFromParent, /*InsnID*/0, 11876 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11877 // GIR_Coverage, 3545, 11878 GIR_Done, 11879 // Label 854: @27226 11880 GIM_Try, /*On fail goto*//*Label 855*/ 27277, // Rule ID 3546 // 11881 GIM_CheckFeatures, GIFBS_HasLSE, 11882 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 11883 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 11884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11885 // MIs[0] Rn 11886 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11888 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11889 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acquire>> => (LDADDAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11890 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAW, 11891 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11892 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11893 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11894 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11895 GIR_EraseFromParent, /*InsnID*/0, 11896 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11897 // GIR_Coverage, 3546, 11898 GIR_Done, 11899 // Label 855: @27277 11900 GIM_Try, /*On fail goto*//*Label 856*/ 27328, // Rule ID 3547 // 11901 GIM_CheckFeatures, GIFBS_HasLSE, 11902 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 11903 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 11904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11905 // MIs[0] Rn 11906 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11907 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11908 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11909 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_release>> => (LDADDLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11910 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLW, 11911 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11912 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11913 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11914 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11915 GIR_EraseFromParent, /*InsnID*/0, 11916 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11917 // GIR_Coverage, 3547, 11918 GIR_Done, 11919 // Label 856: @27328 11920 GIM_Try, /*On fail goto*//*Label 857*/ 27379, // Rule ID 3548 // 11921 GIM_CheckFeatures, GIFBS_HasLSE, 11922 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 11923 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 11924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11925 // MIs[0] Rn 11926 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11927 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11928 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11929 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acq_rel>> => (LDADDALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11930 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW, 11931 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11932 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11934 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11935 GIR_EraseFromParent, /*InsnID*/0, 11936 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11937 // GIR_Coverage, 3548, 11938 GIR_Done, 11939 // Label 857: @27379 11940 GIM_Try, /*On fail goto*//*Label 858*/ 27430, // Rule ID 3549 // 11941 GIM_CheckFeatures, GIFBS_HasLSE, 11942 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 11943 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 11944 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11945 // MIs[0] Rn 11946 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11949 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_seq_cst>> => (LDADDALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11950 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW, 11951 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11952 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11954 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11955 GIR_EraseFromParent, /*InsnID*/0, 11956 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11957 // GIR_Coverage, 3549, 11958 GIR_Done, 11959 // Label 858: @27430 11960 GIM_Try, /*On fail goto*//*Label 859*/ 27481, // Rule ID 3550 // 11961 GIM_CheckFeatures, GIFBS_HasLSE, 11962 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 11963 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 11964 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11965 // MIs[0] Rn 11966 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11968 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11969 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_16>><<P:Predicate_atomic_load_add_16_monotonic>> => (LDADDH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11970 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDH, 11971 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11973 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11974 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11975 GIR_EraseFromParent, /*InsnID*/0, 11976 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11977 // GIR_Coverage, 3550, 11978 GIR_Done, 11979 // Label 859: @27481 11980 GIM_Try, /*On fail goto*//*Label 860*/ 27532, // Rule ID 3551 // 11981 GIM_CheckFeatures, GIFBS_HasLSE, 11982 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 11983 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 11984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 11985 // MIs[0] Rn 11986 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 11987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 11988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 11989 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_16>><<P:Predicate_atomic_load_add_16_acquire>> => (LDADDAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 11990 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAH, 11991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 11992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 11993 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 11994 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 11995 GIR_EraseFromParent, /*InsnID*/0, 11996 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11997 // GIR_Coverage, 3551, 11998 GIR_Done, 11999 // Label 860: @27532 12000 GIM_Try, /*On fail goto*//*Label 861*/ 27583, // Rule ID 3552 // 12001 GIM_CheckFeatures, GIFBS_HasLSE, 12002 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 12003 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 12004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12005 // MIs[0] Rn 12006 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12008 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12009 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_16>><<P:Predicate_atomic_load_add_16_release>> => (LDADDLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 12010 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLH, 12011 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12012 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12014 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12015 GIR_EraseFromParent, /*InsnID*/0, 12016 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12017 // GIR_Coverage, 3552, 12018 GIR_Done, 12019 // Label 861: @27583 12020 GIM_Try, /*On fail goto*//*Label 862*/ 27634, // Rule ID 3553 // 12021 GIM_CheckFeatures, GIFBS_HasLSE, 12022 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 12023 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 12024 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12025 // MIs[0] Rn 12026 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12027 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12028 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12029 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_16>><<P:Predicate_atomic_load_add_16_acq_rel>> => (LDADDALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 12030 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH, 12031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12032 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12033 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12034 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12035 GIR_EraseFromParent, /*InsnID*/0, 12036 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12037 // GIR_Coverage, 3553, 12038 GIR_Done, 12039 // Label 862: @27634 12040 GIM_Try, /*On fail goto*//*Label 863*/ 27685, // Rule ID 3554 // 12041 GIM_CheckFeatures, GIFBS_HasLSE, 12042 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 12043 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 12044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12045 // MIs[0] Rn 12046 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12048 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12049 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_16>><<P:Predicate_atomic_load_add_16_seq_cst>> => (LDADDALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 12050 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH, 12051 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12052 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12053 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12054 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12055 GIR_EraseFromParent, /*InsnID*/0, 12056 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12057 // GIR_Coverage, 3554, 12058 GIR_Done, 12059 // Label 863: @27685 12060 GIM_Try, /*On fail goto*//*Label 864*/ 27736, // Rule ID 3555 // 12061 GIM_CheckFeatures, GIFBS_HasLSE, 12062 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 12063 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 12064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12065 // MIs[0] Rn 12066 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12069 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_8>><<P:Predicate_atomic_load_add_8_monotonic>> => (LDADDB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 12070 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDB, 12071 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12072 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12074 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12075 GIR_EraseFromParent, /*InsnID*/0, 12076 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12077 // GIR_Coverage, 3555, 12078 GIR_Done, 12079 // Label 864: @27736 12080 GIM_Try, /*On fail goto*//*Label 865*/ 27787, // Rule ID 3556 // 12081 GIM_CheckFeatures, GIFBS_HasLSE, 12082 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 12083 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 12084 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12085 // MIs[0] Rn 12086 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12089 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_8>><<P:Predicate_atomic_load_add_8_acquire>> => (LDADDAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 12090 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAB, 12091 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12094 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12095 GIR_EraseFromParent, /*InsnID*/0, 12096 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12097 // GIR_Coverage, 3556, 12098 GIR_Done, 12099 // Label 865: @27787 12100 GIM_Try, /*On fail goto*//*Label 866*/ 27838, // Rule ID 3557 // 12101 GIM_CheckFeatures, GIFBS_HasLSE, 12102 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 12103 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 12104 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12105 // MIs[0] Rn 12106 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12109 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_8>><<P:Predicate_atomic_load_add_8_release>> => (LDADDLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 12110 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLB, 12111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12112 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12114 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12115 GIR_EraseFromParent, /*InsnID*/0, 12116 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12117 // GIR_Coverage, 3557, 12118 GIR_Done, 12119 // Label 866: @27838 12120 GIM_Try, /*On fail goto*//*Label 867*/ 27889, // Rule ID 3558 // 12121 GIM_CheckFeatures, GIFBS_HasLSE, 12122 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 12123 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 12124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12125 // MIs[0] Rn 12126 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12128 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12129 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_8>><<P:Predicate_atomic_load_add_8_acq_rel>> => (LDADDALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 12130 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB, 12131 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12134 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12135 GIR_EraseFromParent, /*InsnID*/0, 12136 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12137 // GIR_Coverage, 3558, 12138 GIR_Done, 12139 // Label 867: @27889 12140 GIM_Try, /*On fail goto*//*Label 868*/ 27940, // Rule ID 3559 // 12141 GIM_CheckFeatures, GIFBS_HasLSE, 12142 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 12143 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 12144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12145 // MIs[0] Rn 12146 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12147 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12148 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12149 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_8>><<P:Predicate_atomic_load_add_8_seq_cst>> => (LDADDALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 12150 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB, 12151 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12152 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12153 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12154 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12155 GIR_EraseFromParent, /*InsnID*/0, 12156 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12157 // GIR_Coverage, 3559, 12158 GIR_Done, 12159 // Label 868: @27940 12160 GIM_Reject, 12161 // Label 853: @27941 12162 GIM_Reject, 12163 // Label 851: @27942 12164 GIM_Try, /*On fail goto*//*Label 869*/ 28188, 12165 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 12166 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 12167 GIM_Try, /*On fail goto*//*Label 870*/ 27999, // Rule ID 1816 // 12168 GIM_CheckFeatures, GIFBS_HasLSE, 12169 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 12170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 12171 // MIs[0] Rn 12172 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 12175 // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_monotonic>> => (LDADDX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 12176 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDX, 12177 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12178 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12179 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12180 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12181 GIR_EraseFromParent, /*InsnID*/0, 12182 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12183 // GIR_Coverage, 1816, 12184 GIR_Done, 12185 // Label 870: @27999 12186 GIM_Try, /*On fail goto*//*Label 871*/ 28046, // Rule ID 1817 // 12187 GIM_CheckFeatures, GIFBS_HasLSE, 12188 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 12189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 12190 // MIs[0] Rn 12191 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12192 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12193 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 12194 // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acquire>> => (LDADDAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 12195 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAX, 12196 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12197 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12198 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12199 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12200 GIR_EraseFromParent, /*InsnID*/0, 12201 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12202 // GIR_Coverage, 1817, 12203 GIR_Done, 12204 // Label 871: @28046 12205 GIM_Try, /*On fail goto*//*Label 872*/ 28093, // Rule ID 1818 // 12206 GIM_CheckFeatures, GIFBS_HasLSE, 12207 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 12208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 12209 // MIs[0] Rn 12210 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12211 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12212 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 12213 // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_release>> => (LDADDLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 12214 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLX, 12215 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12216 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12217 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12218 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12219 GIR_EraseFromParent, /*InsnID*/0, 12220 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12221 // GIR_Coverage, 1818, 12222 GIR_Done, 12223 // Label 872: @28093 12224 GIM_Try, /*On fail goto*//*Label 873*/ 28140, // Rule ID 1819 // 12225 GIM_CheckFeatures, GIFBS_HasLSE, 12226 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 12227 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 12228 // MIs[0] Rn 12229 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12230 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12231 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 12232 // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acq_rel>> => (LDADDALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 12233 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX, 12234 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12235 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12237 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12238 GIR_EraseFromParent, /*InsnID*/0, 12239 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12240 // GIR_Coverage, 1819, 12241 GIR_Done, 12242 // Label 873: @28140 12243 GIM_Try, /*On fail goto*//*Label 874*/ 28187, // Rule ID 1820 // 12244 GIM_CheckFeatures, GIFBS_HasLSE, 12245 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 12246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 12247 // MIs[0] Rn 12248 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12249 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12250 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 12251 // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_seq_cst>> => (LDADDALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 12252 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX, 12253 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12254 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12255 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12256 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12257 GIR_EraseFromParent, /*InsnID*/0, 12258 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12259 // GIR_Coverage, 1820, 12260 GIR_Done, 12261 // Label 874: @28187 12262 GIM_Reject, 12263 // Label 869: @28188 12264 GIM_Reject, 12265 // Label 852: @28189 12266 GIM_Reject, 12267 // Label 16: @28190 12268 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 877*/ 29598, 12269 /*GILLT_s32*//*Label 875*/ 28198, 12270 /*GILLT_s64*//*Label 876*/ 29256, 12271 // Label 875: @28198 12272 GIM_Try, /*On fail goto*//*Label 878*/ 29255, 12273 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 12274 GIM_Try, /*On fail goto*//*Label 879*/ 28274, // Rule ID 3740 // 12275 GIM_CheckFeatures, GIFBS_HasLSE, 12276 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 12277 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 12278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12279 // MIs[0] Rn 12280 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12281 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12282 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12283 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_monotonic>> => (LDADDW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12284 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12285 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, 12286 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12287 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12288 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12289 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12290 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDW, 12291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12292 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12293 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12294 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12295 GIR_EraseFromParent, /*InsnID*/0, 12296 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12297 // GIR_Coverage, 3740, 12298 GIR_Done, 12299 // Label 879: @28274 12300 GIM_Try, /*On fail goto*//*Label 880*/ 28344, // Rule ID 3741 // 12301 GIM_CheckFeatures, GIFBS_HasLSE, 12302 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 12303 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 12304 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12305 // MIs[0] Rn 12306 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12309 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acquire>> => (LDADDAW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12310 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12311 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, 12312 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12313 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12314 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12315 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12316 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAW, 12317 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12318 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12319 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12320 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12321 GIR_EraseFromParent, /*InsnID*/0, 12322 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12323 // GIR_Coverage, 3741, 12324 GIR_Done, 12325 // Label 880: @28344 12326 GIM_Try, /*On fail goto*//*Label 881*/ 28414, // Rule ID 3742 // 12327 GIM_CheckFeatures, GIFBS_HasLSE, 12328 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 12329 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 12330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12331 // MIs[0] Rn 12332 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12335 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_release>> => (LDADDLW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12336 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12337 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, 12338 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12339 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12340 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12341 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12342 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLW, 12343 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12344 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12345 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12346 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12347 GIR_EraseFromParent, /*InsnID*/0, 12348 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12349 // GIR_Coverage, 3742, 12350 GIR_Done, 12351 // Label 881: @28414 12352 GIM_Try, /*On fail goto*//*Label 882*/ 28484, // Rule ID 3743 // 12353 GIM_CheckFeatures, GIFBS_HasLSE, 12354 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 12355 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 12356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12357 // MIs[0] Rn 12358 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12361 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acq_rel>> => (LDADDALW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12362 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12363 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, 12364 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12365 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12366 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12367 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12368 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW, 12369 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12370 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12371 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12372 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12373 GIR_EraseFromParent, /*InsnID*/0, 12374 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12375 // GIR_Coverage, 3743, 12376 GIR_Done, 12377 // Label 882: @28484 12378 GIM_Try, /*On fail goto*//*Label 883*/ 28554, // Rule ID 3744 // 12379 GIM_CheckFeatures, GIFBS_HasLSE, 12380 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 12381 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 12382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12383 // MIs[0] Rn 12384 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12386 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12387 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_seq_cst>> => (LDADDALW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12388 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12389 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, 12390 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12391 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12392 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12393 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12394 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW, 12395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12396 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12397 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12398 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12399 GIR_EraseFromParent, /*InsnID*/0, 12400 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12401 // GIR_Coverage, 3744, 12402 GIR_Done, 12403 // Label 883: @28554 12404 GIM_Try, /*On fail goto*//*Label 884*/ 28624, // Rule ID 3745 // 12405 GIM_CheckFeatures, GIFBS_HasLSE, 12406 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 12407 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 12408 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12409 // MIs[0] Rn 12410 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12413 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_16>><<P:Predicate_atomic_load_sub_16_monotonic>> => (LDADDH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12414 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12415 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, 12416 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12417 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12418 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12419 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDH, 12421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12422 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12423 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12424 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12425 GIR_EraseFromParent, /*InsnID*/0, 12426 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12427 // GIR_Coverage, 3745, 12428 GIR_Done, 12429 // Label 884: @28624 12430 GIM_Try, /*On fail goto*//*Label 885*/ 28694, // Rule ID 3746 // 12431 GIM_CheckFeatures, GIFBS_HasLSE, 12432 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 12433 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 12434 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12435 // MIs[0] Rn 12436 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12439 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_16>><<P:Predicate_atomic_load_sub_16_acquire>> => (LDADDAH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12440 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12441 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, 12442 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12443 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12444 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12445 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12446 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAH, 12447 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12448 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12449 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12450 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12451 GIR_EraseFromParent, /*InsnID*/0, 12452 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12453 // GIR_Coverage, 3746, 12454 GIR_Done, 12455 // Label 885: @28694 12456 GIM_Try, /*On fail goto*//*Label 886*/ 28764, // Rule ID 3747 // 12457 GIM_CheckFeatures, GIFBS_HasLSE, 12458 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 12459 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 12460 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12461 // MIs[0] Rn 12462 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12463 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12464 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12465 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_16>><<P:Predicate_atomic_load_sub_16_release>> => (LDADDLH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12466 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12467 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, 12468 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12469 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12470 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12471 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12472 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLH, 12473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12474 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12476 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12477 GIR_EraseFromParent, /*InsnID*/0, 12478 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12479 // GIR_Coverage, 3747, 12480 GIR_Done, 12481 // Label 886: @28764 12482 GIM_Try, /*On fail goto*//*Label 887*/ 28834, // Rule ID 3748 // 12483 GIM_CheckFeatures, GIFBS_HasLSE, 12484 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 12485 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 12486 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12487 // MIs[0] Rn 12488 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12490 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12491 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_16>><<P:Predicate_atomic_load_sub_16_acq_rel>> => (LDADDALH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12492 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12493 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, 12494 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12495 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12496 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12497 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12498 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH, 12499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12500 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12501 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12502 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12503 GIR_EraseFromParent, /*InsnID*/0, 12504 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12505 // GIR_Coverage, 3748, 12506 GIR_Done, 12507 // Label 887: @28834 12508 GIM_Try, /*On fail goto*//*Label 888*/ 28904, // Rule ID 3749 // 12509 GIM_CheckFeatures, GIFBS_HasLSE, 12510 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 12511 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 12512 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12513 // MIs[0] Rn 12514 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12517 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_16>><<P:Predicate_atomic_load_sub_16_seq_cst>> => (LDADDALH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12518 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12519 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, 12520 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12521 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12522 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12523 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH, 12525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12526 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12528 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12529 GIR_EraseFromParent, /*InsnID*/0, 12530 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12531 // GIR_Coverage, 3749, 12532 GIR_Done, 12533 // Label 888: @28904 12534 GIM_Try, /*On fail goto*//*Label 889*/ 28974, // Rule ID 3750 // 12535 GIM_CheckFeatures, GIFBS_HasLSE, 12536 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 12537 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 12538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12539 // MIs[0] Rn 12540 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12542 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12543 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_8>><<P:Predicate_atomic_load_sub_8_monotonic>> => (LDADDB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12544 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12545 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, 12546 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12547 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12548 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12549 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12550 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDB, 12551 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12552 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12553 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12554 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12555 GIR_EraseFromParent, /*InsnID*/0, 12556 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12557 // GIR_Coverage, 3750, 12558 GIR_Done, 12559 // Label 889: @28974 12560 GIM_Try, /*On fail goto*//*Label 890*/ 29044, // Rule ID 3751 // 12561 GIM_CheckFeatures, GIFBS_HasLSE, 12562 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 12563 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 12564 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12565 // MIs[0] Rn 12566 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12567 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12569 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_8>><<P:Predicate_atomic_load_sub_8_acquire>> => (LDADDAB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12570 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12571 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, 12572 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12573 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12574 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12575 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12576 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAB, 12577 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12578 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12579 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12580 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12581 GIR_EraseFromParent, /*InsnID*/0, 12582 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12583 // GIR_Coverage, 3751, 12584 GIR_Done, 12585 // Label 890: @29044 12586 GIM_Try, /*On fail goto*//*Label 891*/ 29114, // Rule ID 3752 // 12587 GIM_CheckFeatures, GIFBS_HasLSE, 12588 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 12589 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 12590 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12591 // MIs[0] Rn 12592 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12595 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_8>><<P:Predicate_atomic_load_sub_8_release>> => (LDADDLB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12596 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12597 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, 12598 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12599 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12600 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12601 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLB, 12603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12604 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12606 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12607 GIR_EraseFromParent, /*InsnID*/0, 12608 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12609 // GIR_Coverage, 3752, 12610 GIR_Done, 12611 // Label 891: @29114 12612 GIM_Try, /*On fail goto*//*Label 892*/ 29184, // Rule ID 3753 // 12613 GIM_CheckFeatures, GIFBS_HasLSE, 12614 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 12615 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 12616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12617 // MIs[0] Rn 12618 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12621 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_8>><<P:Predicate_atomic_load_sub_8_acq_rel>> => (LDADDALB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12622 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12623 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, 12624 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12625 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12626 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12627 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12628 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB, 12629 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12630 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12631 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12632 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12633 GIR_EraseFromParent, /*InsnID*/0, 12634 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12635 // GIR_Coverage, 3753, 12636 GIR_Done, 12637 // Label 892: @29184 12638 GIM_Try, /*On fail goto*//*Label 893*/ 29254, // Rule ID 3754 // 12639 GIM_CheckFeatures, GIFBS_HasLSE, 12640 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 12641 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 12642 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12643 // MIs[0] Rn 12644 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12645 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12646 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12647 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_8>><<P:Predicate_atomic_load_sub_8_seq_cst>> => (LDADDALB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12648 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12649 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, 12650 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12651 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12652 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12653 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12654 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB, 12655 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12656 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12658 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12659 GIR_EraseFromParent, /*InsnID*/0, 12660 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12661 // GIR_Coverage, 3754, 12662 GIR_Done, 12663 // Label 893: @29254 12664 GIM_Reject, 12665 // Label 878: @29255 12666 GIM_Reject, 12667 // Label 876: @29256 12668 GIM_Try, /*On fail goto*//*Label 894*/ 29597, 12669 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 12670 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 12671 GIM_Try, /*On fail goto*//*Label 895*/ 29332, // Rule ID 3735 // 12672 GIM_CheckFeatures, GIFBS_HasLSE, 12673 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 12674 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 12675 // MIs[0] Rn 12676 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12677 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12678 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 12679 // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_monotonic>> => (LDADDX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12680 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 12681 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, 12682 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12683 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, 12684 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12685 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDX, 12687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12688 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12690 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12691 GIR_EraseFromParent, /*InsnID*/0, 12692 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12693 // GIR_Coverage, 3735, 12694 GIR_Done, 12695 // Label 895: @29332 12696 GIM_Try, /*On fail goto*//*Label 896*/ 29398, // Rule ID 3736 // 12697 GIM_CheckFeatures, GIFBS_HasLSE, 12698 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 12699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 12700 // MIs[0] Rn 12701 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12703 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 12704 // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acquire>> => (LDADDAX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12705 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 12706 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, 12707 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12708 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, 12709 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12710 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12711 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAX, 12712 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12713 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12715 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12716 GIR_EraseFromParent, /*InsnID*/0, 12717 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12718 // GIR_Coverage, 3736, 12719 GIR_Done, 12720 // Label 896: @29398 12721 GIM_Try, /*On fail goto*//*Label 897*/ 29464, // Rule ID 3737 // 12722 GIM_CheckFeatures, GIFBS_HasLSE, 12723 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 12724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 12725 // MIs[0] Rn 12726 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12728 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 12729 // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_release>> => (LDADDLX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12730 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 12731 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, 12732 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12733 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, 12734 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12735 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12736 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLX, 12737 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12738 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12739 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12740 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12741 GIR_EraseFromParent, /*InsnID*/0, 12742 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12743 // GIR_Coverage, 3737, 12744 GIR_Done, 12745 // Label 897: @29464 12746 GIM_Try, /*On fail goto*//*Label 898*/ 29530, // Rule ID 3738 // 12747 GIM_CheckFeatures, GIFBS_HasLSE, 12748 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 12749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 12750 // MIs[0] Rn 12751 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 12754 // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acq_rel>> => (LDADDALX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12755 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 12756 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, 12757 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12758 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, 12759 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12760 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12761 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX, 12762 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12763 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12765 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12766 GIR_EraseFromParent, /*InsnID*/0, 12767 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12768 // GIR_Coverage, 3738, 12769 GIR_Done, 12770 // Label 898: @29530 12771 GIM_Try, /*On fail goto*//*Label 899*/ 29596, // Rule ID 3739 // 12772 GIM_CheckFeatures, GIFBS_HasLSE, 12773 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 12774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 12775 // MIs[0] Rn 12776 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 12779 // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_seq_cst>> => (LDADDALX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12780 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 12781 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, 12782 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12783 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, 12784 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12785 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12786 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX, 12787 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12788 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12789 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12790 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12791 GIR_EraseFromParent, /*InsnID*/0, 12792 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12793 // GIR_Coverage, 3739, 12794 GIR_Done, 12795 // Label 899: @29596 12796 GIM_Reject, 12797 // Label 894: @29597 12798 GIM_Reject, 12799 // Label 877: @29598 12800 GIM_Reject, 12801 // Label 17: @29599 12802 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 902*/ 31007, 12803 /*GILLT_s32*//*Label 900*/ 29607, 12804 /*GILLT_s64*//*Label 901*/ 30665, 12805 // Label 900: @29607 12806 GIM_Try, /*On fail goto*//*Label 903*/ 30664, 12807 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 12808 GIM_Try, /*On fail goto*//*Label 904*/ 29683, // Rule ID 3760 // 12809 GIM_CheckFeatures, GIFBS_HasLSE, 12810 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 12811 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 12812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12813 // MIs[0] Rn 12814 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12817 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_monotonic>> => (LDCLRW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12818 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12819 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, 12820 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12821 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12822 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12823 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12824 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRW, 12825 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12826 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12828 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12829 GIR_EraseFromParent, /*InsnID*/0, 12830 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12831 // GIR_Coverage, 3760, 12832 GIR_Done, 12833 // Label 904: @29683 12834 GIM_Try, /*On fail goto*//*Label 905*/ 29753, // Rule ID 3761 // 12835 GIM_CheckFeatures, GIFBS_HasLSE, 12836 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 12837 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 12838 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12839 // MIs[0] Rn 12840 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12841 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12843 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acquire>> => (LDCLRAW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12844 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12845 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, 12846 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12847 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12848 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12849 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12850 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAW, 12851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12852 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12853 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12854 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12855 GIR_EraseFromParent, /*InsnID*/0, 12856 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12857 // GIR_Coverage, 3761, 12858 GIR_Done, 12859 // Label 905: @29753 12860 GIM_Try, /*On fail goto*//*Label 906*/ 29823, // Rule ID 3762 // 12861 GIM_CheckFeatures, GIFBS_HasLSE, 12862 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 12863 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 12864 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12865 // MIs[0] Rn 12866 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12867 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12869 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_release>> => (LDCLRLW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12870 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12871 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, 12872 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12873 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12874 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12875 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12876 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLW, 12877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12878 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12880 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12881 GIR_EraseFromParent, /*InsnID*/0, 12882 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12883 // GIR_Coverage, 3762, 12884 GIR_Done, 12885 // Label 906: @29823 12886 GIM_Try, /*On fail goto*//*Label 907*/ 29893, // Rule ID 3763 // 12887 GIM_CheckFeatures, GIFBS_HasLSE, 12888 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 12889 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 12890 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12891 // MIs[0] Rn 12892 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12894 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12895 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acq_rel>> => (LDCLRALW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12896 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12897 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, 12898 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12899 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12900 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12901 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12902 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALW, 12903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12904 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12905 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12906 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12907 GIR_EraseFromParent, /*InsnID*/0, 12908 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12909 // GIR_Coverage, 3763, 12910 GIR_Done, 12911 // Label 907: @29893 12912 GIM_Try, /*On fail goto*//*Label 908*/ 29963, // Rule ID 3764 // 12913 GIM_CheckFeatures, GIFBS_HasLSE, 12914 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 12915 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 12916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12917 // MIs[0] Rn 12918 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12921 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_seq_cst>> => (LDCLRALW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12922 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12923 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, 12924 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12925 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12926 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12927 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12928 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALW, 12929 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12930 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12931 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12932 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12933 GIR_EraseFromParent, /*InsnID*/0, 12934 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12935 // GIR_Coverage, 3764, 12936 GIR_Done, 12937 // Label 908: @29963 12938 GIM_Try, /*On fail goto*//*Label 909*/ 30033, // Rule ID 3765 // 12939 GIM_CheckFeatures, GIFBS_HasLSE, 12940 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 12941 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 12942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12943 // MIs[0] Rn 12944 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12945 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12946 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12947 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_16>><<P:Predicate_atomic_load_and_16_monotonic>> => (LDCLRH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12948 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12949 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, 12950 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12951 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12952 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12953 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12954 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRH, 12955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12956 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12957 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12958 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12959 GIR_EraseFromParent, /*InsnID*/0, 12960 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12961 // GIR_Coverage, 3765, 12962 GIR_Done, 12963 // Label 909: @30033 12964 GIM_Try, /*On fail goto*//*Label 910*/ 30103, // Rule ID 3766 // 12965 GIM_CheckFeatures, GIFBS_HasLSE, 12966 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 12967 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 12968 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12969 // MIs[0] Rn 12970 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12973 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_16>><<P:Predicate_atomic_load_and_16_acquire>> => (LDCLRAH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 12974 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12975 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, 12976 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12977 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 12978 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 12979 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12980 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAH, 12981 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 12982 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12983 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 12984 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12985 GIR_EraseFromParent, /*InsnID*/0, 12986 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12987 // GIR_Coverage, 3766, 12988 GIR_Done, 12989 // Label 910: @30103 12990 GIM_Try, /*On fail goto*//*Label 911*/ 30173, // Rule ID 3767 // 12991 GIM_CheckFeatures, GIFBS_HasLSE, 12992 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 12993 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 12994 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 12995 // MIs[0] Rn 12996 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12997 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 12998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 12999 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_16>><<P:Predicate_atomic_load_and_16_release>> => (LDCLRLH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 13000 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13001 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, 13002 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13003 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 13004 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13005 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13006 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLH, 13007 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13008 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13010 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13011 GIR_EraseFromParent, /*InsnID*/0, 13012 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13013 // GIR_Coverage, 3767, 13014 GIR_Done, 13015 // Label 911: @30173 13016 GIM_Try, /*On fail goto*//*Label 912*/ 30243, // Rule ID 3768 // 13017 GIM_CheckFeatures, GIFBS_HasLSE, 13018 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 13019 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 13020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13021 // MIs[0] Rn 13022 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13023 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13024 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13025 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_16>><<P:Predicate_atomic_load_and_16_acq_rel>> => (LDCLRALH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 13026 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13027 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, 13028 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13029 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 13030 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13031 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13032 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALH, 13033 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13034 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13035 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13036 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13037 GIR_EraseFromParent, /*InsnID*/0, 13038 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13039 // GIR_Coverage, 3768, 13040 GIR_Done, 13041 // Label 912: @30243 13042 GIM_Try, /*On fail goto*//*Label 913*/ 30313, // Rule ID 3769 // 13043 GIM_CheckFeatures, GIFBS_HasLSE, 13044 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 13045 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 13046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13047 // MIs[0] Rn 13048 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13050 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13051 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_16>><<P:Predicate_atomic_load_and_16_seq_cst>> => (LDCLRALH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 13052 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13053 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, 13054 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13055 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 13056 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13057 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13058 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALH, 13059 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13060 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13061 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13062 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13063 GIR_EraseFromParent, /*InsnID*/0, 13064 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13065 // GIR_Coverage, 3769, 13066 GIR_Done, 13067 // Label 913: @30313 13068 GIM_Try, /*On fail goto*//*Label 914*/ 30383, // Rule ID 3770 // 13069 GIM_CheckFeatures, GIFBS_HasLSE, 13070 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 13071 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 13072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13073 // MIs[0] Rn 13074 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13076 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13077 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_8>><<P:Predicate_atomic_load_and_8_monotonic>> => (LDCLRB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 13078 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13079 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, 13080 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13081 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 13082 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13083 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13084 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRB, 13085 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13086 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13087 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13088 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13089 GIR_EraseFromParent, /*InsnID*/0, 13090 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13091 // GIR_Coverage, 3770, 13092 GIR_Done, 13093 // Label 914: @30383 13094 GIM_Try, /*On fail goto*//*Label 915*/ 30453, // Rule ID 3771 // 13095 GIM_CheckFeatures, GIFBS_HasLSE, 13096 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 13097 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 13098 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13099 // MIs[0] Rn 13100 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13103 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_8>><<P:Predicate_atomic_load_and_8_acquire>> => (LDCLRAB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 13104 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13105 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, 13106 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13107 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 13108 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13109 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13110 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAB, 13111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13112 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13114 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13115 GIR_EraseFromParent, /*InsnID*/0, 13116 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13117 // GIR_Coverage, 3771, 13118 GIR_Done, 13119 // Label 915: @30453 13120 GIM_Try, /*On fail goto*//*Label 916*/ 30523, // Rule ID 3772 // 13121 GIM_CheckFeatures, GIFBS_HasLSE, 13122 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 13123 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 13124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13125 // MIs[0] Rn 13126 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13128 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13129 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_8>><<P:Predicate_atomic_load_and_8_release>> => (LDCLRLB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 13130 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13131 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, 13132 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13133 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 13134 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13135 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13136 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLB, 13137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13138 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13140 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13141 GIR_EraseFromParent, /*InsnID*/0, 13142 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13143 // GIR_Coverage, 3772, 13144 GIR_Done, 13145 // Label 916: @30523 13146 GIM_Try, /*On fail goto*//*Label 917*/ 30593, // Rule ID 3773 // 13147 GIM_CheckFeatures, GIFBS_HasLSE, 13148 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 13149 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 13150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13151 // MIs[0] Rn 13152 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13155 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_8>><<P:Predicate_atomic_load_and_8_acq_rel>> => (LDCLRALB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 13156 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13157 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, 13158 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13159 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 13160 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13161 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALB, 13163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13164 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13166 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13167 GIR_EraseFromParent, /*InsnID*/0, 13168 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13169 // GIR_Coverage, 3773, 13170 GIR_Done, 13171 // Label 917: @30593 13172 GIM_Try, /*On fail goto*//*Label 918*/ 30663, // Rule ID 3774 // 13173 GIM_CheckFeatures, GIFBS_HasLSE, 13174 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 13175 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 13176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13177 // MIs[0] Rn 13178 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13179 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13181 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_8>><<P:Predicate_atomic_load_and_8_seq_cst>> => (LDCLRALB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 13182 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13183 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, 13184 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13185 GIR_AddRegister, /*InsnID*/1, AArch64::WZR, 13186 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13187 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13188 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALB, 13189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13190 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13191 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13192 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13193 GIR_EraseFromParent, /*InsnID*/0, 13194 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13195 // GIR_Coverage, 3774, 13196 GIR_Done, 13197 // Label 918: @30663 13198 GIM_Reject, 13199 // Label 903: @30664 13200 GIM_Reject, 13201 // Label 901: @30665 13202 GIM_Try, /*On fail goto*//*Label 919*/ 31006, 13203 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13204 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 13205 GIM_Try, /*On fail goto*//*Label 920*/ 30741, // Rule ID 3755 // 13206 GIM_CheckFeatures, GIFBS_HasLSE, 13207 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 13208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 13209 // MIs[0] Rn 13210 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13211 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13212 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 13213 // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_monotonic>> => (LDCLRX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 13214 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 13215 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, 13216 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13217 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, 13218 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13219 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13220 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRX, 13221 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13222 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13224 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13225 GIR_EraseFromParent, /*InsnID*/0, 13226 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13227 // GIR_Coverage, 3755, 13228 GIR_Done, 13229 // Label 920: @30741 13230 GIM_Try, /*On fail goto*//*Label 921*/ 30807, // Rule ID 3756 // 13231 GIM_CheckFeatures, GIFBS_HasLSE, 13232 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 13233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 13234 // MIs[0] Rn 13235 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 13238 // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acquire>> => (LDCLRAX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 13239 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 13240 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, 13241 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13242 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, 13243 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13244 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13245 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAX, 13246 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13247 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13248 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13249 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13250 GIR_EraseFromParent, /*InsnID*/0, 13251 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13252 // GIR_Coverage, 3756, 13253 GIR_Done, 13254 // Label 921: @30807 13255 GIM_Try, /*On fail goto*//*Label 922*/ 30873, // Rule ID 3757 // 13256 GIM_CheckFeatures, GIFBS_HasLSE, 13257 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 13258 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 13259 // MIs[0] Rn 13260 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 13263 // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_release>> => (LDCLRLX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 13264 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 13265 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, 13266 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13267 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, 13268 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13269 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13270 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLX, 13271 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13272 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13273 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13274 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13275 GIR_EraseFromParent, /*InsnID*/0, 13276 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13277 // GIR_Coverage, 3757, 13278 GIR_Done, 13279 // Label 922: @30873 13280 GIM_Try, /*On fail goto*//*Label 923*/ 30939, // Rule ID 3758 // 13281 GIM_CheckFeatures, GIFBS_HasLSE, 13282 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 13283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 13284 // MIs[0] Rn 13285 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 13288 // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acq_rel>> => (LDCLRALX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 13289 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 13290 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, 13291 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13292 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, 13293 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13294 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13295 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALX, 13296 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13297 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13298 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13299 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13300 GIR_EraseFromParent, /*InsnID*/0, 13301 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13302 // GIR_Coverage, 3758, 13303 GIR_Done, 13304 // Label 923: @30939 13305 GIM_Try, /*On fail goto*//*Label 924*/ 31005, // Rule ID 3759 // 13306 GIM_CheckFeatures, GIFBS_HasLSE, 13307 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 13308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 13309 // MIs[0] Rn 13310 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13311 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 13313 // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_seq_cst>> => (LDCLRALX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) 13314 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 13315 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, 13316 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13317 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, 13318 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13319 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13320 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALX, 13321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13322 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13323 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13324 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13325 GIR_EraseFromParent, /*InsnID*/0, 13326 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13327 // GIR_Coverage, 3759, 13328 GIR_Done, 13329 // Label 924: @31005 13330 GIM_Reject, 13331 // Label 919: @31006 13332 GIM_Reject, 13333 // Label 902: @31007 13334 GIM_Reject, 13335 // Label 18: @31008 13336 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 927*/ 32036, 13337 /*GILLT_s32*//*Label 925*/ 31016, 13338 /*GILLT_s64*//*Label 926*/ 31789, 13339 // Label 925: @31016 13340 GIM_Try, /*On fail goto*//*Label 928*/ 31788, 13341 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13342 GIM_Try, /*On fail goto*//*Label 929*/ 31073, // Rule ID 3565 // 13343 GIM_CheckFeatures, GIFBS_HasLSE, 13344 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 13345 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 13346 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13347 // MIs[0] Rn 13348 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13351 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_monotonic>> => (LDSETW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13352 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETW, 13353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13356 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13357 GIR_EraseFromParent, /*InsnID*/0, 13358 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13359 // GIR_Coverage, 3565, 13360 GIR_Done, 13361 // Label 929: @31073 13362 GIM_Try, /*On fail goto*//*Label 930*/ 31124, // Rule ID 3566 // 13363 GIM_CheckFeatures, GIFBS_HasLSE, 13364 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 13365 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 13366 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13367 // MIs[0] Rn 13368 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13371 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acquire>> => (LDSETAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13372 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAW, 13373 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13374 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13375 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13376 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13377 GIR_EraseFromParent, /*InsnID*/0, 13378 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13379 // GIR_Coverage, 3566, 13380 GIR_Done, 13381 // Label 930: @31124 13382 GIM_Try, /*On fail goto*//*Label 931*/ 31175, // Rule ID 3567 // 13383 GIM_CheckFeatures, GIFBS_HasLSE, 13384 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 13385 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 13386 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13387 // MIs[0] Rn 13388 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13391 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_release>> => (LDSETLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13392 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLW, 13393 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13394 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13396 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13397 GIR_EraseFromParent, /*InsnID*/0, 13398 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13399 // GIR_Coverage, 3567, 13400 GIR_Done, 13401 // Label 931: @31175 13402 GIM_Try, /*On fail goto*//*Label 932*/ 31226, // Rule ID 3568 // 13403 GIM_CheckFeatures, GIFBS_HasLSE, 13404 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 13405 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 13406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13407 // MIs[0] Rn 13408 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13409 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13410 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13411 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acq_rel>> => (LDSETALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13412 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALW, 13413 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13414 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13415 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13416 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13417 GIR_EraseFromParent, /*InsnID*/0, 13418 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13419 // GIR_Coverage, 3568, 13420 GIR_Done, 13421 // Label 932: @31226 13422 GIM_Try, /*On fail goto*//*Label 933*/ 31277, // Rule ID 3569 // 13423 GIM_CheckFeatures, GIFBS_HasLSE, 13424 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 13425 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 13426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13427 // MIs[0] Rn 13428 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13431 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_seq_cst>> => (LDSETALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13432 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALW, 13433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13435 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13436 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13437 GIR_EraseFromParent, /*InsnID*/0, 13438 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13439 // GIR_Coverage, 3569, 13440 GIR_Done, 13441 // Label 933: @31277 13442 GIM_Try, /*On fail goto*//*Label 934*/ 31328, // Rule ID 3570 // 13443 GIM_CheckFeatures, GIFBS_HasLSE, 13444 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 13445 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 13446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13447 // MIs[0] Rn 13448 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13451 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_16>><<P:Predicate_atomic_load_or_16_monotonic>> => (LDSETH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13452 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETH, 13453 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13454 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13456 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13457 GIR_EraseFromParent, /*InsnID*/0, 13458 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13459 // GIR_Coverage, 3570, 13460 GIR_Done, 13461 // Label 934: @31328 13462 GIM_Try, /*On fail goto*//*Label 935*/ 31379, // Rule ID 3571 // 13463 GIM_CheckFeatures, GIFBS_HasLSE, 13464 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 13465 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 13466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13467 // MIs[0] Rn 13468 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13471 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_16>><<P:Predicate_atomic_load_or_16_acquire>> => (LDSETAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13472 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAH, 13473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13476 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13477 GIR_EraseFromParent, /*InsnID*/0, 13478 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13479 // GIR_Coverage, 3571, 13480 GIR_Done, 13481 // Label 935: @31379 13482 GIM_Try, /*On fail goto*//*Label 936*/ 31430, // Rule ID 3572 // 13483 GIM_CheckFeatures, GIFBS_HasLSE, 13484 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 13485 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 13486 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13487 // MIs[0] Rn 13488 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13490 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13491 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_16>><<P:Predicate_atomic_load_or_16_release>> => (LDSETLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13492 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLH, 13493 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13494 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13495 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13496 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13497 GIR_EraseFromParent, /*InsnID*/0, 13498 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13499 // GIR_Coverage, 3572, 13500 GIR_Done, 13501 // Label 936: @31430 13502 GIM_Try, /*On fail goto*//*Label 937*/ 31481, // Rule ID 3573 // 13503 GIM_CheckFeatures, GIFBS_HasLSE, 13504 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 13505 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 13506 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13507 // MIs[0] Rn 13508 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13510 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13511 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_16>><<P:Predicate_atomic_load_or_16_acq_rel>> => (LDSETALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13512 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALH, 13513 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13514 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13515 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13516 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13517 GIR_EraseFromParent, /*InsnID*/0, 13518 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13519 // GIR_Coverage, 3573, 13520 GIR_Done, 13521 // Label 937: @31481 13522 GIM_Try, /*On fail goto*//*Label 938*/ 31532, // Rule ID 3574 // 13523 GIM_CheckFeatures, GIFBS_HasLSE, 13524 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 13525 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 13526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13527 // MIs[0] Rn 13528 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13530 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13531 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_16>><<P:Predicate_atomic_load_or_16_seq_cst>> => (LDSETALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13532 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALH, 13533 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13534 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13536 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13537 GIR_EraseFromParent, /*InsnID*/0, 13538 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13539 // GIR_Coverage, 3574, 13540 GIR_Done, 13541 // Label 938: @31532 13542 GIM_Try, /*On fail goto*//*Label 939*/ 31583, // Rule ID 3575 // 13543 GIM_CheckFeatures, GIFBS_HasLSE, 13544 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 13545 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 13546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13547 // MIs[0] Rn 13548 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13549 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13550 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13551 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_8>><<P:Predicate_atomic_load_or_8_monotonic>> => (LDSETB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13552 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETB, 13553 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13554 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13555 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13556 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13557 GIR_EraseFromParent, /*InsnID*/0, 13558 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13559 // GIR_Coverage, 3575, 13560 GIR_Done, 13561 // Label 939: @31583 13562 GIM_Try, /*On fail goto*//*Label 940*/ 31634, // Rule ID 3576 // 13563 GIM_CheckFeatures, GIFBS_HasLSE, 13564 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 13565 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 13566 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13567 // MIs[0] Rn 13568 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13569 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13570 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13571 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_8>><<P:Predicate_atomic_load_or_8_acquire>> => (LDSETAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13572 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAB, 13573 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13574 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13575 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13576 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13577 GIR_EraseFromParent, /*InsnID*/0, 13578 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13579 // GIR_Coverage, 3576, 13580 GIR_Done, 13581 // Label 940: @31634 13582 GIM_Try, /*On fail goto*//*Label 941*/ 31685, // Rule ID 3577 // 13583 GIM_CheckFeatures, GIFBS_HasLSE, 13584 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 13585 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 13586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13587 // MIs[0] Rn 13588 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13589 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13590 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13591 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_8>><<P:Predicate_atomic_load_or_8_release>> => (LDSETLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13592 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLB, 13593 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13594 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13595 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13596 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13597 GIR_EraseFromParent, /*InsnID*/0, 13598 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13599 // GIR_Coverage, 3577, 13600 GIR_Done, 13601 // Label 941: @31685 13602 GIM_Try, /*On fail goto*//*Label 942*/ 31736, // Rule ID 3578 // 13603 GIM_CheckFeatures, GIFBS_HasLSE, 13604 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 13605 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 13606 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13607 // MIs[0] Rn 13608 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13609 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13610 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13611 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_8>><<P:Predicate_atomic_load_or_8_acq_rel>> => (LDSETALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13612 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALB, 13613 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13614 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13615 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13616 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13617 GIR_EraseFromParent, /*InsnID*/0, 13618 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13619 // GIR_Coverage, 3578, 13620 GIR_Done, 13621 // Label 942: @31736 13622 GIM_Try, /*On fail goto*//*Label 943*/ 31787, // Rule ID 3579 // 13623 GIM_CheckFeatures, GIFBS_HasLSE, 13624 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 13625 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 13626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13627 // MIs[0] Rn 13628 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13631 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_8>><<P:Predicate_atomic_load_or_8_seq_cst>> => (LDSETALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALB, 13633 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13634 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13635 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13636 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13637 GIR_EraseFromParent, /*InsnID*/0, 13638 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13639 // GIR_Coverage, 3579, 13640 GIR_Done, 13641 // Label 943: @31787 13642 GIM_Reject, 13643 // Label 928: @31788 13644 GIM_Reject, 13645 // Label 926: @31789 13646 GIM_Try, /*On fail goto*//*Label 944*/ 32035, 13647 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13648 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 13649 GIM_Try, /*On fail goto*//*Label 945*/ 31846, // Rule ID 3560 // 13650 GIM_CheckFeatures, GIFBS_HasLSE, 13651 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 13652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 13653 // MIs[0] Rn 13654 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13655 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 13657 // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_monotonic>> => (LDSETX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13658 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETX, 13659 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13660 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13661 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13662 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13663 GIR_EraseFromParent, /*InsnID*/0, 13664 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13665 // GIR_Coverage, 3560, 13666 GIR_Done, 13667 // Label 945: @31846 13668 GIM_Try, /*On fail goto*//*Label 946*/ 31893, // Rule ID 3561 // 13669 GIM_CheckFeatures, GIFBS_HasLSE, 13670 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 13671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 13672 // MIs[0] Rn 13673 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13674 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 13676 // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acquire>> => (LDSETAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13677 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAX, 13678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13679 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13680 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13681 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13682 GIR_EraseFromParent, /*InsnID*/0, 13683 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13684 // GIR_Coverage, 3561, 13685 GIR_Done, 13686 // Label 946: @31893 13687 GIM_Try, /*On fail goto*//*Label 947*/ 31940, // Rule ID 3562 // 13688 GIM_CheckFeatures, GIFBS_HasLSE, 13689 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 13690 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 13691 // MIs[0] Rn 13692 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13693 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 13695 // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_release>> => (LDSETLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13696 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLX, 13697 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13698 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13699 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13700 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13701 GIR_EraseFromParent, /*InsnID*/0, 13702 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13703 // GIR_Coverage, 3562, 13704 GIR_Done, 13705 // Label 947: @31940 13706 GIM_Try, /*On fail goto*//*Label 948*/ 31987, // Rule ID 3563 // 13707 GIM_CheckFeatures, GIFBS_HasLSE, 13708 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 13709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 13710 // MIs[0] Rn 13711 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13712 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 13714 // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acq_rel>> => (LDSETALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13715 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALX, 13716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13717 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13718 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13719 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13720 GIR_EraseFromParent, /*InsnID*/0, 13721 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13722 // GIR_Coverage, 3563, 13723 GIR_Done, 13724 // Label 948: @31987 13725 GIM_Try, /*On fail goto*//*Label 949*/ 32034, // Rule ID 3564 // 13726 GIM_CheckFeatures, GIFBS_HasLSE, 13727 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 13728 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 13729 // MIs[0] Rn 13730 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13731 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13732 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 13733 // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_seq_cst>> => (LDSETALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13734 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALX, 13735 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13736 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13737 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13738 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13739 GIR_EraseFromParent, /*InsnID*/0, 13740 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13741 // GIR_Coverage, 3564, 13742 GIR_Done, 13743 // Label 949: @32034 13744 GIM_Reject, 13745 // Label 944: @32035 13746 GIM_Reject, 13747 // Label 927: @32036 13748 GIM_Reject, 13749 // Label 19: @32037 13750 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 952*/ 33065, 13751 /*GILLT_s32*//*Label 950*/ 32045, 13752 /*GILLT_s64*//*Label 951*/ 32818, 13753 // Label 950: @32045 13754 GIM_Try, /*On fail goto*//*Label 953*/ 32817, 13755 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13756 GIM_Try, /*On fail goto*//*Label 954*/ 32102, // Rule ID 3585 // 13757 GIM_CheckFeatures, GIFBS_HasLSE, 13758 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 13759 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 13760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13761 // MIs[0] Rn 13762 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13763 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13765 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_monotonic>> => (LDEORW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13766 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORW, 13767 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13768 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13770 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13771 GIR_EraseFromParent, /*InsnID*/0, 13772 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13773 // GIR_Coverage, 3585, 13774 GIR_Done, 13775 // Label 954: @32102 13776 GIM_Try, /*On fail goto*//*Label 955*/ 32153, // Rule ID 3586 // 13777 GIM_CheckFeatures, GIFBS_HasLSE, 13778 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 13779 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 13780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13781 // MIs[0] Rn 13782 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13783 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13784 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13785 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acquire>> => (LDEORAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13786 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAW, 13787 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13788 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13789 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13790 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13791 GIR_EraseFromParent, /*InsnID*/0, 13792 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13793 // GIR_Coverage, 3586, 13794 GIR_Done, 13795 // Label 955: @32153 13796 GIM_Try, /*On fail goto*//*Label 956*/ 32204, // Rule ID 3587 // 13797 GIM_CheckFeatures, GIFBS_HasLSE, 13798 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 13799 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 13800 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13801 // MIs[0] Rn 13802 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13804 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13805 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_release>> => (LDEORLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13806 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLW, 13807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13808 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13809 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13810 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13811 GIR_EraseFromParent, /*InsnID*/0, 13812 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13813 // GIR_Coverage, 3587, 13814 GIR_Done, 13815 // Label 956: @32204 13816 GIM_Try, /*On fail goto*//*Label 957*/ 32255, // Rule ID 3588 // 13817 GIM_CheckFeatures, GIFBS_HasLSE, 13818 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 13819 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 13820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13821 // MIs[0] Rn 13822 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13823 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13824 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13825 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acq_rel>> => (LDEORALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13826 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALW, 13827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13829 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13830 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13831 GIR_EraseFromParent, /*InsnID*/0, 13832 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13833 // GIR_Coverage, 3588, 13834 GIR_Done, 13835 // Label 957: @32255 13836 GIM_Try, /*On fail goto*//*Label 958*/ 32306, // Rule ID 3589 // 13837 GIM_CheckFeatures, GIFBS_HasLSE, 13838 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 13839 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 13840 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13841 // MIs[0] Rn 13842 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13844 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13845 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_seq_cst>> => (LDEORALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13846 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALW, 13847 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13848 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13849 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13850 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13851 GIR_EraseFromParent, /*InsnID*/0, 13852 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13853 // GIR_Coverage, 3589, 13854 GIR_Done, 13855 // Label 958: @32306 13856 GIM_Try, /*On fail goto*//*Label 959*/ 32357, // Rule ID 3590 // 13857 GIM_CheckFeatures, GIFBS_HasLSE, 13858 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 13859 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 13860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13861 // MIs[0] Rn 13862 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13863 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13864 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13865 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_16>><<P:Predicate_atomic_load_xor_16_monotonic>> => (LDEORH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13866 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORH, 13867 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13868 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13869 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13870 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13871 GIR_EraseFromParent, /*InsnID*/0, 13872 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13873 // GIR_Coverage, 3590, 13874 GIR_Done, 13875 // Label 959: @32357 13876 GIM_Try, /*On fail goto*//*Label 960*/ 32408, // Rule ID 3591 // 13877 GIM_CheckFeatures, GIFBS_HasLSE, 13878 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 13879 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 13880 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13881 // MIs[0] Rn 13882 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13883 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13885 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_16>><<P:Predicate_atomic_load_xor_16_acquire>> => (LDEORAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13886 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAH, 13887 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13888 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13890 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13891 GIR_EraseFromParent, /*InsnID*/0, 13892 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13893 // GIR_Coverage, 3591, 13894 GIR_Done, 13895 // Label 960: @32408 13896 GIM_Try, /*On fail goto*//*Label 961*/ 32459, // Rule ID 3592 // 13897 GIM_CheckFeatures, GIFBS_HasLSE, 13898 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 13899 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 13900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13901 // MIs[0] Rn 13902 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13905 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_16>><<P:Predicate_atomic_load_xor_16_release>> => (LDEORLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13906 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLH, 13907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13909 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13910 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13911 GIR_EraseFromParent, /*InsnID*/0, 13912 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13913 // GIR_Coverage, 3592, 13914 GIR_Done, 13915 // Label 961: @32459 13916 GIM_Try, /*On fail goto*//*Label 962*/ 32510, // Rule ID 3593 // 13917 GIM_CheckFeatures, GIFBS_HasLSE, 13918 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 13919 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 13920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13921 // MIs[0] Rn 13922 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13925 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_16>><<P:Predicate_atomic_load_xor_16_acq_rel>> => (LDEORALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13926 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALH, 13927 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13928 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13929 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13930 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13931 GIR_EraseFromParent, /*InsnID*/0, 13932 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13933 // GIR_Coverage, 3593, 13934 GIR_Done, 13935 // Label 962: @32510 13936 GIM_Try, /*On fail goto*//*Label 963*/ 32561, // Rule ID 3594 // 13937 GIM_CheckFeatures, GIFBS_HasLSE, 13938 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 13939 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 13940 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13941 // MIs[0] Rn 13942 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13944 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13945 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_16>><<P:Predicate_atomic_load_xor_16_seq_cst>> => (LDEORALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13946 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALH, 13947 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13948 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13950 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13951 GIR_EraseFromParent, /*InsnID*/0, 13952 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13953 // GIR_Coverage, 3594, 13954 GIR_Done, 13955 // Label 963: @32561 13956 GIM_Try, /*On fail goto*//*Label 964*/ 32612, // Rule ID 3595 // 13957 GIM_CheckFeatures, GIFBS_HasLSE, 13958 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 13959 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 13960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13961 // MIs[0] Rn 13962 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13963 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13964 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13965 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_8>><<P:Predicate_atomic_load_xor_8_monotonic>> => (LDEORB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13966 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORB, 13967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13968 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13969 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13970 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13971 GIR_EraseFromParent, /*InsnID*/0, 13972 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13973 // GIR_Coverage, 3595, 13974 GIR_Done, 13975 // Label 964: @32612 13976 GIM_Try, /*On fail goto*//*Label 965*/ 32663, // Rule ID 3596 // 13977 GIM_CheckFeatures, GIFBS_HasLSE, 13978 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 13979 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 13980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 13981 // MIs[0] Rn 13982 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 13984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 13985 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_8>><<P:Predicate_atomic_load_xor_8_acquire>> => (LDEORAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 13986 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAB, 13987 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 13988 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 13989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 13990 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13991 GIR_EraseFromParent, /*InsnID*/0, 13992 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13993 // GIR_Coverage, 3596, 13994 GIR_Done, 13995 // Label 965: @32663 13996 GIM_Try, /*On fail goto*//*Label 966*/ 32714, // Rule ID 3597 // 13997 GIM_CheckFeatures, GIFBS_HasLSE, 13998 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 13999 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 14000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14001 // MIs[0] Rn 14002 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14003 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14005 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_8>><<P:Predicate_atomic_load_xor_8_release>> => (LDEORLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14006 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLB, 14007 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14010 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14011 GIR_EraseFromParent, /*InsnID*/0, 14012 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14013 // GIR_Coverage, 3597, 14014 GIR_Done, 14015 // Label 966: @32714 14016 GIM_Try, /*On fail goto*//*Label 967*/ 32765, // Rule ID 3598 // 14017 GIM_CheckFeatures, GIFBS_HasLSE, 14018 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 14019 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 14020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14021 // MIs[0] Rn 14022 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14023 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14024 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14025 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_8>><<P:Predicate_atomic_load_xor_8_acq_rel>> => (LDEORALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14026 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALB, 14027 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14028 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14030 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14031 GIR_EraseFromParent, /*InsnID*/0, 14032 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14033 // GIR_Coverage, 3598, 14034 GIR_Done, 14035 // Label 967: @32765 14036 GIM_Try, /*On fail goto*//*Label 968*/ 32816, // Rule ID 3599 // 14037 GIM_CheckFeatures, GIFBS_HasLSE, 14038 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 14039 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 14040 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14041 // MIs[0] Rn 14042 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14045 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_8>><<P:Predicate_atomic_load_xor_8_seq_cst>> => (LDEORALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14046 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALB, 14047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14050 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14051 GIR_EraseFromParent, /*InsnID*/0, 14052 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14053 // GIR_Coverage, 3599, 14054 GIR_Done, 14055 // Label 968: @32816 14056 GIM_Reject, 14057 // Label 953: @32817 14058 GIM_Reject, 14059 // Label 951: @32818 14060 GIM_Try, /*On fail goto*//*Label 969*/ 33064, 14061 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 14062 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 14063 GIM_Try, /*On fail goto*//*Label 970*/ 32875, // Rule ID 3580 // 14064 GIM_CheckFeatures, GIFBS_HasLSE, 14065 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 14066 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 14067 // MIs[0] Rn 14068 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14070 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 14071 // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_monotonic>> => (LDEORX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14072 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORX, 14073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14075 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14076 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14077 GIR_EraseFromParent, /*InsnID*/0, 14078 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14079 // GIR_Coverage, 3580, 14080 GIR_Done, 14081 // Label 970: @32875 14082 GIM_Try, /*On fail goto*//*Label 971*/ 32922, // Rule ID 3581 // 14083 GIM_CheckFeatures, GIFBS_HasLSE, 14084 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 14085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 14086 // MIs[0] Rn 14087 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 14090 // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acquire>> => (LDEORAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14091 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAX, 14092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14095 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14096 GIR_EraseFromParent, /*InsnID*/0, 14097 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14098 // GIR_Coverage, 3581, 14099 GIR_Done, 14100 // Label 971: @32922 14101 GIM_Try, /*On fail goto*//*Label 972*/ 32969, // Rule ID 3582 // 14102 GIM_CheckFeatures, GIFBS_HasLSE, 14103 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 14104 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 14105 // MIs[0] Rn 14106 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 14109 // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_release>> => (LDEORLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14110 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLX, 14111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14112 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14114 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14115 GIR_EraseFromParent, /*InsnID*/0, 14116 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14117 // GIR_Coverage, 3582, 14118 GIR_Done, 14119 // Label 972: @32969 14120 GIM_Try, /*On fail goto*//*Label 973*/ 33016, // Rule ID 3583 // 14121 GIM_CheckFeatures, GIFBS_HasLSE, 14122 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 14123 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 14124 // MIs[0] Rn 14125 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 14128 // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acq_rel>> => (LDEORALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14129 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALX, 14130 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14131 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14133 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14134 GIR_EraseFromParent, /*InsnID*/0, 14135 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14136 // GIR_Coverage, 3583, 14137 GIR_Done, 14138 // Label 973: @33016 14139 GIM_Try, /*On fail goto*//*Label 974*/ 33063, // Rule ID 3584 // 14140 GIM_CheckFeatures, GIFBS_HasLSE, 14141 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 14142 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 14143 // MIs[0] Rn 14144 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14146 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 14147 // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_seq_cst>> => (LDEORALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14148 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALX, 14149 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14150 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14151 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14152 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14153 GIR_EraseFromParent, /*InsnID*/0, 14154 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14155 // GIR_Coverage, 3584, 14156 GIR_Done, 14157 // Label 974: @33063 14158 GIM_Reject, 14159 // Label 969: @33064 14160 GIM_Reject, 14161 // Label 952: @33065 14162 GIM_Reject, 14163 // Label 20: @33066 14164 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 977*/ 34094, 14165 /*GILLT_s32*//*Label 975*/ 33074, 14166 /*GILLT_s64*//*Label 976*/ 33847, 14167 // Label 975: @33074 14168 GIM_Try, /*On fail goto*//*Label 978*/ 33846, 14169 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 14170 GIM_Try, /*On fail goto*//*Label 979*/ 33131, // Rule ID 3625 // 14171 GIM_CheckFeatures, GIFBS_HasLSE, 14172 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 14173 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 14174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14175 // MIs[0] Rn 14176 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14179 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_monotonic>> => (LDSMAXW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14180 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXW, 14181 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14182 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14183 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14184 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14185 GIR_EraseFromParent, /*InsnID*/0, 14186 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14187 // GIR_Coverage, 3625, 14188 GIR_Done, 14189 // Label 979: @33131 14190 GIM_Try, /*On fail goto*//*Label 980*/ 33182, // Rule ID 3626 // 14191 GIM_CheckFeatures, GIFBS_HasLSE, 14192 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 14193 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 14194 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14195 // MIs[0] Rn 14196 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14199 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acquire>> => (LDSMAXAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14200 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAW, 14201 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14202 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14203 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14204 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14205 GIR_EraseFromParent, /*InsnID*/0, 14206 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14207 // GIR_Coverage, 3626, 14208 GIR_Done, 14209 // Label 980: @33182 14210 GIM_Try, /*On fail goto*//*Label 981*/ 33233, // Rule ID 3627 // 14211 GIM_CheckFeatures, GIFBS_HasLSE, 14212 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 14213 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 14214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14215 // MIs[0] Rn 14216 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14219 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_release>> => (LDSMAXLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14220 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLW, 14221 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14222 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14224 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14225 GIR_EraseFromParent, /*InsnID*/0, 14226 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14227 // GIR_Coverage, 3627, 14228 GIR_Done, 14229 // Label 981: @33233 14230 GIM_Try, /*On fail goto*//*Label 982*/ 33284, // Rule ID 3628 // 14231 GIM_CheckFeatures, GIFBS_HasLSE, 14232 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 14233 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 14234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14235 // MIs[0] Rn 14236 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14239 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acq_rel>> => (LDSMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14240 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALW, 14241 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14242 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14243 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14244 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14245 GIR_EraseFromParent, /*InsnID*/0, 14246 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14247 // GIR_Coverage, 3628, 14248 GIR_Done, 14249 // Label 982: @33284 14250 GIM_Try, /*On fail goto*//*Label 983*/ 33335, // Rule ID 3629 // 14251 GIM_CheckFeatures, GIFBS_HasLSE, 14252 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 14253 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 14254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14255 // MIs[0] Rn 14256 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14257 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14258 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14259 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_seq_cst>> => (LDSMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14260 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALW, 14261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14262 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14263 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14264 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14265 GIR_EraseFromParent, /*InsnID*/0, 14266 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14267 // GIR_Coverage, 3629, 14268 GIR_Done, 14269 // Label 983: @33335 14270 GIM_Try, /*On fail goto*//*Label 984*/ 33386, // Rule ID 3630 // 14271 GIM_CheckFeatures, GIFBS_HasLSE, 14272 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 14273 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 14274 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14275 // MIs[0] Rn 14276 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14279 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_16>><<P:Predicate_atomic_load_max_16_monotonic>> => (LDSMAXH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14280 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXH, 14281 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14282 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14283 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14284 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14285 GIR_EraseFromParent, /*InsnID*/0, 14286 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14287 // GIR_Coverage, 3630, 14288 GIR_Done, 14289 // Label 984: @33386 14290 GIM_Try, /*On fail goto*//*Label 985*/ 33437, // Rule ID 3631 // 14291 GIM_CheckFeatures, GIFBS_HasLSE, 14292 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 14293 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 14294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14295 // MIs[0] Rn 14296 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14297 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14298 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14299 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_16>><<P:Predicate_atomic_load_max_16_acquire>> => (LDSMAXAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14300 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAH, 14301 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14302 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14303 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14304 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14305 GIR_EraseFromParent, /*InsnID*/0, 14306 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14307 // GIR_Coverage, 3631, 14308 GIR_Done, 14309 // Label 985: @33437 14310 GIM_Try, /*On fail goto*//*Label 986*/ 33488, // Rule ID 3632 // 14311 GIM_CheckFeatures, GIFBS_HasLSE, 14312 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 14313 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 14314 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14315 // MIs[0] Rn 14316 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14319 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_16>><<P:Predicate_atomic_load_max_16_release>> => (LDSMAXLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14320 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLH, 14321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14322 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14323 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14324 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14325 GIR_EraseFromParent, /*InsnID*/0, 14326 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14327 // GIR_Coverage, 3632, 14328 GIR_Done, 14329 // Label 986: @33488 14330 GIM_Try, /*On fail goto*//*Label 987*/ 33539, // Rule ID 3633 // 14331 GIM_CheckFeatures, GIFBS_HasLSE, 14332 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 14333 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 14334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14335 // MIs[0] Rn 14336 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14339 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_16>><<P:Predicate_atomic_load_max_16_acq_rel>> => (LDSMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14340 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALH, 14341 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14342 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14343 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14344 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14345 GIR_EraseFromParent, /*InsnID*/0, 14346 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14347 // GIR_Coverage, 3633, 14348 GIR_Done, 14349 // Label 987: @33539 14350 GIM_Try, /*On fail goto*//*Label 988*/ 33590, // Rule ID 3634 // 14351 GIM_CheckFeatures, GIFBS_HasLSE, 14352 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 14353 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 14354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14355 // MIs[0] Rn 14356 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14359 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_16>><<P:Predicate_atomic_load_max_16_seq_cst>> => (LDSMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14360 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALH, 14361 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14362 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14364 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14365 GIR_EraseFromParent, /*InsnID*/0, 14366 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14367 // GIR_Coverage, 3634, 14368 GIR_Done, 14369 // Label 988: @33590 14370 GIM_Try, /*On fail goto*//*Label 989*/ 33641, // Rule ID 3635 // 14371 GIM_CheckFeatures, GIFBS_HasLSE, 14372 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 14373 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 14374 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14375 // MIs[0] Rn 14376 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14377 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14378 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14379 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_8>><<P:Predicate_atomic_load_max_8_monotonic>> => (LDSMAXB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14380 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXB, 14381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14384 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14385 GIR_EraseFromParent, /*InsnID*/0, 14386 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14387 // GIR_Coverage, 3635, 14388 GIR_Done, 14389 // Label 989: @33641 14390 GIM_Try, /*On fail goto*//*Label 990*/ 33692, // Rule ID 3636 // 14391 GIM_CheckFeatures, GIFBS_HasLSE, 14392 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 14393 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 14394 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14395 // MIs[0] Rn 14396 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14399 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_8>><<P:Predicate_atomic_load_max_8_acquire>> => (LDSMAXAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14400 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAB, 14401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14404 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14405 GIR_EraseFromParent, /*InsnID*/0, 14406 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14407 // GIR_Coverage, 3636, 14408 GIR_Done, 14409 // Label 990: @33692 14410 GIM_Try, /*On fail goto*//*Label 991*/ 33743, // Rule ID 3637 // 14411 GIM_CheckFeatures, GIFBS_HasLSE, 14412 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 14413 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 14414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14415 // MIs[0] Rn 14416 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14419 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_8>><<P:Predicate_atomic_load_max_8_release>> => (LDSMAXLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLB, 14421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14422 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14423 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14424 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14425 GIR_EraseFromParent, /*InsnID*/0, 14426 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14427 // GIR_Coverage, 3637, 14428 GIR_Done, 14429 // Label 991: @33743 14430 GIM_Try, /*On fail goto*//*Label 992*/ 33794, // Rule ID 3638 // 14431 GIM_CheckFeatures, GIFBS_HasLSE, 14432 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 14433 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 14434 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14435 // MIs[0] Rn 14436 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14439 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_8>><<P:Predicate_atomic_load_max_8_acq_rel>> => (LDSMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14440 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALB, 14441 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14442 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14443 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14444 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14445 GIR_EraseFromParent, /*InsnID*/0, 14446 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14447 // GIR_Coverage, 3638, 14448 GIR_Done, 14449 // Label 992: @33794 14450 GIM_Try, /*On fail goto*//*Label 993*/ 33845, // Rule ID 3639 // 14451 GIM_CheckFeatures, GIFBS_HasLSE, 14452 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 14453 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 14454 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14455 // MIs[0] Rn 14456 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14458 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14459 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_8>><<P:Predicate_atomic_load_max_8_seq_cst>> => (LDSMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14460 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALB, 14461 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14462 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14463 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14464 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14465 GIR_EraseFromParent, /*InsnID*/0, 14466 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14467 // GIR_Coverage, 3639, 14468 GIR_Done, 14469 // Label 993: @33845 14470 GIM_Reject, 14471 // Label 978: @33846 14472 GIM_Reject, 14473 // Label 976: @33847 14474 GIM_Try, /*On fail goto*//*Label 994*/ 34093, 14475 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 14476 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 14477 GIM_Try, /*On fail goto*//*Label 995*/ 33904, // Rule ID 3620 // 14478 GIM_CheckFeatures, GIFBS_HasLSE, 14479 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 14480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 14481 // MIs[0] Rn 14482 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14483 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14484 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 14485 // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_monotonic>> => (LDSMAXX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14486 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXX, 14487 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14488 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14489 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14490 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14491 GIR_EraseFromParent, /*InsnID*/0, 14492 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14493 // GIR_Coverage, 3620, 14494 GIR_Done, 14495 // Label 995: @33904 14496 GIM_Try, /*On fail goto*//*Label 996*/ 33951, // Rule ID 3621 // 14497 GIM_CheckFeatures, GIFBS_HasLSE, 14498 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 14499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 14500 // MIs[0] Rn 14501 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14502 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 14504 // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acquire>> => (LDSMAXAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14505 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAX, 14506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14507 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14508 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14509 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14510 GIR_EraseFromParent, /*InsnID*/0, 14511 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14512 // GIR_Coverage, 3621, 14513 GIR_Done, 14514 // Label 996: @33951 14515 GIM_Try, /*On fail goto*//*Label 997*/ 33998, // Rule ID 3622 // 14516 GIM_CheckFeatures, GIFBS_HasLSE, 14517 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 14518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 14519 // MIs[0] Rn 14520 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 14523 // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_release>> => (LDSMAXLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLX, 14525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14528 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14529 GIR_EraseFromParent, /*InsnID*/0, 14530 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14531 // GIR_Coverage, 3622, 14532 GIR_Done, 14533 // Label 997: @33998 14534 GIM_Try, /*On fail goto*//*Label 998*/ 34045, // Rule ID 3623 // 14535 GIM_CheckFeatures, GIFBS_HasLSE, 14536 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 14537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 14538 // MIs[0] Rn 14539 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14540 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 14542 // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acq_rel>> => (LDSMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14543 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALX, 14544 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14545 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14546 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14547 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14548 GIR_EraseFromParent, /*InsnID*/0, 14549 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14550 // GIR_Coverage, 3623, 14551 GIR_Done, 14552 // Label 998: @34045 14553 GIM_Try, /*On fail goto*//*Label 999*/ 34092, // Rule ID 3624 // 14554 GIM_CheckFeatures, GIFBS_HasLSE, 14555 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 14556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 14557 // MIs[0] Rn 14558 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 14561 // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_seq_cst>> => (LDSMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14562 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALX, 14563 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14564 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14565 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14566 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14567 GIR_EraseFromParent, /*InsnID*/0, 14568 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14569 // GIR_Coverage, 3624, 14570 GIR_Done, 14571 // Label 999: @34092 14572 GIM_Reject, 14573 // Label 994: @34093 14574 GIM_Reject, 14575 // Label 977: @34094 14576 GIM_Reject, 14577 // Label 21: @34095 14578 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1002*/ 35123, 14579 /*GILLT_s32*//*Label 1000*/ 34103, 14580 /*GILLT_s64*//*Label 1001*/ 34876, 14581 // Label 1000: @34103 14582 GIM_Try, /*On fail goto*//*Label 1003*/ 34875, 14583 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 14584 GIM_Try, /*On fail goto*//*Label 1004*/ 34160, // Rule ID 3645 // 14585 GIM_CheckFeatures, GIFBS_HasLSE, 14586 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 14587 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 14588 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14589 // MIs[0] Rn 14590 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14591 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14592 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14593 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_monotonic>> => (LDSMINW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14594 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINW, 14595 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14596 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14597 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14598 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14599 GIR_EraseFromParent, /*InsnID*/0, 14600 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14601 // GIR_Coverage, 3645, 14602 GIR_Done, 14603 // Label 1004: @34160 14604 GIM_Try, /*On fail goto*//*Label 1005*/ 34211, // Rule ID 3646 // 14605 GIM_CheckFeatures, GIFBS_HasLSE, 14606 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 14607 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 14608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14609 // MIs[0] Rn 14610 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14611 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14613 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acquire>> => (LDSMINAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14614 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAW, 14615 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14616 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14617 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14618 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14619 GIR_EraseFromParent, /*InsnID*/0, 14620 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14621 // GIR_Coverage, 3646, 14622 GIR_Done, 14623 // Label 1005: @34211 14624 GIM_Try, /*On fail goto*//*Label 1006*/ 34262, // Rule ID 3647 // 14625 GIM_CheckFeatures, GIFBS_HasLSE, 14626 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 14627 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 14628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14629 // MIs[0] Rn 14630 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14632 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14633 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_release>> => (LDSMINLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLW, 14635 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14636 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14637 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14638 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14639 GIR_EraseFromParent, /*InsnID*/0, 14640 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14641 // GIR_Coverage, 3647, 14642 GIR_Done, 14643 // Label 1006: @34262 14644 GIM_Try, /*On fail goto*//*Label 1007*/ 34313, // Rule ID 3648 // 14645 GIM_CheckFeatures, GIFBS_HasLSE, 14646 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 14647 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 14648 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14649 // MIs[0] Rn 14650 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14653 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acq_rel>> => (LDSMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14654 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALW, 14655 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14656 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14658 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14659 GIR_EraseFromParent, /*InsnID*/0, 14660 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14661 // GIR_Coverage, 3648, 14662 GIR_Done, 14663 // Label 1007: @34313 14664 GIM_Try, /*On fail goto*//*Label 1008*/ 34364, // Rule ID 3649 // 14665 GIM_CheckFeatures, GIFBS_HasLSE, 14666 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 14667 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 14668 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14669 // MIs[0] Rn 14670 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14673 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_seq_cst>> => (LDSMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14674 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALW, 14675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14678 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14679 GIR_EraseFromParent, /*InsnID*/0, 14680 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14681 // GIR_Coverage, 3649, 14682 GIR_Done, 14683 // Label 1008: @34364 14684 GIM_Try, /*On fail goto*//*Label 1009*/ 34415, // Rule ID 3650 // 14685 GIM_CheckFeatures, GIFBS_HasLSE, 14686 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 14687 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 14688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14689 // MIs[0] Rn 14690 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14691 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14692 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14693 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_16>><<P:Predicate_atomic_load_min_16_monotonic>> => (LDSMINH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14694 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINH, 14695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14696 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14697 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14698 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14699 GIR_EraseFromParent, /*InsnID*/0, 14700 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14701 // GIR_Coverage, 3650, 14702 GIR_Done, 14703 // Label 1009: @34415 14704 GIM_Try, /*On fail goto*//*Label 1010*/ 34466, // Rule ID 3651 // 14705 GIM_CheckFeatures, GIFBS_HasLSE, 14706 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 14707 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 14708 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14709 // MIs[0] Rn 14710 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14711 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14712 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14713 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_16>><<P:Predicate_atomic_load_min_16_acquire>> => (LDSMINAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14714 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAH, 14715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14717 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14718 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14719 GIR_EraseFromParent, /*InsnID*/0, 14720 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14721 // GIR_Coverage, 3651, 14722 GIR_Done, 14723 // Label 1010: @34466 14724 GIM_Try, /*On fail goto*//*Label 1011*/ 34517, // Rule ID 3652 // 14725 GIM_CheckFeatures, GIFBS_HasLSE, 14726 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 14727 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 14728 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14729 // MIs[0] Rn 14730 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14731 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14732 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14733 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_16>><<P:Predicate_atomic_load_min_16_release>> => (LDSMINLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14734 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLH, 14735 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14736 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14737 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14738 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14739 GIR_EraseFromParent, /*InsnID*/0, 14740 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14741 // GIR_Coverage, 3652, 14742 GIR_Done, 14743 // Label 1011: @34517 14744 GIM_Try, /*On fail goto*//*Label 1012*/ 34568, // Rule ID 3653 // 14745 GIM_CheckFeatures, GIFBS_HasLSE, 14746 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 14747 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 14748 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14749 // MIs[0] Rn 14750 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14751 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14753 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_16>><<P:Predicate_atomic_load_min_16_acq_rel>> => (LDSMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14754 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALH, 14755 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14756 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14757 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14758 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14759 GIR_EraseFromParent, /*InsnID*/0, 14760 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14761 // GIR_Coverage, 3653, 14762 GIR_Done, 14763 // Label 1012: @34568 14764 GIM_Try, /*On fail goto*//*Label 1013*/ 34619, // Rule ID 3654 // 14765 GIM_CheckFeatures, GIFBS_HasLSE, 14766 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 14767 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 14768 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14769 // MIs[0] Rn 14770 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14772 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14773 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_16>><<P:Predicate_atomic_load_min_16_seq_cst>> => (LDSMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14774 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALH, 14775 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14776 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14778 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14779 GIR_EraseFromParent, /*InsnID*/0, 14780 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14781 // GIR_Coverage, 3654, 14782 GIR_Done, 14783 // Label 1013: @34619 14784 GIM_Try, /*On fail goto*//*Label 1014*/ 34670, // Rule ID 3655 // 14785 GIM_CheckFeatures, GIFBS_HasLSE, 14786 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 14787 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 14788 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14789 // MIs[0] Rn 14790 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14791 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14792 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14793 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_8>><<P:Predicate_atomic_load_min_8_monotonic>> => (LDSMINB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14794 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINB, 14795 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14796 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14797 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14798 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14799 GIR_EraseFromParent, /*InsnID*/0, 14800 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14801 // GIR_Coverage, 3655, 14802 GIR_Done, 14803 // Label 1014: @34670 14804 GIM_Try, /*On fail goto*//*Label 1015*/ 34721, // Rule ID 3656 // 14805 GIM_CheckFeatures, GIFBS_HasLSE, 14806 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 14807 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 14808 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14809 // MIs[0] Rn 14810 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14811 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14813 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_8>><<P:Predicate_atomic_load_min_8_acquire>> => (LDSMINAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14814 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAB, 14815 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14816 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14817 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14818 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14819 GIR_EraseFromParent, /*InsnID*/0, 14820 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14821 // GIR_Coverage, 3656, 14822 GIR_Done, 14823 // Label 1015: @34721 14824 GIM_Try, /*On fail goto*//*Label 1016*/ 34772, // Rule ID 3657 // 14825 GIM_CheckFeatures, GIFBS_HasLSE, 14826 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 14827 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 14828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14829 // MIs[0] Rn 14830 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14832 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14833 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_8>><<P:Predicate_atomic_load_min_8_release>> => (LDSMINLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14834 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLB, 14835 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14836 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14837 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14838 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14839 GIR_EraseFromParent, /*InsnID*/0, 14840 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14841 // GIR_Coverage, 3657, 14842 GIR_Done, 14843 // Label 1016: @34772 14844 GIM_Try, /*On fail goto*//*Label 1017*/ 34823, // Rule ID 3658 // 14845 GIM_CheckFeatures, GIFBS_HasLSE, 14846 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 14847 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 14848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14849 // MIs[0] Rn 14850 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14853 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_8>><<P:Predicate_atomic_load_min_8_acq_rel>> => (LDSMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14854 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALB, 14855 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14857 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14858 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14859 GIR_EraseFromParent, /*InsnID*/0, 14860 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14861 // GIR_Coverage, 3658, 14862 GIR_Done, 14863 // Label 1017: @34823 14864 GIM_Try, /*On fail goto*//*Label 1018*/ 34874, // Rule ID 3659 // 14865 GIM_CheckFeatures, GIFBS_HasLSE, 14866 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 14867 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 14868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 14869 // MIs[0] Rn 14870 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 14873 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_8>><<P:Predicate_atomic_load_min_8_seq_cst>> => (LDSMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14874 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALB, 14875 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14876 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14878 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14879 GIR_EraseFromParent, /*InsnID*/0, 14880 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14881 // GIR_Coverage, 3659, 14882 GIR_Done, 14883 // Label 1018: @34874 14884 GIM_Reject, 14885 // Label 1003: @34875 14886 GIM_Reject, 14887 // Label 1001: @34876 14888 GIM_Try, /*On fail goto*//*Label 1019*/ 35122, 14889 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 14890 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 14891 GIM_Try, /*On fail goto*//*Label 1020*/ 34933, // Rule ID 3640 // 14892 GIM_CheckFeatures, GIFBS_HasLSE, 14893 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 14894 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 14895 // MIs[0] Rn 14896 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14897 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 14899 // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_monotonic>> => (LDSMINX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14900 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINX, 14901 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14902 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14904 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14905 GIR_EraseFromParent, /*InsnID*/0, 14906 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14907 // GIR_Coverage, 3640, 14908 GIR_Done, 14909 // Label 1020: @34933 14910 GIM_Try, /*On fail goto*//*Label 1021*/ 34980, // Rule ID 3641 // 14911 GIM_CheckFeatures, GIFBS_HasLSE, 14912 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 14913 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 14914 // MIs[0] Rn 14915 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 14918 // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acquire>> => (LDSMINAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAX, 14920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14922 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14923 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14924 GIR_EraseFromParent, /*InsnID*/0, 14925 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14926 // GIR_Coverage, 3641, 14927 GIR_Done, 14928 // Label 1021: @34980 14929 GIM_Try, /*On fail goto*//*Label 1022*/ 35027, // Rule ID 3642 // 14930 GIM_CheckFeatures, GIFBS_HasLSE, 14931 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 14932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 14933 // MIs[0] Rn 14934 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14936 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 14937 // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_release>> => (LDSMINLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14938 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLX, 14939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14940 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14941 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14942 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14943 GIR_EraseFromParent, /*InsnID*/0, 14944 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14945 // GIR_Coverage, 3642, 14946 GIR_Done, 14947 // Label 1022: @35027 14948 GIM_Try, /*On fail goto*//*Label 1023*/ 35074, // Rule ID 3643 // 14949 GIM_CheckFeatures, GIFBS_HasLSE, 14950 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 14951 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 14952 // MIs[0] Rn 14953 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 14956 // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acq_rel>> => (LDSMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14957 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALX, 14958 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14959 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14960 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14961 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14962 GIR_EraseFromParent, /*InsnID*/0, 14963 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14964 // GIR_Coverage, 3643, 14965 GIR_Done, 14966 // Label 1023: @35074 14967 GIM_Try, /*On fail goto*//*Label 1024*/ 35121, // Rule ID 3644 // 14968 GIM_CheckFeatures, GIFBS_HasLSE, 14969 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 14970 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 14971 // MIs[0] Rn 14972 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 14973 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 14974 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 14975 // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_seq_cst>> => (LDSMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 14976 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALX, 14977 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 14978 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 14979 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 14980 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 14981 GIR_EraseFromParent, /*InsnID*/0, 14982 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14983 // GIR_Coverage, 3644, 14984 GIR_Done, 14985 // Label 1024: @35121 14986 GIM_Reject, 14987 // Label 1019: @35122 14988 GIM_Reject, 14989 // Label 1002: @35123 14990 GIM_Reject, 14991 // Label 22: @35124 14992 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1027*/ 36152, 14993 /*GILLT_s32*//*Label 1025*/ 35132, 14994 /*GILLT_s64*//*Label 1026*/ 35905, 14995 // Label 1025: @35132 14996 GIM_Try, /*On fail goto*//*Label 1028*/ 35904, 14997 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 14998 GIM_Try, /*On fail goto*//*Label 1029*/ 35189, // Rule ID 3665 // 14999 GIM_CheckFeatures, GIFBS_HasLSE, 15000 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 15001 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 15002 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15003 // MIs[0] Rn 15004 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15006 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15007 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_monotonic>> => (LDUMAXW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15008 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXW, 15009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15011 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15012 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15013 GIR_EraseFromParent, /*InsnID*/0, 15014 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15015 // GIR_Coverage, 3665, 15016 GIR_Done, 15017 // Label 1029: @35189 15018 GIM_Try, /*On fail goto*//*Label 1030*/ 35240, // Rule ID 3666 // 15019 GIM_CheckFeatures, GIFBS_HasLSE, 15020 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 15021 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 15022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15023 // MIs[0] Rn 15024 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15027 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acquire>> => (LDUMAXAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15028 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAW, 15029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15032 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15033 GIR_EraseFromParent, /*InsnID*/0, 15034 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15035 // GIR_Coverage, 3666, 15036 GIR_Done, 15037 // Label 1030: @35240 15038 GIM_Try, /*On fail goto*//*Label 1031*/ 35291, // Rule ID 3667 // 15039 GIM_CheckFeatures, GIFBS_HasLSE, 15040 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 15041 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 15042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15043 // MIs[0] Rn 15044 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15047 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_release>> => (LDUMAXLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15048 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLW, 15049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15051 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15052 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15053 GIR_EraseFromParent, /*InsnID*/0, 15054 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15055 // GIR_Coverage, 3667, 15056 GIR_Done, 15057 // Label 1031: @35291 15058 GIM_Try, /*On fail goto*//*Label 1032*/ 35342, // Rule ID 3668 // 15059 GIM_CheckFeatures, GIFBS_HasLSE, 15060 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 15061 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 15062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15063 // MIs[0] Rn 15064 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15065 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15066 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15067 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acq_rel>> => (LDUMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15068 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALW, 15069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15070 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15071 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15072 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15073 GIR_EraseFromParent, /*InsnID*/0, 15074 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15075 // GIR_Coverage, 3668, 15076 GIR_Done, 15077 // Label 1032: @35342 15078 GIM_Try, /*On fail goto*//*Label 1033*/ 35393, // Rule ID 3669 // 15079 GIM_CheckFeatures, GIFBS_HasLSE, 15080 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 15081 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 15082 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15083 // MIs[0] Rn 15084 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15087 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_seq_cst>> => (LDUMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15088 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALW, 15089 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15090 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15091 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15092 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15093 GIR_EraseFromParent, /*InsnID*/0, 15094 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15095 // GIR_Coverage, 3669, 15096 GIR_Done, 15097 // Label 1033: @35393 15098 GIM_Try, /*On fail goto*//*Label 1034*/ 35444, // Rule ID 3670 // 15099 GIM_CheckFeatures, GIFBS_HasLSE, 15100 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 15101 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 15102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15103 // MIs[0] Rn 15104 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15107 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_16>><<P:Predicate_atomic_load_umax_16_monotonic>> => (LDUMAXH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15108 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXH, 15109 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15110 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15112 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15113 GIR_EraseFromParent, /*InsnID*/0, 15114 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15115 // GIR_Coverage, 3670, 15116 GIR_Done, 15117 // Label 1034: @35444 15118 GIM_Try, /*On fail goto*//*Label 1035*/ 35495, // Rule ID 3671 // 15119 GIM_CheckFeatures, GIFBS_HasLSE, 15120 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 15121 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 15122 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15123 // MIs[0] Rn 15124 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15127 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_16>><<P:Predicate_atomic_load_umax_16_acquire>> => (LDUMAXAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15128 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAH, 15129 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15130 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15131 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15132 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15133 GIR_EraseFromParent, /*InsnID*/0, 15134 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15135 // GIR_Coverage, 3671, 15136 GIR_Done, 15137 // Label 1035: @35495 15138 GIM_Try, /*On fail goto*//*Label 1036*/ 35546, // Rule ID 3672 // 15139 GIM_CheckFeatures, GIFBS_HasLSE, 15140 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 15141 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 15142 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15143 // MIs[0] Rn 15144 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15146 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15147 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_16>><<P:Predicate_atomic_load_umax_16_release>> => (LDUMAXLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15148 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLH, 15149 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15150 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15151 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15152 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15153 GIR_EraseFromParent, /*InsnID*/0, 15154 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15155 // GIR_Coverage, 3672, 15156 GIR_Done, 15157 // Label 1036: @35546 15158 GIM_Try, /*On fail goto*//*Label 1037*/ 35597, // Rule ID 3673 // 15159 GIM_CheckFeatures, GIFBS_HasLSE, 15160 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 15161 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 15162 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15163 // MIs[0] Rn 15164 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15167 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_16>><<P:Predicate_atomic_load_umax_16_acq_rel>> => (LDUMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15168 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALH, 15169 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15170 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15171 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15172 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15173 GIR_EraseFromParent, /*InsnID*/0, 15174 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15175 // GIR_Coverage, 3673, 15176 GIR_Done, 15177 // Label 1037: @35597 15178 GIM_Try, /*On fail goto*//*Label 1038*/ 35648, // Rule ID 3674 // 15179 GIM_CheckFeatures, GIFBS_HasLSE, 15180 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 15181 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 15182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15183 // MIs[0] Rn 15184 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15185 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15186 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15187 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_16>><<P:Predicate_atomic_load_umax_16_seq_cst>> => (LDUMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15188 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALH, 15189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15190 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15191 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15192 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15193 GIR_EraseFromParent, /*InsnID*/0, 15194 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15195 // GIR_Coverage, 3674, 15196 GIR_Done, 15197 // Label 1038: @35648 15198 GIM_Try, /*On fail goto*//*Label 1039*/ 35699, // Rule ID 3675 // 15199 GIM_CheckFeatures, GIFBS_HasLSE, 15200 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 15201 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 15202 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15203 // MIs[0] Rn 15204 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15205 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15207 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_8>><<P:Predicate_atomic_load_umax_8_monotonic>> => (LDUMAXB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXB, 15209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15211 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15212 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15213 GIR_EraseFromParent, /*InsnID*/0, 15214 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15215 // GIR_Coverage, 3675, 15216 GIR_Done, 15217 // Label 1039: @35699 15218 GIM_Try, /*On fail goto*//*Label 1040*/ 35750, // Rule ID 3676 // 15219 GIM_CheckFeatures, GIFBS_HasLSE, 15220 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 15221 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 15222 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15223 // MIs[0] Rn 15224 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15227 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_8>><<P:Predicate_atomic_load_umax_8_acquire>> => (LDUMAXAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15228 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAB, 15229 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15230 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15231 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15232 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15233 GIR_EraseFromParent, /*InsnID*/0, 15234 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15235 // GIR_Coverage, 3676, 15236 GIR_Done, 15237 // Label 1040: @35750 15238 GIM_Try, /*On fail goto*//*Label 1041*/ 35801, // Rule ID 3677 // 15239 GIM_CheckFeatures, GIFBS_HasLSE, 15240 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 15241 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 15242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15243 // MIs[0] Rn 15244 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15247 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_8>><<P:Predicate_atomic_load_umax_8_release>> => (LDUMAXLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15248 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLB, 15249 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15251 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15252 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15253 GIR_EraseFromParent, /*InsnID*/0, 15254 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15255 // GIR_Coverage, 3677, 15256 GIR_Done, 15257 // Label 1041: @35801 15258 GIM_Try, /*On fail goto*//*Label 1042*/ 35852, // Rule ID 3678 // 15259 GIM_CheckFeatures, GIFBS_HasLSE, 15260 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 15261 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 15262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15263 // MIs[0] Rn 15264 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15266 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15267 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_8>><<P:Predicate_atomic_load_umax_8_acq_rel>> => (LDUMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15268 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALB, 15269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15271 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15272 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15273 GIR_EraseFromParent, /*InsnID*/0, 15274 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15275 // GIR_Coverage, 3678, 15276 GIR_Done, 15277 // Label 1042: @35852 15278 GIM_Try, /*On fail goto*//*Label 1043*/ 35903, // Rule ID 3679 // 15279 GIM_CheckFeatures, GIFBS_HasLSE, 15280 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 15281 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 15282 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15283 // MIs[0] Rn 15284 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15287 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_8>><<P:Predicate_atomic_load_umax_8_seq_cst>> => (LDUMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALB, 15289 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15290 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15292 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15293 GIR_EraseFromParent, /*InsnID*/0, 15294 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15295 // GIR_Coverage, 3679, 15296 GIR_Done, 15297 // Label 1043: @35903 15298 GIM_Reject, 15299 // Label 1028: @35904 15300 GIM_Reject, 15301 // Label 1026: @35905 15302 GIM_Try, /*On fail goto*//*Label 1044*/ 36151, 15303 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 15304 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 15305 GIM_Try, /*On fail goto*//*Label 1045*/ 35962, // Rule ID 3660 // 15306 GIM_CheckFeatures, GIFBS_HasLSE, 15307 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 15308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 15309 // MIs[0] Rn 15310 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15311 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 15313 // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_monotonic>> => (LDUMAXX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15314 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXX, 15315 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15316 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15317 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15318 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15319 GIR_EraseFromParent, /*InsnID*/0, 15320 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15321 // GIR_Coverage, 3660, 15322 GIR_Done, 15323 // Label 1045: @35962 15324 GIM_Try, /*On fail goto*//*Label 1046*/ 36009, // Rule ID 3661 // 15325 GIM_CheckFeatures, GIFBS_HasLSE, 15326 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 15327 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 15328 // MIs[0] Rn 15329 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 15332 // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acquire>> => (LDUMAXAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15333 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAX, 15334 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15335 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15336 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15337 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15338 GIR_EraseFromParent, /*InsnID*/0, 15339 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15340 // GIR_Coverage, 3661, 15341 GIR_Done, 15342 // Label 1046: @36009 15343 GIM_Try, /*On fail goto*//*Label 1047*/ 36056, // Rule ID 3662 // 15344 GIM_CheckFeatures, GIFBS_HasLSE, 15345 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 15346 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 15347 // MIs[0] Rn 15348 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 15351 // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_release>> => (LDUMAXLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15352 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLX, 15353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15356 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15357 GIR_EraseFromParent, /*InsnID*/0, 15358 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15359 // GIR_Coverage, 3662, 15360 GIR_Done, 15361 // Label 1047: @36056 15362 GIM_Try, /*On fail goto*//*Label 1048*/ 36103, // Rule ID 3663 // 15363 GIM_CheckFeatures, GIFBS_HasLSE, 15364 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 15365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 15366 // MIs[0] Rn 15367 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 15370 // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acq_rel>> => (LDUMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15371 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALX, 15372 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15373 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15374 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15375 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15376 GIR_EraseFromParent, /*InsnID*/0, 15377 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15378 // GIR_Coverage, 3663, 15379 GIR_Done, 15380 // Label 1048: @36103 15381 GIM_Try, /*On fail goto*//*Label 1049*/ 36150, // Rule ID 3664 // 15382 GIM_CheckFeatures, GIFBS_HasLSE, 15383 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 15384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 15385 // MIs[0] Rn 15386 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15387 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15388 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 15389 // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_seq_cst>> => (LDUMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15390 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALX, 15391 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15392 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15393 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15394 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15395 GIR_EraseFromParent, /*InsnID*/0, 15396 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15397 // GIR_Coverage, 3664, 15398 GIR_Done, 15399 // Label 1049: @36150 15400 GIM_Reject, 15401 // Label 1044: @36151 15402 GIM_Reject, 15403 // Label 1027: @36152 15404 GIM_Reject, 15405 // Label 23: @36153 15406 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1052*/ 37181, 15407 /*GILLT_s32*//*Label 1050*/ 36161, 15408 /*GILLT_s64*//*Label 1051*/ 36934, 15409 // Label 1050: @36161 15410 GIM_Try, /*On fail goto*//*Label 1053*/ 36933, 15411 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 15412 GIM_Try, /*On fail goto*//*Label 1054*/ 36218, // Rule ID 3685 // 15413 GIM_CheckFeatures, GIFBS_HasLSE, 15414 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 15415 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 15416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15417 // MIs[0] Rn 15418 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15420 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15421 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_monotonic>> => (LDUMINW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15422 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINW, 15423 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15424 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15425 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15426 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15427 GIR_EraseFromParent, /*InsnID*/0, 15428 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15429 // GIR_Coverage, 3685, 15430 GIR_Done, 15431 // Label 1054: @36218 15432 GIM_Try, /*On fail goto*//*Label 1055*/ 36269, // Rule ID 3686 // 15433 GIM_CheckFeatures, GIFBS_HasLSE, 15434 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 15435 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 15436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15437 // MIs[0] Rn 15438 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15439 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15440 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15441 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acquire>> => (LDUMINAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15442 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAW, 15443 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15444 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15445 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15446 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15447 GIR_EraseFromParent, /*InsnID*/0, 15448 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15449 // GIR_Coverage, 3686, 15450 GIR_Done, 15451 // Label 1055: @36269 15452 GIM_Try, /*On fail goto*//*Label 1056*/ 36320, // Rule ID 3687 // 15453 GIM_CheckFeatures, GIFBS_HasLSE, 15454 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 15455 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 15456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15457 // MIs[0] Rn 15458 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15459 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15460 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15461 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_release>> => (LDUMINLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15462 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLW, 15463 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15464 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15465 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15466 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15467 GIR_EraseFromParent, /*InsnID*/0, 15468 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15469 // GIR_Coverage, 3687, 15470 GIR_Done, 15471 // Label 1056: @36320 15472 GIM_Try, /*On fail goto*//*Label 1057*/ 36371, // Rule ID 3688 // 15473 GIM_CheckFeatures, GIFBS_HasLSE, 15474 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 15475 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 15476 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15477 // MIs[0] Rn 15478 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15481 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acq_rel>> => (LDUMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15482 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALW, 15483 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15486 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15487 GIR_EraseFromParent, /*InsnID*/0, 15488 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15489 // GIR_Coverage, 3688, 15490 GIR_Done, 15491 // Label 1057: @36371 15492 GIM_Try, /*On fail goto*//*Label 1058*/ 36422, // Rule ID 3689 // 15493 GIM_CheckFeatures, GIFBS_HasLSE, 15494 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 15495 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 15496 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15497 // MIs[0] Rn 15498 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15501 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_seq_cst>> => (LDUMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15502 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALW, 15503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15506 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15507 GIR_EraseFromParent, /*InsnID*/0, 15508 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15509 // GIR_Coverage, 3689, 15510 GIR_Done, 15511 // Label 1058: @36422 15512 GIM_Try, /*On fail goto*//*Label 1059*/ 36473, // Rule ID 3690 // 15513 GIM_CheckFeatures, GIFBS_HasLSE, 15514 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 15515 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 15516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15517 // MIs[0] Rn 15518 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15521 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_16>><<P:Predicate_atomic_load_umin_16_monotonic>> => (LDUMINH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15522 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINH, 15523 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15524 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15526 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15527 GIR_EraseFromParent, /*InsnID*/0, 15528 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15529 // GIR_Coverage, 3690, 15530 GIR_Done, 15531 // Label 1059: @36473 15532 GIM_Try, /*On fail goto*//*Label 1060*/ 36524, // Rule ID 3691 // 15533 GIM_CheckFeatures, GIFBS_HasLSE, 15534 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 15535 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 15536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15537 // MIs[0] Rn 15538 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15539 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15540 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15541 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_16>><<P:Predicate_atomic_load_umin_16_acquire>> => (LDUMINAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15542 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAH, 15543 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15544 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15545 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15546 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15547 GIR_EraseFromParent, /*InsnID*/0, 15548 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15549 // GIR_Coverage, 3691, 15550 GIR_Done, 15551 // Label 1060: @36524 15552 GIM_Try, /*On fail goto*//*Label 1061*/ 36575, // Rule ID 3692 // 15553 GIM_CheckFeatures, GIFBS_HasLSE, 15554 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 15555 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 15556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15557 // MIs[0] Rn 15558 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15561 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_16>><<P:Predicate_atomic_load_umin_16_release>> => (LDUMINLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15562 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLH, 15563 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15564 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15565 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15566 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15567 GIR_EraseFromParent, /*InsnID*/0, 15568 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15569 // GIR_Coverage, 3692, 15570 GIR_Done, 15571 // Label 1061: @36575 15572 GIM_Try, /*On fail goto*//*Label 1062*/ 36626, // Rule ID 3693 // 15573 GIM_CheckFeatures, GIFBS_HasLSE, 15574 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 15575 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 15576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15577 // MIs[0] Rn 15578 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15581 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_16>><<P:Predicate_atomic_load_umin_16_acq_rel>> => (LDUMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15582 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALH, 15583 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15584 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15585 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15586 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15587 GIR_EraseFromParent, /*InsnID*/0, 15588 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15589 // GIR_Coverage, 3693, 15590 GIR_Done, 15591 // Label 1062: @36626 15592 GIM_Try, /*On fail goto*//*Label 1063*/ 36677, // Rule ID 3694 // 15593 GIM_CheckFeatures, GIFBS_HasLSE, 15594 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 15595 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 15596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15597 // MIs[0] Rn 15598 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15599 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15600 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15601 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_16>><<P:Predicate_atomic_load_umin_16_seq_cst>> => (LDUMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALH, 15603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15606 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15607 GIR_EraseFromParent, /*InsnID*/0, 15608 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15609 // GIR_Coverage, 3694, 15610 GIR_Done, 15611 // Label 1063: @36677 15612 GIM_Try, /*On fail goto*//*Label 1064*/ 36728, // Rule ID 3695 // 15613 GIM_CheckFeatures, GIFBS_HasLSE, 15614 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 15615 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 15616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15617 // MIs[0] Rn 15618 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15621 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_8>><<P:Predicate_atomic_load_umin_8_monotonic>> => (LDUMINB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15622 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINB, 15623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15626 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15627 GIR_EraseFromParent, /*InsnID*/0, 15628 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15629 // GIR_Coverage, 3695, 15630 GIR_Done, 15631 // Label 1064: @36728 15632 GIM_Try, /*On fail goto*//*Label 1065*/ 36779, // Rule ID 3696 // 15633 GIM_CheckFeatures, GIFBS_HasLSE, 15634 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 15635 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 15636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15637 // MIs[0] Rn 15638 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15640 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15641 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_8>><<P:Predicate_atomic_load_umin_8_acquire>> => (LDUMINAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15642 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAB, 15643 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15646 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15647 GIR_EraseFromParent, /*InsnID*/0, 15648 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15649 // GIR_Coverage, 3696, 15650 GIR_Done, 15651 // Label 1065: @36779 15652 GIM_Try, /*On fail goto*//*Label 1066*/ 36830, // Rule ID 3697 // 15653 GIM_CheckFeatures, GIFBS_HasLSE, 15654 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 15655 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 15656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15657 // MIs[0] Rn 15658 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15660 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15661 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_8>><<P:Predicate_atomic_load_umin_8_release>> => (LDUMINLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15662 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLB, 15663 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15664 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15665 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15666 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15667 GIR_EraseFromParent, /*InsnID*/0, 15668 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15669 // GIR_Coverage, 3697, 15670 GIR_Done, 15671 // Label 1066: @36830 15672 GIM_Try, /*On fail goto*//*Label 1067*/ 36881, // Rule ID 3698 // 15673 GIM_CheckFeatures, GIFBS_HasLSE, 15674 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 15675 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 15676 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15677 // MIs[0] Rn 15678 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15679 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15680 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15681 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_8>><<P:Predicate_atomic_load_umin_8_acq_rel>> => (LDUMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15682 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALB, 15683 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15684 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15685 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15686 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15687 GIR_EraseFromParent, /*InsnID*/0, 15688 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15689 // GIR_Coverage, 3698, 15690 GIR_Done, 15691 // Label 1067: @36881 15692 GIM_Try, /*On fail goto*//*Label 1068*/ 36932, // Rule ID 3699 // 15693 GIM_CheckFeatures, GIFBS_HasLSE, 15694 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 15695 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 15696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15697 // MIs[0] Rn 15698 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 15701 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_8>><<P:Predicate_atomic_load_umin_8_seq_cst>> => (LDUMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15702 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALB, 15703 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15706 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15707 GIR_EraseFromParent, /*InsnID*/0, 15708 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15709 // GIR_Coverage, 3699, 15710 GIR_Done, 15711 // Label 1068: @36932 15712 GIM_Reject, 15713 // Label 1053: @36933 15714 GIM_Reject, 15715 // Label 1051: @36934 15716 GIM_Try, /*On fail goto*//*Label 1069*/ 37180, 15717 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 15718 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 15719 GIM_Try, /*On fail goto*//*Label 1070*/ 36991, // Rule ID 3680 // 15720 GIM_CheckFeatures, GIFBS_HasLSE, 15721 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 15722 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 15723 // MIs[0] Rn 15724 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15726 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 15727 // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_monotonic>> => (LDUMINX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15728 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINX, 15729 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15730 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15731 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15732 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15733 GIR_EraseFromParent, /*InsnID*/0, 15734 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15735 // GIR_Coverage, 3680, 15736 GIR_Done, 15737 // Label 1070: @36991 15738 GIM_Try, /*On fail goto*//*Label 1071*/ 37038, // Rule ID 3681 // 15739 GIM_CheckFeatures, GIFBS_HasLSE, 15740 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 15741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 15742 // MIs[0] Rn 15743 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15744 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15745 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 15746 // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acquire>> => (LDUMINAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15747 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAX, 15748 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15749 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15750 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15751 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15752 GIR_EraseFromParent, /*InsnID*/0, 15753 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15754 // GIR_Coverage, 3681, 15755 GIR_Done, 15756 // Label 1071: @37038 15757 GIM_Try, /*On fail goto*//*Label 1072*/ 37085, // Rule ID 3682 // 15758 GIM_CheckFeatures, GIFBS_HasLSE, 15759 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 15760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 15761 // MIs[0] Rn 15762 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15763 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 15765 // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_release>> => (LDUMINLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15766 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLX, 15767 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15768 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15770 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15771 GIR_EraseFromParent, /*InsnID*/0, 15772 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15773 // GIR_Coverage, 3682, 15774 GIR_Done, 15775 // Label 1072: @37085 15776 GIM_Try, /*On fail goto*//*Label 1073*/ 37132, // Rule ID 3683 // 15777 GIM_CheckFeatures, GIFBS_HasLSE, 15778 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 15779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 15780 // MIs[0] Rn 15781 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15782 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15783 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 15784 // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acq_rel>> => (LDUMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15785 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALX, 15786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15787 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15788 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15789 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15790 GIR_EraseFromParent, /*InsnID*/0, 15791 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15792 // GIR_Coverage, 3683, 15793 GIR_Done, 15794 // Label 1073: @37132 15795 GIM_Try, /*On fail goto*//*Label 1074*/ 37179, // Rule ID 3684 // 15796 GIM_CheckFeatures, GIFBS_HasLSE, 15797 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 15798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 15799 // MIs[0] Rn 15800 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 15801 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 15802 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 15803 // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_seq_cst>> => (LDUMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) 15804 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALX, 15805 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15806 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 15807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 15808 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 15809 GIR_EraseFromParent, /*InsnID*/0, 15810 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15811 // GIR_Coverage, 3684, 15812 GIR_Done, 15813 // Label 1074: @37179 15814 GIM_Reject, 15815 // Label 1069: @37180 15816 GIM_Reject, 15817 // Label 1052: @37181 15818 GIM_Reject, 15819 // Label 24: @37182 15820 GIM_Try, /*On fail goto*//*Label 1075*/ 37214, // Rule ID 1830 // 15821 GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, 15822 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_get_fpcr, 15823 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 15824 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 15825 // (intrinsic_wo_chain:{ *:[i64] } 206:{ *:[iPTR] }) => (MRS:{ *:[i64] } 55840:{ *:[i32] }) 15826 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MRS, 15827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt 15828 GIR_AddImm, /*InsnID*/0, /*Imm*/55840, 15829 GIR_EraseFromParent, /*InsnID*/0, 15830 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15831 // GIR_Coverage, 1830, 15832 GIR_Done, 15833 // Label 1075: @37214 15834 GIM_Try, /*On fail goto*//*Label 1076*/ 45772, 15835 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, 15836 GIM_Try, /*On fail goto*//*Label 1077*/ 37307, // Rule ID 3087 // 15837 GIM_CheckFeatures, GIFBS_HasFuseAES, 15838 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesmc, 15839 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 15840 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 15841 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 15842 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 15843 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 15844 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 15845 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_crypto_aese, 15846 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, 15847 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, 15848 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 15849 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 15850 GIM_CheckIsSafeToFold, /*InsnID*/1, 15851 // (intrinsic_wo_chain:{ *:[v16i8] } 193:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v16i8] } 191:{ *:[iPTR] }, V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2)) => (AESMCrrTied:{ *:[v16i8] } (AESErr:{ *:[v16i8] } V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2)) 15852 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, 15853 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::AESErr, 15854 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 15855 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1 15856 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // src2 15857 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 15858 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESMCrrTied, 15859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 15860 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 15861 GIR_EraseFromParent, /*InsnID*/0, 15862 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15863 // GIR_Coverage, 3087, 15864 GIR_Done, 15865 // Label 1077: @37307 15866 GIM_Try, /*On fail goto*//*Label 1078*/ 37395, // Rule ID 3088 // 15867 GIM_CheckFeatures, GIFBS_HasFuseAES, 15868 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesimc, 15869 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 15870 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 15871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 15872 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 15873 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 15874 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 15875 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_crypto_aesd, 15876 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, 15877 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, 15878 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 15879 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 15880 GIM_CheckIsSafeToFold, /*InsnID*/1, 15881 // (intrinsic_wo_chain:{ *:[v16i8] } 192:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v16i8] } 190:{ *:[iPTR] }, V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2)) => (AESIMCrrTied:{ *:[v16i8] } (AESDrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2)) 15882 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, 15883 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::AESDrr, 15884 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 15885 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1 15886 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // src2 15887 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 15888 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESIMCrrTied, 15889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 15890 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 15891 GIR_EraseFromParent, /*InsnID*/0, 15892 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15893 // GIR_Coverage, 3088, 15894 GIR_Done, 15895 // Label 1078: @37395 15896 GIM_Try, /*On fail goto*//*Label 1079*/ 37435, // Rule ID 272 // 15897 GIM_CheckFeatures, GIFBS_HasFullFP16, 15898 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, 15899 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 15900 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 15901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 15903 // (intrinsic_wo_chain:{ *:[i32] } 221:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTASUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) 15904 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWHr, 15905 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 15906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 15907 GIR_EraseFromParent, /*InsnID*/0, 15908 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15909 // GIR_Coverage, 272, 15910 GIR_Done, 15911 // Label 1079: @37435 15912 GIM_Try, /*On fail goto*//*Label 1080*/ 37475, // Rule ID 273 // 15913 GIM_CheckFeatures, GIFBS_HasFullFP16, 15914 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, 15915 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 15916 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 15917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 15918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 15919 // (intrinsic_wo_chain:{ *:[i64] } 221:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTASUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) 15920 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXHr, 15921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 15922 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 15923 GIR_EraseFromParent, /*InsnID*/0, 15924 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15925 // GIR_Coverage, 273, 15926 GIR_Done, 15927 // Label 1080: @37475 15928 GIM_Try, /*On fail goto*//*Label 1081*/ 37515, // Rule ID 274 // 15929 GIM_CheckFeatures, GIFBS_HasFPARMv8, 15930 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, 15931 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 15932 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 15933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 15935 // (intrinsic_wo_chain:{ *:[i32] } 221:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTASUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) 15936 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWSr, 15937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 15938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 15939 GIR_EraseFromParent, /*InsnID*/0, 15940 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15941 // GIR_Coverage, 274, 15942 GIR_Done, 15943 // Label 1081: @37515 15944 GIM_Try, /*On fail goto*//*Label 1082*/ 37555, // Rule ID 275 // 15945 GIM_CheckFeatures, GIFBS_HasFPARMv8, 15946 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, 15947 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 15948 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 15949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 15950 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 15951 // (intrinsic_wo_chain:{ *:[i64] } 221:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTASUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) 15952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXSr, 15953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 15954 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 15955 GIR_EraseFromParent, /*InsnID*/0, 15956 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15957 // GIR_Coverage, 275, 15958 GIR_Done, 15959 // Label 1082: @37555 15960 GIM_Try, /*On fail goto*//*Label 1083*/ 37595, // Rule ID 276 // 15961 GIM_CheckFeatures, GIFBS_HasFPARMv8, 15962 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, 15963 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 15964 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 15965 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 15967 // (intrinsic_wo_chain:{ *:[i32] } 221:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTASUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) 15968 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWDr, 15969 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 15970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 15971 GIR_EraseFromParent, /*InsnID*/0, 15972 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15973 // GIR_Coverage, 276, 15974 GIR_Done, 15975 // Label 1083: @37595 15976 GIM_Try, /*On fail goto*//*Label 1084*/ 37635, // Rule ID 277 // 15977 GIM_CheckFeatures, GIFBS_HasFPARMv8, 15978 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, 15979 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 15980 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 15981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 15982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 15983 // (intrinsic_wo_chain:{ *:[i64] } 221:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTASUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) 15984 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXDr, 15985 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 15986 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 15987 GIR_EraseFromParent, /*InsnID*/0, 15988 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15989 // GIR_Coverage, 277, 15990 GIR_Done, 15991 // Label 1084: @37635 15992 GIM_Try, /*On fail goto*//*Label 1085*/ 37675, // Rule ID 278 // 15993 GIM_CheckFeatures, GIFBS_HasFullFP16, 15994 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, 15995 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 15996 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 15997 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 15998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 15999 // (intrinsic_wo_chain:{ *:[i32] } 222:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTAUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) 16000 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWHr, 16001 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16002 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16003 GIR_EraseFromParent, /*InsnID*/0, 16004 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16005 // GIR_Coverage, 278, 16006 GIR_Done, 16007 // Label 1085: @37675 16008 GIM_Try, /*On fail goto*//*Label 1086*/ 37715, // Rule ID 279 // 16009 GIM_CheckFeatures, GIFBS_HasFullFP16, 16010 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, 16011 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16012 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 16013 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16014 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 16015 // (intrinsic_wo_chain:{ *:[i64] } 222:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTAUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) 16016 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXHr, 16017 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16018 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16019 GIR_EraseFromParent, /*InsnID*/0, 16020 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16021 // GIR_Coverage, 279, 16022 GIR_Done, 16023 // Label 1086: @37715 16024 GIM_Try, /*On fail goto*//*Label 1087*/ 37755, // Rule ID 280 // 16025 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16026 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, 16027 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16028 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16030 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 16031 // (intrinsic_wo_chain:{ *:[i32] } 222:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTAUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) 16032 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWSr, 16033 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16034 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16035 GIR_EraseFromParent, /*InsnID*/0, 16036 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16037 // GIR_Coverage, 280, 16038 GIR_Done, 16039 // Label 1087: @37755 16040 GIM_Try, /*On fail goto*//*Label 1088*/ 37795, // Rule ID 281 // 16041 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16042 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, 16043 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16044 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 16047 // (intrinsic_wo_chain:{ *:[i64] } 222:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTAUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) 16048 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXSr, 16049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16051 GIR_EraseFromParent, /*InsnID*/0, 16052 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16053 // GIR_Coverage, 281, 16054 GIR_Done, 16055 // Label 1088: @37795 16056 GIM_Try, /*On fail goto*//*Label 1089*/ 37835, // Rule ID 282 // 16057 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16058 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, 16059 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16060 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16063 // (intrinsic_wo_chain:{ *:[i32] } 222:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTAUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) 16064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWDr, 16065 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16066 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16067 GIR_EraseFromParent, /*InsnID*/0, 16068 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16069 // GIR_Coverage, 282, 16070 GIR_Done, 16071 // Label 1089: @37835 16072 GIM_Try, /*On fail goto*//*Label 1090*/ 37875, // Rule ID 283 // 16073 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16074 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, 16075 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16076 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16077 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16079 // (intrinsic_wo_chain:{ *:[i64] } 222:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTAUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) 16080 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXDr, 16081 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16083 GIR_EraseFromParent, /*InsnID*/0, 16084 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16085 // GIR_Coverage, 283, 16086 GIR_Done, 16087 // Label 1090: @37875 16088 GIM_Try, /*On fail goto*//*Label 1091*/ 37915, // Rule ID 284 // 16089 GIM_CheckFeatures, GIFBS_HasFullFP16, 16090 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, 16091 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16092 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 16093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 16095 // (intrinsic_wo_chain:{ *:[i32] } 223:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) 16096 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWHr, 16097 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16098 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16099 GIR_EraseFromParent, /*InsnID*/0, 16100 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16101 // GIR_Coverage, 284, 16102 GIR_Done, 16103 // Label 1091: @37915 16104 GIM_Try, /*On fail goto*//*Label 1092*/ 37955, // Rule ID 285 // 16105 GIM_CheckFeatures, GIFBS_HasFullFP16, 16106 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, 16107 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16108 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 16109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 16111 // (intrinsic_wo_chain:{ *:[i64] } 223:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) 16112 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXHr, 16113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16114 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16115 GIR_EraseFromParent, /*InsnID*/0, 16116 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16117 // GIR_Coverage, 285, 16118 GIR_Done, 16119 // Label 1092: @37955 16120 GIM_Try, /*On fail goto*//*Label 1093*/ 37995, // Rule ID 286 // 16121 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16122 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, 16123 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16124 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 16127 // (intrinsic_wo_chain:{ *:[i32] } 223:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) 16128 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWSr, 16129 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16130 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16131 GIR_EraseFromParent, /*InsnID*/0, 16132 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16133 // GIR_Coverage, 286, 16134 GIR_Done, 16135 // Label 1093: @37995 16136 GIM_Try, /*On fail goto*//*Label 1094*/ 38035, // Rule ID 287 // 16137 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16138 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, 16139 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16140 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16141 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16142 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 16143 // (intrinsic_wo_chain:{ *:[i64] } 223:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) 16144 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXSr, 16145 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16146 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16147 GIR_EraseFromParent, /*InsnID*/0, 16148 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16149 // GIR_Coverage, 287, 16150 GIR_Done, 16151 // Label 1094: @38035 16152 GIM_Try, /*On fail goto*//*Label 1095*/ 38075, // Rule ID 288 // 16153 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16154 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, 16155 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16156 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16159 // (intrinsic_wo_chain:{ *:[i32] } 223:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) 16160 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWDr, 16161 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16163 GIR_EraseFromParent, /*InsnID*/0, 16164 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16165 // GIR_Coverage, 288, 16166 GIR_Done, 16167 // Label 1095: @38075 16168 GIM_Try, /*On fail goto*//*Label 1096*/ 38115, // Rule ID 289 // 16169 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16170 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, 16171 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16172 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16175 // (intrinsic_wo_chain:{ *:[i64] } 223:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) 16176 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXDr, 16177 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16178 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16179 GIR_EraseFromParent, /*InsnID*/0, 16180 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16181 // GIR_Coverage, 289, 16182 GIR_Done, 16183 // Label 1096: @38115 16184 GIM_Try, /*On fail goto*//*Label 1097*/ 38155, // Rule ID 290 // 16185 GIM_CheckFeatures, GIFBS_HasFullFP16, 16186 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, 16187 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16188 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 16189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16190 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 16191 // (intrinsic_wo_chain:{ *:[i32] } 224:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) 16192 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWHr, 16193 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16194 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16195 GIR_EraseFromParent, /*InsnID*/0, 16196 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16197 // GIR_Coverage, 290, 16198 GIR_Done, 16199 // Label 1097: @38155 16200 GIM_Try, /*On fail goto*//*Label 1098*/ 38195, // Rule ID 291 // 16201 GIM_CheckFeatures, GIFBS_HasFullFP16, 16202 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, 16203 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16204 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 16205 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 16207 // (intrinsic_wo_chain:{ *:[i64] } 224:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) 16208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXHr, 16209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16211 GIR_EraseFromParent, /*InsnID*/0, 16212 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16213 // GIR_Coverage, 291, 16214 GIR_Done, 16215 // Label 1098: @38195 16216 GIM_Try, /*On fail goto*//*Label 1099*/ 38235, // Rule ID 292 // 16217 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16218 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, 16219 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16220 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16221 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16222 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 16223 // (intrinsic_wo_chain:{ *:[i32] } 224:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) 16224 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWSr, 16225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16226 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16227 GIR_EraseFromParent, /*InsnID*/0, 16228 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16229 // GIR_Coverage, 292, 16230 GIR_Done, 16231 // Label 1099: @38235 16232 GIM_Try, /*On fail goto*//*Label 1100*/ 38275, // Rule ID 293 // 16233 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16234 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, 16235 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16236 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 16239 // (intrinsic_wo_chain:{ *:[i64] } 224:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) 16240 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXSr, 16241 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16242 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16243 GIR_EraseFromParent, /*InsnID*/0, 16244 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16245 // GIR_Coverage, 293, 16246 GIR_Done, 16247 // Label 1100: @38275 16248 GIM_Try, /*On fail goto*//*Label 1101*/ 38315, // Rule ID 294 // 16249 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16250 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, 16251 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16252 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16255 // (intrinsic_wo_chain:{ *:[i32] } 224:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) 16256 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWDr, 16257 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16258 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16259 GIR_EraseFromParent, /*InsnID*/0, 16260 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16261 // GIR_Coverage, 294, 16262 GIR_Done, 16263 // Label 1101: @38315 16264 GIM_Try, /*On fail goto*//*Label 1102*/ 38355, // Rule ID 295 // 16265 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16266 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, 16267 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16268 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16269 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16270 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16271 // (intrinsic_wo_chain:{ *:[i64] } 224:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) 16272 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXDr, 16273 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16274 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16275 GIR_EraseFromParent, /*InsnID*/0, 16276 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16277 // GIR_Coverage, 295, 16278 GIR_Done, 16279 // Label 1102: @38355 16280 GIM_Try, /*On fail goto*//*Label 1103*/ 38395, // Rule ID 296 // 16281 GIM_CheckFeatures, GIFBS_HasFullFP16, 16282 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, 16283 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16284 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 16285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 16287 // (intrinsic_wo_chain:{ *:[i32] } 225:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) 16288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUWHr, 16289 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16290 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16291 GIR_EraseFromParent, /*InsnID*/0, 16292 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16293 // GIR_Coverage, 296, 16294 GIR_Done, 16295 // Label 1103: @38395 16296 GIM_Try, /*On fail goto*//*Label 1104*/ 38435, // Rule ID 297 // 16297 GIM_CheckFeatures, GIFBS_HasFullFP16, 16298 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, 16299 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16300 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 16301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 16303 // (intrinsic_wo_chain:{ *:[i64] } 225:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) 16304 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUXHr, 16305 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16306 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16307 GIR_EraseFromParent, /*InsnID*/0, 16308 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16309 // GIR_Coverage, 297, 16310 GIR_Done, 16311 // Label 1104: @38435 16312 GIM_Try, /*On fail goto*//*Label 1105*/ 38475, // Rule ID 298 // 16313 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16314 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, 16315 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16316 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 16319 // (intrinsic_wo_chain:{ *:[i32] } 225:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) 16320 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUWSr, 16321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16322 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16323 GIR_EraseFromParent, /*InsnID*/0, 16324 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16325 // GIR_Coverage, 298, 16326 GIR_Done, 16327 // Label 1105: @38475 16328 GIM_Try, /*On fail goto*//*Label 1106*/ 38515, // Rule ID 299 // 16329 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16330 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, 16331 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16332 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 16335 // (intrinsic_wo_chain:{ *:[i64] } 225:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) 16336 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUXSr, 16337 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16338 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16339 GIR_EraseFromParent, /*InsnID*/0, 16340 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16341 // GIR_Coverage, 299, 16342 GIR_Done, 16343 // Label 1106: @38515 16344 GIM_Try, /*On fail goto*//*Label 1107*/ 38555, // Rule ID 300 // 16345 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16346 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, 16347 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16348 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16351 // (intrinsic_wo_chain:{ *:[i32] } 225:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) 16352 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUWDr, 16353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16355 GIR_EraseFromParent, /*InsnID*/0, 16356 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16357 // GIR_Coverage, 300, 16358 GIR_Done, 16359 // Label 1107: @38555 16360 GIM_Try, /*On fail goto*//*Label 1108*/ 38595, // Rule ID 301 // 16361 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16362 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, 16363 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16364 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16366 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16367 // (intrinsic_wo_chain:{ *:[i64] } 225:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) 16368 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUXDr, 16369 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16370 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16371 GIR_EraseFromParent, /*InsnID*/0, 16372 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16373 // GIR_Coverage, 301, 16374 GIR_Done, 16375 // Label 1108: @38595 16376 GIM_Try, /*On fail goto*//*Label 1109*/ 38635, // Rule ID 302 // 16377 GIM_CheckFeatures, GIFBS_HasFullFP16, 16378 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, 16379 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16380 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 16381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 16383 // (intrinsic_wo_chain:{ *:[i32] } 226:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) 16384 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUWHr, 16385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16386 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16387 GIR_EraseFromParent, /*InsnID*/0, 16388 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16389 // GIR_Coverage, 302, 16390 GIR_Done, 16391 // Label 1109: @38635 16392 GIM_Try, /*On fail goto*//*Label 1110*/ 38675, // Rule ID 303 // 16393 GIM_CheckFeatures, GIFBS_HasFullFP16, 16394 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, 16395 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16396 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 16397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 16399 // (intrinsic_wo_chain:{ *:[i64] } 226:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) 16400 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUXHr, 16401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16403 GIR_EraseFromParent, /*InsnID*/0, 16404 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16405 // GIR_Coverage, 303, 16406 GIR_Done, 16407 // Label 1110: @38675 16408 GIM_Try, /*On fail goto*//*Label 1111*/ 38715, // Rule ID 304 // 16409 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16410 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, 16411 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16412 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 16415 // (intrinsic_wo_chain:{ *:[i32] } 226:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) 16416 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUWSr, 16417 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16418 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16419 GIR_EraseFromParent, /*InsnID*/0, 16420 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16421 // GIR_Coverage, 304, 16422 GIR_Done, 16423 // Label 1111: @38715 16424 GIM_Try, /*On fail goto*//*Label 1112*/ 38755, // Rule ID 305 // 16425 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16426 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, 16427 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16428 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 16431 // (intrinsic_wo_chain:{ *:[i64] } 226:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) 16432 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUXSr, 16433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16435 GIR_EraseFromParent, /*InsnID*/0, 16436 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16437 // GIR_Coverage, 305, 16438 GIR_Done, 16439 // Label 1112: @38755 16440 GIM_Try, /*On fail goto*//*Label 1113*/ 38795, // Rule ID 306 // 16441 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16442 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, 16443 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16444 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16447 // (intrinsic_wo_chain:{ *:[i32] } 226:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) 16448 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUWDr, 16449 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16450 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16451 GIR_EraseFromParent, /*InsnID*/0, 16452 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16453 // GIR_Coverage, 306, 16454 GIR_Done, 16455 // Label 1113: @38795 16456 GIM_Try, /*On fail goto*//*Label 1114*/ 38835, // Rule ID 307 // 16457 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16458 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, 16459 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16460 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16461 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16462 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16463 // (intrinsic_wo_chain:{ *:[i64] } 226:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) 16464 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUXDr, 16465 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16466 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16467 GIR_EraseFromParent, /*InsnID*/0, 16468 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16469 // GIR_Coverage, 307, 16470 GIR_Done, 16471 // Label 1114: @38835 16472 GIM_Try, /*On fail goto*//*Label 1115*/ 38875, // Rule ID 308 // 16473 GIM_CheckFeatures, GIFBS_HasFullFP16, 16474 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, 16475 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16476 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 16477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 16479 // (intrinsic_wo_chain:{ *:[i32] } 227:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) 16480 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWHr, 16481 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16482 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16483 GIR_EraseFromParent, /*InsnID*/0, 16484 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16485 // GIR_Coverage, 308, 16486 GIR_Done, 16487 // Label 1115: @38875 16488 GIM_Try, /*On fail goto*//*Label 1116*/ 38915, // Rule ID 309 // 16489 GIM_CheckFeatures, GIFBS_HasFullFP16, 16490 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, 16491 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16492 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 16493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 16495 // (intrinsic_wo_chain:{ *:[i64] } 227:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) 16496 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXHr, 16497 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16498 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16499 GIR_EraseFromParent, /*InsnID*/0, 16500 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16501 // GIR_Coverage, 309, 16502 GIR_Done, 16503 // Label 1116: @38915 16504 GIM_Try, /*On fail goto*//*Label 1117*/ 38955, // Rule ID 310 // 16505 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16506 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, 16507 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16508 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16510 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 16511 // (intrinsic_wo_chain:{ *:[i32] } 227:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) 16512 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWSr, 16513 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16514 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16515 GIR_EraseFromParent, /*InsnID*/0, 16516 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16517 // GIR_Coverage, 310, 16518 GIR_Done, 16519 // Label 1117: @38955 16520 GIM_Try, /*On fail goto*//*Label 1118*/ 38995, // Rule ID 311 // 16521 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16522 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, 16523 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16524 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 16527 // (intrinsic_wo_chain:{ *:[i64] } 227:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) 16528 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXSr, 16529 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16530 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16531 GIR_EraseFromParent, /*InsnID*/0, 16532 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16533 // GIR_Coverage, 311, 16534 GIR_Done, 16535 // Label 1118: @38995 16536 GIM_Try, /*On fail goto*//*Label 1119*/ 39035, // Rule ID 312 // 16537 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16538 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, 16539 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16540 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16542 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16543 // (intrinsic_wo_chain:{ *:[i32] } 227:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) 16544 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWDr, 16545 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16546 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16547 GIR_EraseFromParent, /*InsnID*/0, 16548 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16549 // GIR_Coverage, 312, 16550 GIR_Done, 16551 // Label 1119: @39035 16552 GIM_Try, /*On fail goto*//*Label 1120*/ 39075, // Rule ID 313 // 16553 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16554 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, 16555 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16556 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16558 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16559 // (intrinsic_wo_chain:{ *:[i64] } 227:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) 16560 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXDr, 16561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16563 GIR_EraseFromParent, /*InsnID*/0, 16564 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16565 // GIR_Coverage, 313, 16566 GIR_Done, 16567 // Label 1120: @39075 16568 GIM_Try, /*On fail goto*//*Label 1121*/ 39115, // Rule ID 314 // 16569 GIM_CheckFeatures, GIFBS_HasFullFP16, 16570 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, 16571 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16572 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 16573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 16575 // (intrinsic_wo_chain:{ *:[i32] } 228:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) 16576 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWHr, 16577 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16578 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16579 GIR_EraseFromParent, /*InsnID*/0, 16580 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16581 // GIR_Coverage, 314, 16582 GIR_Done, 16583 // Label 1121: @39115 16584 GIM_Try, /*On fail goto*//*Label 1122*/ 39155, // Rule ID 315 // 16585 GIM_CheckFeatures, GIFBS_HasFullFP16, 16586 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, 16587 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16588 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 16589 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16590 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 16591 // (intrinsic_wo_chain:{ *:[i64] } 228:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) 16592 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXHr, 16593 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16594 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16595 GIR_EraseFromParent, /*InsnID*/0, 16596 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16597 // GIR_Coverage, 315, 16598 GIR_Done, 16599 // Label 1122: @39155 16600 GIM_Try, /*On fail goto*//*Label 1123*/ 39195, // Rule ID 316 // 16601 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16602 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, 16603 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16604 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16606 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 16607 // (intrinsic_wo_chain:{ *:[i32] } 228:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) 16608 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWSr, 16609 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16610 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16611 GIR_EraseFromParent, /*InsnID*/0, 16612 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16613 // GIR_Coverage, 316, 16614 GIR_Done, 16615 // Label 1123: @39195 16616 GIM_Try, /*On fail goto*//*Label 1124*/ 39235, // Rule ID 317 // 16617 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16618 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, 16619 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16620 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16621 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16622 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 16623 // (intrinsic_wo_chain:{ *:[i64] } 228:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) 16624 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXSr, 16625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16626 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16627 GIR_EraseFromParent, /*InsnID*/0, 16628 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16629 // GIR_Coverage, 317, 16630 GIR_Done, 16631 // Label 1124: @39235 16632 GIM_Try, /*On fail goto*//*Label 1125*/ 39275, // Rule ID 318 // 16633 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16634 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, 16635 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16636 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 16638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16639 // (intrinsic_wo_chain:{ *:[i32] } 228:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) 16640 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWDr, 16641 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16642 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16643 GIR_EraseFromParent, /*InsnID*/0, 16644 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16645 // GIR_Coverage, 318, 16646 GIR_Done, 16647 // Label 1125: @39275 16648 GIM_Try, /*On fail goto*//*Label 1126*/ 39315, // Rule ID 319 // 16649 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16650 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, 16651 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16652 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 16654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16655 // (intrinsic_wo_chain:{ *:[i64] } 228:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) 16656 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXDr, 16657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16659 GIR_EraseFromParent, /*InsnID*/0, 16660 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16661 // GIR_Coverage, 319, 16662 GIR_Done, 16663 // Label 1126: @39315 16664 GIM_Try, /*On fail goto*//*Label 1127*/ 39355, // Rule ID 392 // 16665 GIM_CheckFeatures, GIFBS_HasFullFP16, 16666 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, 16667 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 16668 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 16669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 16670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 16671 // (intrinsic_wo_chain:{ *:[f16] } 248:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FRINTNHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) 16672 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNHr, 16673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16675 GIR_EraseFromParent, /*InsnID*/0, 16676 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16677 // GIR_Coverage, 392, 16678 GIR_Done, 16679 // Label 1127: @39355 16680 GIM_Try, /*On fail goto*//*Label 1128*/ 39395, // Rule ID 393 // 16681 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16682 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, 16683 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 16684 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 16685 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 16686 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 16687 // (intrinsic_wo_chain:{ *:[f32] } 248:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRINTNSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) 16688 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNSr, 16689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16690 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16691 GIR_EraseFromParent, /*InsnID*/0, 16692 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16693 // GIR_Coverage, 393, 16694 GIR_Done, 16695 // Label 1128: @39395 16696 GIM_Try, /*On fail goto*//*Label 1129*/ 39435, // Rule ID 394 // 16697 GIM_CheckFeatures, GIFBS_HasFPARMv8, 16698 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, 16699 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 16700 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 16701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 16702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16703 // (intrinsic_wo_chain:{ *:[f64] } 248:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRINTNDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) 16704 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNDr, 16705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16706 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16707 GIR_EraseFromParent, /*InsnID*/0, 16708 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16709 // GIR_Coverage, 394, 16710 GIR_Done, 16711 // Label 1129: @39435 16712 GIM_Try, /*On fail goto*//*Label 1130*/ 39475, // Rule ID 475 // 16713 GIM_CheckFeatures, GIFBS_HasNEON, 16714 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, 16715 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 16716 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 16717 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 16718 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16719 // (intrinsic_wo_chain:{ *:[v8i8] } 216:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (CLSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) 16720 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv8i8, 16721 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16722 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16723 GIR_EraseFromParent, /*InsnID*/0, 16724 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16725 // GIR_Coverage, 475, 16726 GIR_Done, 16727 // Label 1130: @39475 16728 GIM_Try, /*On fail goto*//*Label 1131*/ 39515, // Rule ID 476 // 16729 GIM_CheckFeatures, GIFBS_HasNEON, 16730 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, 16731 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 16732 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 16733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 16734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 16735 // (intrinsic_wo_chain:{ *:[v16i8] } 216:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (CLSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) 16736 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv16i8, 16737 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16738 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16739 GIR_EraseFromParent, /*InsnID*/0, 16740 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16741 // GIR_Coverage, 476, 16742 GIR_Done, 16743 // Label 1131: @39515 16744 GIM_Try, /*On fail goto*//*Label 1132*/ 39555, // Rule ID 477 // 16745 GIM_CheckFeatures, GIFBS_HasNEON, 16746 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, 16747 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 16748 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 16749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 16750 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16751 // (intrinsic_wo_chain:{ *:[v4i16] } 216:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (CLSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) 16752 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv4i16, 16753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16754 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16755 GIR_EraseFromParent, /*InsnID*/0, 16756 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16757 // GIR_Coverage, 477, 16758 GIR_Done, 16759 // Label 1132: @39555 16760 GIM_Try, /*On fail goto*//*Label 1133*/ 39595, // Rule ID 478 // 16761 GIM_CheckFeatures, GIFBS_HasNEON, 16762 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, 16763 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 16764 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 16765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 16766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 16767 // (intrinsic_wo_chain:{ *:[v8i16] } 216:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (CLSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) 16768 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv8i16, 16769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16771 GIR_EraseFromParent, /*InsnID*/0, 16772 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16773 // GIR_Coverage, 478, 16774 GIR_Done, 16775 // Label 1133: @39595 16776 GIM_Try, /*On fail goto*//*Label 1134*/ 39635, // Rule ID 479 // 16777 GIM_CheckFeatures, GIFBS_HasNEON, 16778 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, 16779 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 16780 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 16781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 16782 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16783 // (intrinsic_wo_chain:{ *:[v2i32] } 216:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (CLSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) 16784 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv2i32, 16785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16787 GIR_EraseFromParent, /*InsnID*/0, 16788 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16789 // GIR_Coverage, 479, 16790 GIR_Done, 16791 // Label 1134: @39635 16792 GIM_Try, /*On fail goto*//*Label 1135*/ 39675, // Rule ID 480 // 16793 GIM_CheckFeatures, GIFBS_HasNEON, 16794 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, 16795 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 16796 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 16797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 16798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 16799 // (intrinsic_wo_chain:{ *:[v4i32] } 216:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (CLSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) 16800 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv4i32, 16801 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16802 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16803 GIR_EraseFromParent, /*InsnID*/0, 16804 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16805 // GIR_Coverage, 480, 16806 GIR_Done, 16807 // Label 1135: @39675 16808 GIM_Try, /*On fail goto*//*Label 1136*/ 39715, // Rule ID 554 // 16809 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 16810 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, 16811 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 16812 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 16813 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 16814 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16815 // (intrinsic_wo_chain:{ *:[v4i16] } 221:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTASv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) 16816 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv4f16, 16817 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16818 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16819 GIR_EraseFromParent, /*InsnID*/0, 16820 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16821 // GIR_Coverage, 554, 16822 GIR_Done, 16823 // Label 1136: @39715 16824 GIM_Try, /*On fail goto*//*Label 1137*/ 39755, // Rule ID 555 // 16825 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 16826 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, 16827 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 16828 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 16829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 16830 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 16831 // (intrinsic_wo_chain:{ *:[v8i16] } 221:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTASv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) 16832 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv8f16, 16833 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16834 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16835 GIR_EraseFromParent, /*InsnID*/0, 16836 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16837 // GIR_Coverage, 555, 16838 GIR_Done, 16839 // Label 1137: @39755 16840 GIM_Try, /*On fail goto*//*Label 1138*/ 39795, // Rule ID 556 // 16841 GIM_CheckFeatures, GIFBS_HasNEON, 16842 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, 16843 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 16844 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 16845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 16846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16847 // (intrinsic_wo_chain:{ *:[v2i32] } 221:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTASv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) 16848 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv2f32, 16849 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16851 GIR_EraseFromParent, /*InsnID*/0, 16852 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16853 // GIR_Coverage, 556, 16854 GIR_Done, 16855 // Label 1138: @39795 16856 GIM_Try, /*On fail goto*//*Label 1139*/ 39835, // Rule ID 557 // 16857 GIM_CheckFeatures, GIFBS_HasNEON, 16858 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, 16859 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 16860 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 16861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 16862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 16863 // (intrinsic_wo_chain:{ *:[v4i32] } 221:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTASv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) 16864 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv4f32, 16865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16866 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16867 GIR_EraseFromParent, /*InsnID*/0, 16868 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16869 // GIR_Coverage, 557, 16870 GIR_Done, 16871 // Label 1139: @39835 16872 GIM_Try, /*On fail goto*//*Label 1140*/ 39875, // Rule ID 558 // 16873 GIM_CheckFeatures, GIFBS_HasNEON, 16874 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, 16875 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 16876 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 16877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 16878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 16879 // (intrinsic_wo_chain:{ *:[v2i64] } 221:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTASv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) 16880 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv2f64, 16881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16883 GIR_EraseFromParent, /*InsnID*/0, 16884 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16885 // GIR_Coverage, 558, 16886 GIR_Done, 16887 // Label 1140: @39875 16888 GIM_Try, /*On fail goto*//*Label 1141*/ 39915, // Rule ID 559 // 16889 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 16890 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, 16891 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 16892 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 16893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 16894 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16895 // (intrinsic_wo_chain:{ *:[v4i16] } 222:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTAUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) 16896 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv4f16, 16897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16898 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16899 GIR_EraseFromParent, /*InsnID*/0, 16900 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16901 // GIR_Coverage, 559, 16902 GIR_Done, 16903 // Label 1141: @39915 16904 GIM_Try, /*On fail goto*//*Label 1142*/ 39955, // Rule ID 560 // 16905 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 16906 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, 16907 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 16908 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 16909 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 16910 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 16911 // (intrinsic_wo_chain:{ *:[v8i16] } 222:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTAUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) 16912 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv8f16, 16913 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16914 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16915 GIR_EraseFromParent, /*InsnID*/0, 16916 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16917 // GIR_Coverage, 560, 16918 GIR_Done, 16919 // Label 1142: @39955 16920 GIM_Try, /*On fail goto*//*Label 1143*/ 39995, // Rule ID 561 // 16921 GIM_CheckFeatures, GIFBS_HasNEON, 16922 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, 16923 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 16924 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 16925 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 16926 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16927 // (intrinsic_wo_chain:{ *:[v2i32] } 222:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTAUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) 16928 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv2f32, 16929 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16930 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16931 GIR_EraseFromParent, /*InsnID*/0, 16932 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16933 // GIR_Coverage, 561, 16934 GIR_Done, 16935 // Label 1143: @39995 16936 GIM_Try, /*On fail goto*//*Label 1144*/ 40035, // Rule ID 562 // 16937 GIM_CheckFeatures, GIFBS_HasNEON, 16938 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, 16939 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 16940 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 16941 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 16942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 16943 // (intrinsic_wo_chain:{ *:[v4i32] } 222:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTAUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) 16944 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv4f32, 16945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16947 GIR_EraseFromParent, /*InsnID*/0, 16948 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16949 // GIR_Coverage, 562, 16950 GIR_Done, 16951 // Label 1144: @40035 16952 GIM_Try, /*On fail goto*//*Label 1145*/ 40075, // Rule ID 563 // 16953 GIM_CheckFeatures, GIFBS_HasNEON, 16954 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, 16955 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 16956 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 16957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 16958 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 16959 // (intrinsic_wo_chain:{ *:[v2i64] } 222:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTAUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) 16960 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv2f64, 16961 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16962 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16963 GIR_EraseFromParent, /*InsnID*/0, 16964 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16965 // GIR_Coverage, 563, 16966 GIR_Done, 16967 // Label 1145: @40075 16968 GIM_Try, /*On fail goto*//*Label 1146*/ 40115, // Rule ID 564 // 16969 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 16970 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, 16971 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 16972 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 16973 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 16974 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 16975 // (intrinsic_wo_chain:{ *:[v4i16] } 223:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTMSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) 16976 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv4f16, 16977 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16978 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16979 GIR_EraseFromParent, /*InsnID*/0, 16980 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16981 // GIR_Coverage, 564, 16982 GIR_Done, 16983 // Label 1146: @40115 16984 GIM_Try, /*On fail goto*//*Label 1147*/ 40155, // Rule ID 565 // 16985 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 16986 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, 16987 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 16988 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 16989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 16990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 16991 // (intrinsic_wo_chain:{ *:[v8i16] } 223:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTMSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) 16992 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv8f16, 16993 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 16994 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 16995 GIR_EraseFromParent, /*InsnID*/0, 16996 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16997 // GIR_Coverage, 565, 16998 GIR_Done, 16999 // Label 1147: @40155 17000 GIM_Try, /*On fail goto*//*Label 1148*/ 40195, // Rule ID 566 // 17001 GIM_CheckFeatures, GIFBS_HasNEON, 17002 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, 17003 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 17004 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 17005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17006 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17007 // (intrinsic_wo_chain:{ *:[v2i32] } 223:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTMSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) 17008 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv2f32, 17009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17011 GIR_EraseFromParent, /*InsnID*/0, 17012 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17013 // GIR_Coverage, 566, 17014 GIR_Done, 17015 // Label 1148: @40195 17016 GIM_Try, /*On fail goto*//*Label 1149*/ 40235, // Rule ID 567 // 17017 GIM_CheckFeatures, GIFBS_HasNEON, 17018 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, 17019 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 17020 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 17021 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17023 // (intrinsic_wo_chain:{ *:[v4i32] } 223:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTMSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) 17024 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv4f32, 17025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17027 GIR_EraseFromParent, /*InsnID*/0, 17028 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17029 // GIR_Coverage, 567, 17030 GIR_Done, 17031 // Label 1149: @40235 17032 GIM_Try, /*On fail goto*//*Label 1150*/ 40275, // Rule ID 568 // 17033 GIM_CheckFeatures, GIFBS_HasNEON, 17034 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, 17035 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 17036 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 17037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17038 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17039 // (intrinsic_wo_chain:{ *:[v2i64] } 223:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTMSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) 17040 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv2f64, 17041 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17042 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17043 GIR_EraseFromParent, /*InsnID*/0, 17044 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17045 // GIR_Coverage, 568, 17046 GIR_Done, 17047 // Label 1150: @40275 17048 GIM_Try, /*On fail goto*//*Label 1151*/ 40315, // Rule ID 569 // 17049 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 17050 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, 17051 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 17052 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 17053 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17054 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17055 // (intrinsic_wo_chain:{ *:[v4i16] } 224:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTMUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) 17056 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv4f16, 17057 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17058 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17059 GIR_EraseFromParent, /*InsnID*/0, 17060 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17061 // GIR_Coverage, 569, 17062 GIR_Done, 17063 // Label 1151: @40315 17064 GIM_Try, /*On fail goto*//*Label 1152*/ 40355, // Rule ID 570 // 17065 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 17066 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, 17067 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 17068 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 17069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17070 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17071 // (intrinsic_wo_chain:{ *:[v8i16] } 224:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTMUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) 17072 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv8f16, 17073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17075 GIR_EraseFromParent, /*InsnID*/0, 17076 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17077 // GIR_Coverage, 570, 17078 GIR_Done, 17079 // Label 1152: @40355 17080 GIM_Try, /*On fail goto*//*Label 1153*/ 40395, // Rule ID 571 // 17081 GIM_CheckFeatures, GIFBS_HasNEON, 17082 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, 17083 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 17084 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 17085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17087 // (intrinsic_wo_chain:{ *:[v2i32] } 224:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTMUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) 17088 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv2f32, 17089 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17090 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17091 GIR_EraseFromParent, /*InsnID*/0, 17092 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17093 // GIR_Coverage, 571, 17094 GIR_Done, 17095 // Label 1153: @40395 17096 GIM_Try, /*On fail goto*//*Label 1154*/ 40435, // Rule ID 572 // 17097 GIM_CheckFeatures, GIFBS_HasNEON, 17098 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, 17099 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 17100 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 17101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17103 // (intrinsic_wo_chain:{ *:[v4i32] } 224:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTMUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) 17104 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv4f32, 17105 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17106 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17107 GIR_EraseFromParent, /*InsnID*/0, 17108 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17109 // GIR_Coverage, 572, 17110 GIR_Done, 17111 // Label 1154: @40435 17112 GIM_Try, /*On fail goto*//*Label 1155*/ 40475, // Rule ID 573 // 17113 GIM_CheckFeatures, GIFBS_HasNEON, 17114 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, 17115 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 17116 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 17117 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17119 // (intrinsic_wo_chain:{ *:[v2i64] } 224:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTMUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) 17120 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv2f64, 17121 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17122 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17123 GIR_EraseFromParent, /*InsnID*/0, 17124 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17125 // GIR_Coverage, 573, 17126 GIR_Done, 17127 // Label 1155: @40475 17128 GIM_Try, /*On fail goto*//*Label 1156*/ 40515, // Rule ID 574 // 17129 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 17130 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, 17131 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 17132 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 17133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17134 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17135 // (intrinsic_wo_chain:{ *:[v4i16] } 225:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTNSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) 17136 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv4f16, 17137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17138 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17139 GIR_EraseFromParent, /*InsnID*/0, 17140 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17141 // GIR_Coverage, 574, 17142 GIR_Done, 17143 // Label 1156: @40515 17144 GIM_Try, /*On fail goto*//*Label 1157*/ 40555, // Rule ID 575 // 17145 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 17146 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, 17147 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 17148 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 17149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17151 // (intrinsic_wo_chain:{ *:[v8i16] } 225:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTNSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) 17152 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv8f16, 17153 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17155 GIR_EraseFromParent, /*InsnID*/0, 17156 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17157 // GIR_Coverage, 575, 17158 GIR_Done, 17159 // Label 1157: @40555 17160 GIM_Try, /*On fail goto*//*Label 1158*/ 40595, // Rule ID 576 // 17161 GIM_CheckFeatures, GIFBS_HasNEON, 17162 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, 17163 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 17164 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 17165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17167 // (intrinsic_wo_chain:{ *:[v2i32] } 225:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTNSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) 17168 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv2f32, 17169 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17170 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17171 GIR_EraseFromParent, /*InsnID*/0, 17172 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17173 // GIR_Coverage, 576, 17174 GIR_Done, 17175 // Label 1158: @40595 17176 GIM_Try, /*On fail goto*//*Label 1159*/ 40635, // Rule ID 577 // 17177 GIM_CheckFeatures, GIFBS_HasNEON, 17178 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, 17179 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 17180 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 17181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17183 // (intrinsic_wo_chain:{ *:[v4i32] } 225:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTNSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) 17184 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv4f32, 17185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17186 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17187 GIR_EraseFromParent, /*InsnID*/0, 17188 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17189 // GIR_Coverage, 577, 17190 GIR_Done, 17191 // Label 1159: @40635 17192 GIM_Try, /*On fail goto*//*Label 1160*/ 40675, // Rule ID 578 // 17193 GIM_CheckFeatures, GIFBS_HasNEON, 17194 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, 17195 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 17196 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 17197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17199 // (intrinsic_wo_chain:{ *:[v2i64] } 225:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTNSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) 17200 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv2f64, 17201 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17202 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17203 GIR_EraseFromParent, /*InsnID*/0, 17204 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17205 // GIR_Coverage, 578, 17206 GIR_Done, 17207 // Label 1160: @40675 17208 GIM_Try, /*On fail goto*//*Label 1161*/ 40715, // Rule ID 579 // 17209 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 17210 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, 17211 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 17212 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 17213 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17215 // (intrinsic_wo_chain:{ *:[v4i16] } 226:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTNUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) 17216 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv4f16, 17217 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17218 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17219 GIR_EraseFromParent, /*InsnID*/0, 17220 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17221 // GIR_Coverage, 579, 17222 GIR_Done, 17223 // Label 1161: @40715 17224 GIM_Try, /*On fail goto*//*Label 1162*/ 40755, // Rule ID 580 // 17225 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 17226 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, 17227 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 17228 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 17229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17230 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17231 // (intrinsic_wo_chain:{ *:[v8i16] } 226:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTNUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) 17232 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv8f16, 17233 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17234 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17235 GIR_EraseFromParent, /*InsnID*/0, 17236 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17237 // GIR_Coverage, 580, 17238 GIR_Done, 17239 // Label 1162: @40755 17240 GIM_Try, /*On fail goto*//*Label 1163*/ 40795, // Rule ID 581 // 17241 GIM_CheckFeatures, GIFBS_HasNEON, 17242 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, 17243 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 17244 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 17245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17247 // (intrinsic_wo_chain:{ *:[v2i32] } 226:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTNUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) 17248 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv2f32, 17249 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17251 GIR_EraseFromParent, /*InsnID*/0, 17252 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17253 // GIR_Coverage, 581, 17254 GIR_Done, 17255 // Label 1163: @40795 17256 GIM_Try, /*On fail goto*//*Label 1164*/ 40835, // Rule ID 582 // 17257 GIM_CheckFeatures, GIFBS_HasNEON, 17258 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, 17259 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 17260 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 17261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17263 // (intrinsic_wo_chain:{ *:[v4i32] } 226:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTNUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) 17264 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv4f32, 17265 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17266 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17267 GIR_EraseFromParent, /*InsnID*/0, 17268 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17269 // GIR_Coverage, 582, 17270 GIR_Done, 17271 // Label 1164: @40835 17272 GIM_Try, /*On fail goto*//*Label 1165*/ 40875, // Rule ID 583 // 17273 GIM_CheckFeatures, GIFBS_HasNEON, 17274 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, 17275 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 17276 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 17277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17279 // (intrinsic_wo_chain:{ *:[v2i64] } 226:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTNUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) 17280 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv2f64, 17281 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17282 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17283 GIR_EraseFromParent, /*InsnID*/0, 17284 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17285 // GIR_Coverage, 583, 17286 GIR_Done, 17287 // Label 1165: @40875 17288 GIM_Try, /*On fail goto*//*Label 1166*/ 40915, // Rule ID 584 // 17289 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 17290 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, 17291 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 17292 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 17293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17295 // (intrinsic_wo_chain:{ *:[v4i16] } 227:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTPSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) 17296 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv4f16, 17297 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17298 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17299 GIR_EraseFromParent, /*InsnID*/0, 17300 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17301 // GIR_Coverage, 584, 17302 GIR_Done, 17303 // Label 1166: @40915 17304 GIM_Try, /*On fail goto*//*Label 1167*/ 40955, // Rule ID 585 // 17305 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 17306 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, 17307 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 17308 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 17309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17311 // (intrinsic_wo_chain:{ *:[v8i16] } 227:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTPSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) 17312 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv8f16, 17313 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17315 GIR_EraseFromParent, /*InsnID*/0, 17316 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17317 // GIR_Coverage, 585, 17318 GIR_Done, 17319 // Label 1167: @40955 17320 GIM_Try, /*On fail goto*//*Label 1168*/ 40995, // Rule ID 586 // 17321 GIM_CheckFeatures, GIFBS_HasNEON, 17322 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, 17323 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 17324 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 17325 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17326 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17327 // (intrinsic_wo_chain:{ *:[v2i32] } 227:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTPSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) 17328 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv2f32, 17329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17330 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17331 GIR_EraseFromParent, /*InsnID*/0, 17332 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17333 // GIR_Coverage, 586, 17334 GIR_Done, 17335 // Label 1168: @40995 17336 GIM_Try, /*On fail goto*//*Label 1169*/ 41035, // Rule ID 587 // 17337 GIM_CheckFeatures, GIFBS_HasNEON, 17338 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, 17339 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 17340 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 17341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17343 // (intrinsic_wo_chain:{ *:[v4i32] } 227:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTPSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) 17344 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv4f32, 17345 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17346 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17347 GIR_EraseFromParent, /*InsnID*/0, 17348 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17349 // GIR_Coverage, 587, 17350 GIR_Done, 17351 // Label 1169: @41035 17352 GIM_Try, /*On fail goto*//*Label 1170*/ 41075, // Rule ID 588 // 17353 GIM_CheckFeatures, GIFBS_HasNEON, 17354 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, 17355 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 17356 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 17357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17359 // (intrinsic_wo_chain:{ *:[v2i64] } 227:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTPSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) 17360 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv2f64, 17361 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17362 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17363 GIR_EraseFromParent, /*InsnID*/0, 17364 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17365 // GIR_Coverage, 588, 17366 GIR_Done, 17367 // Label 1170: @41075 17368 GIM_Try, /*On fail goto*//*Label 1171*/ 41115, // Rule ID 589 // 17369 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 17370 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, 17371 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 17372 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 17373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17374 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17375 // (intrinsic_wo_chain:{ *:[v4i16] } 228:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTPUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) 17376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv4f16, 17377 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17378 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17379 GIR_EraseFromParent, /*InsnID*/0, 17380 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17381 // GIR_Coverage, 589, 17382 GIR_Done, 17383 // Label 1171: @41115 17384 GIM_Try, /*On fail goto*//*Label 1172*/ 41155, // Rule ID 590 // 17385 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 17386 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, 17387 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 17388 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 17389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17391 // (intrinsic_wo_chain:{ *:[v8i16] } 228:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTPUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) 17392 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv8f16, 17393 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17394 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17395 GIR_EraseFromParent, /*InsnID*/0, 17396 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17397 // GIR_Coverage, 590, 17398 GIR_Done, 17399 // Label 1172: @41155 17400 GIM_Try, /*On fail goto*//*Label 1173*/ 41195, // Rule ID 591 // 17401 GIM_CheckFeatures, GIFBS_HasNEON, 17402 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, 17403 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 17404 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 17405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17407 // (intrinsic_wo_chain:{ *:[v2i32] } 228:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTPUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) 17408 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv2f32, 17409 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17410 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17411 GIR_EraseFromParent, /*InsnID*/0, 17412 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17413 // GIR_Coverage, 591, 17414 GIR_Done, 17415 // Label 1173: @41195 17416 GIM_Try, /*On fail goto*//*Label 1174*/ 41235, // Rule ID 592 // 17417 GIM_CheckFeatures, GIFBS_HasNEON, 17418 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, 17419 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 17420 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 17421 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17422 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17423 // (intrinsic_wo_chain:{ *:[v4i32] } 228:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTPUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) 17424 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv4f32, 17425 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17426 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17427 GIR_EraseFromParent, /*InsnID*/0, 17428 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17429 // GIR_Coverage, 592, 17430 GIR_Done, 17431 // Label 1174: @41235 17432 GIM_Try, /*On fail goto*//*Label 1175*/ 41275, // Rule ID 593 // 17433 GIM_CheckFeatures, GIFBS_HasNEON, 17434 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, 17435 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 17436 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 17437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17439 // (intrinsic_wo_chain:{ *:[v2i64] } 228:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTPUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) 17440 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv2f64, 17441 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17442 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17443 GIR_EraseFromParent, /*InsnID*/0, 17444 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17445 // GIR_Coverage, 593, 17446 GIR_Done, 17447 // Label 1175: @41275 17448 GIM_Try, /*On fail goto*//*Label 1176*/ 41315, // Rule ID 594 // 17449 GIM_CheckFeatures, GIFBS_HasNEON, 17450 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtxn, 17451 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 17452 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 17453 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17454 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17455 // (intrinsic_wo_chain:{ *:[v2f32] } 229:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTXNv2f32:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn) 17456 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTXNv2f32, 17457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17458 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17459 GIR_EraseFromParent, /*InsnID*/0, 17460 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17461 // GIR_Coverage, 594, 17462 GIR_Done, 17463 // Label 1176: @41315 17464 GIM_Try, /*On fail goto*//*Label 1177*/ 41355, // Rule ID 610 // 17465 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 17466 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, 17467 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 17468 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 17469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17471 // (intrinsic_wo_chain:{ *:[v4f16] } 245:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FRECPEv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) 17472 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv4f16, 17473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17475 GIR_EraseFromParent, /*InsnID*/0, 17476 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17477 // GIR_Coverage, 610, 17478 GIR_Done, 17479 // Label 1177: @41355 17480 GIM_Try, /*On fail goto*//*Label 1178*/ 41395, // Rule ID 611 // 17481 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 17482 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, 17483 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 17484 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 17485 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17486 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17487 // (intrinsic_wo_chain:{ *:[v8f16] } 245:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FRECPEv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) 17488 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv8f16, 17489 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17490 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17491 GIR_EraseFromParent, /*InsnID*/0, 17492 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17493 // GIR_Coverage, 611, 17494 GIR_Done, 17495 // Label 1178: @41395 17496 GIM_Try, /*On fail goto*//*Label 1179*/ 41435, // Rule ID 612 // 17497 GIM_CheckFeatures, GIFBS_HasNEON, 17498 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, 17499 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 17500 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 17501 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17502 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17503 // (intrinsic_wo_chain:{ *:[v2f32] } 245:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRECPEv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) 17504 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv2f32, 17505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17507 GIR_EraseFromParent, /*InsnID*/0, 17508 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17509 // GIR_Coverage, 612, 17510 GIR_Done, 17511 // Label 1179: @41435 17512 GIM_Try, /*On fail goto*//*Label 1180*/ 41475, // Rule ID 613 // 17513 GIM_CheckFeatures, GIFBS_HasNEON, 17514 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, 17515 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 17516 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 17517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17519 // (intrinsic_wo_chain:{ *:[v4f32] } 245:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRECPEv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) 17520 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv4f32, 17521 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17522 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17523 GIR_EraseFromParent, /*InsnID*/0, 17524 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17525 // GIR_Coverage, 613, 17526 GIR_Done, 17527 // Label 1180: @41475 17528 GIM_Try, /*On fail goto*//*Label 1181*/ 41515, // Rule ID 614 // 17529 GIM_CheckFeatures, GIFBS_HasNEON, 17530 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, 17531 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 17532 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 17533 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17534 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17535 // (intrinsic_wo_chain:{ *:[v2f64] } 245:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRECPEv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) 17536 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv2f64, 17537 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17538 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17539 GIR_EraseFromParent, /*InsnID*/0, 17540 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17541 // GIR_Coverage, 614, 17542 GIR_Done, 17543 // Label 1181: @41515 17544 GIM_Try, /*On fail goto*//*Label 1182*/ 41555, // Rule ID 630 // 17545 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 17546 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, 17547 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 17548 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 17549 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17550 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17551 // (intrinsic_wo_chain:{ *:[v4f16] } 248:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FRINTNv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) 17552 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv4f16, 17553 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17554 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17555 GIR_EraseFromParent, /*InsnID*/0, 17556 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17557 // GIR_Coverage, 630, 17558 GIR_Done, 17559 // Label 1182: @41555 17560 GIM_Try, /*On fail goto*//*Label 1183*/ 41595, // Rule ID 631 // 17561 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 17562 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, 17563 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 17564 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 17565 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17566 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17567 // (intrinsic_wo_chain:{ *:[v8f16] } 248:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FRINTNv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) 17568 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv8f16, 17569 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17570 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17571 GIR_EraseFromParent, /*InsnID*/0, 17572 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17573 // GIR_Coverage, 631, 17574 GIR_Done, 17575 // Label 1183: @41595 17576 GIM_Try, /*On fail goto*//*Label 1184*/ 41635, // Rule ID 632 // 17577 GIM_CheckFeatures, GIFBS_HasNEON, 17578 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, 17579 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 17580 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 17581 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17582 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17583 // (intrinsic_wo_chain:{ *:[v2f32] } 248:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRINTNv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) 17584 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv2f32, 17585 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17586 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17587 GIR_EraseFromParent, /*InsnID*/0, 17588 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17589 // GIR_Coverage, 632, 17590 GIR_Done, 17591 // Label 1184: @41635 17592 GIM_Try, /*On fail goto*//*Label 1185*/ 41675, // Rule ID 633 // 17593 GIM_CheckFeatures, GIFBS_HasNEON, 17594 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, 17595 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 17596 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 17597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17599 // (intrinsic_wo_chain:{ *:[v4f32] } 248:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRINTNv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) 17600 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv4f32, 17601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17603 GIR_EraseFromParent, /*InsnID*/0, 17604 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17605 // GIR_Coverage, 633, 17606 GIR_Done, 17607 // Label 1185: @41675 17608 GIM_Try, /*On fail goto*//*Label 1186*/ 41715, // Rule ID 634 // 17609 GIM_CheckFeatures, GIFBS_HasNEON, 17610 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, 17611 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 17612 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 17613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17615 // (intrinsic_wo_chain:{ *:[v2f64] } 248:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRINTNv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) 17616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv2f64, 17617 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17619 GIR_EraseFromParent, /*InsnID*/0, 17620 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17621 // GIR_Coverage, 634, 17622 GIR_Done, 17623 // Label 1186: @41715 17624 GIM_Try, /*On fail goto*//*Label 1187*/ 41755, // Rule ID 650 // 17625 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 17626 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, 17627 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 17628 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 17629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17631 // (intrinsic_wo_chain:{ *:[v4f16] } 249:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FRSQRTEv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) 17632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv4f16, 17633 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17634 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17635 GIR_EraseFromParent, /*InsnID*/0, 17636 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17637 // GIR_Coverage, 650, 17638 GIR_Done, 17639 // Label 1187: @41755 17640 GIM_Try, /*On fail goto*//*Label 1188*/ 41795, // Rule ID 651 // 17641 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 17642 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, 17643 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 17644 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 17645 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17646 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17647 // (intrinsic_wo_chain:{ *:[v8f16] } 249:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FRSQRTEv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) 17648 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv8f16, 17649 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17650 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17651 GIR_EraseFromParent, /*InsnID*/0, 17652 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17653 // GIR_Coverage, 651, 17654 GIR_Done, 17655 // Label 1188: @41795 17656 GIM_Try, /*On fail goto*//*Label 1189*/ 41835, // Rule ID 652 // 17657 GIM_CheckFeatures, GIFBS_HasNEON, 17658 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, 17659 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 17660 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 17661 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17662 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17663 // (intrinsic_wo_chain:{ *:[v2f32] } 249:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRSQRTEv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) 17664 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv2f32, 17665 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17666 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17667 GIR_EraseFromParent, /*InsnID*/0, 17668 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17669 // GIR_Coverage, 652, 17670 GIR_Done, 17671 // Label 1189: @41835 17672 GIM_Try, /*On fail goto*//*Label 1190*/ 41875, // Rule ID 653 // 17673 GIM_CheckFeatures, GIFBS_HasNEON, 17674 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, 17675 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 17676 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 17677 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17678 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17679 // (intrinsic_wo_chain:{ *:[v4f32] } 249:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRSQRTEv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) 17680 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv4f32, 17681 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17682 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17683 GIR_EraseFromParent, /*InsnID*/0, 17684 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17685 // GIR_Coverage, 653, 17686 GIR_Done, 17687 // Label 1190: @41875 17688 GIM_Try, /*On fail goto*//*Label 1191*/ 41915, // Rule ID 654 // 17689 GIM_CheckFeatures, GIFBS_HasNEON, 17690 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, 17691 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 17692 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 17693 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17695 // (intrinsic_wo_chain:{ *:[v2f64] } 249:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRSQRTEv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) 17696 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv2f64, 17697 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17698 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17699 GIR_EraseFromParent, /*InsnID*/0, 17700 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17701 // GIR_Coverage, 654, 17702 GIR_Done, 17703 // Label 1191: @41915 17704 GIM_Try, /*On fail goto*//*Label 1192*/ 41955, // Rule ID 669 // 17705 GIM_CheckFeatures, GIFBS_HasNEON, 17706 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rbit, 17707 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 17708 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 17709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17711 // (intrinsic_wo_chain:{ *:[v8i8] } 267:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (RBITv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) 17712 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RBITv8i8, 17713 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17715 GIR_EraseFromParent, /*InsnID*/0, 17716 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17717 // GIR_Coverage, 669, 17718 GIR_Done, 17719 // Label 1192: @41955 17720 GIM_Try, /*On fail goto*//*Label 1193*/ 41995, // Rule ID 670 // 17721 GIM_CheckFeatures, GIFBS_HasNEON, 17722 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rbit, 17723 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 17724 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 17725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17726 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17727 // (intrinsic_wo_chain:{ *:[v16i8] } 267:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (RBITv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) 17728 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RBITv16i8, 17729 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17730 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17731 GIR_EraseFromParent, /*InsnID*/0, 17732 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17733 // GIR_Coverage, 670, 17734 GIR_Done, 17735 // Label 1193: @41995 17736 GIM_Try, /*On fail goto*//*Label 1194*/ 42035, // Rule ID 689 // 17737 GIM_CheckFeatures, GIFBS_HasNEON, 17738 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, 17739 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 17740 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 17741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17742 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17743 // (intrinsic_wo_chain:{ *:[v4i16] } 271:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn) 17744 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv8i8_v4i16, 17745 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17747 GIR_EraseFromParent, /*InsnID*/0, 17748 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17749 // GIR_Coverage, 689, 17750 GIR_Done, 17751 // Label 1194: @42035 17752 GIM_Try, /*On fail goto*//*Label 1195*/ 42075, // Rule ID 690 // 17753 GIM_CheckFeatures, GIFBS_HasNEON, 17754 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, 17755 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 17756 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 17757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17759 // (intrinsic_wo_chain:{ *:[v8i16] } 271:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn) 17760 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv16i8_v8i16, 17761 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17762 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17763 GIR_EraseFromParent, /*InsnID*/0, 17764 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17765 // GIR_Coverage, 690, 17766 GIR_Done, 17767 // Label 1195: @42075 17768 GIM_Try, /*On fail goto*//*Label 1196*/ 42115, // Rule ID 691 // 17769 GIM_CheckFeatures, GIFBS_HasNEON, 17770 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, 17771 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 17772 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 17773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17775 // (intrinsic_wo_chain:{ *:[v2i32] } 271:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (SADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn) 17776 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv4i16_v2i32, 17777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17778 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17779 GIR_EraseFromParent, /*InsnID*/0, 17780 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17781 // GIR_Coverage, 691, 17782 GIR_Done, 17783 // Label 1196: @42115 17784 GIM_Try, /*On fail goto*//*Label 1197*/ 42155, // Rule ID 692 // 17785 GIM_CheckFeatures, GIFBS_HasNEON, 17786 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, 17787 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 17788 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 17789 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17790 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17791 // (intrinsic_wo_chain:{ *:[v4i32] } 271:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn) 17792 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv8i16_v4i32, 17793 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17794 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17795 GIR_EraseFromParent, /*InsnID*/0, 17796 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17797 // GIR_Coverage, 692, 17798 GIR_Done, 17799 // Label 1197: @42155 17800 GIM_Try, /*On fail goto*//*Label 1198*/ 42195, // Rule ID 693 // 17801 GIM_CheckFeatures, GIFBS_HasNEON, 17802 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, 17803 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 17804 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 17805 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17806 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17807 // (intrinsic_wo_chain:{ *:[v1i64] } 271:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (SADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn) 17808 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv2i32_v1i64, 17809 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17810 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17811 GIR_EraseFromParent, /*InsnID*/0, 17812 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17813 // GIR_Coverage, 693, 17814 GIR_Done, 17815 // Label 1198: @42195 17816 GIM_Try, /*On fail goto*//*Label 1199*/ 42235, // Rule ID 694 // 17817 GIM_CheckFeatures, GIFBS_HasNEON, 17818 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, 17819 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 17820 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 17821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17822 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17823 // (intrinsic_wo_chain:{ *:[v2i64] } 271:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn) 17824 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv4i32_v2i64, 17825 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17826 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17827 GIR_EraseFromParent, /*InsnID*/0, 17828 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17829 // GIR_Coverage, 694, 17830 GIR_Done, 17831 // Label 1199: @42235 17832 GIM_Try, /*On fail goto*//*Label 1200*/ 42275, // Rule ID 700 // 17833 GIM_CheckFeatures, GIFBS_HasNEON, 17834 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, 17835 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 17836 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 17837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17838 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17839 // (intrinsic_wo_chain:{ *:[v8i8] } 288:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SQABSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) 17840 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv8i8, 17841 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17842 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17843 GIR_EraseFromParent, /*InsnID*/0, 17844 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17845 // GIR_Coverage, 700, 17846 GIR_Done, 17847 // Label 1200: @42275 17848 GIM_Try, /*On fail goto*//*Label 1201*/ 42315, // Rule ID 701 // 17849 GIM_CheckFeatures, GIFBS_HasNEON, 17850 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, 17851 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 17852 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 17853 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17854 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17855 // (intrinsic_wo_chain:{ *:[v16i8] } 288:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SQABSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) 17856 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv16i8, 17857 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17859 GIR_EraseFromParent, /*InsnID*/0, 17860 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17861 // GIR_Coverage, 701, 17862 GIR_Done, 17863 // Label 1201: @42315 17864 GIM_Try, /*On fail goto*//*Label 1202*/ 42355, // Rule ID 702 // 17865 GIM_CheckFeatures, GIFBS_HasNEON, 17866 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, 17867 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 17868 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 17869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17871 // (intrinsic_wo_chain:{ *:[v4i16] } 288:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (SQABSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) 17872 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv4i16, 17873 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17874 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17875 GIR_EraseFromParent, /*InsnID*/0, 17876 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17877 // GIR_Coverage, 702, 17878 GIR_Done, 17879 // Label 1202: @42355 17880 GIM_Try, /*On fail goto*//*Label 1203*/ 42395, // Rule ID 703 // 17881 GIM_CheckFeatures, GIFBS_HasNEON, 17882 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, 17883 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 17884 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 17885 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17887 // (intrinsic_wo_chain:{ *:[v8i16] } 288:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQABSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) 17888 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv8i16, 17889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17891 GIR_EraseFromParent, /*InsnID*/0, 17892 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17893 // GIR_Coverage, 703, 17894 GIR_Done, 17895 // Label 1203: @42395 17896 GIM_Try, /*On fail goto*//*Label 1204*/ 42435, // Rule ID 704 // 17897 GIM_CheckFeatures, GIFBS_HasNEON, 17898 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, 17899 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 17900 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 17901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17903 // (intrinsic_wo_chain:{ *:[v2i32] } 288:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (SQABSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) 17904 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv2i32, 17905 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17907 GIR_EraseFromParent, /*InsnID*/0, 17908 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17909 // GIR_Coverage, 704, 17910 GIR_Done, 17911 // Label 1204: @42435 17912 GIM_Try, /*On fail goto*//*Label 1205*/ 42475, // Rule ID 705 // 17913 GIM_CheckFeatures, GIFBS_HasNEON, 17914 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, 17915 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 17916 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 17917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17919 // (intrinsic_wo_chain:{ *:[v4i32] } 288:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQABSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) 17920 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv4i32, 17921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17922 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17923 GIR_EraseFromParent, /*InsnID*/0, 17924 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17925 // GIR_Coverage, 705, 17926 GIR_Done, 17927 // Label 1205: @42475 17928 GIM_Try, /*On fail goto*//*Label 1206*/ 42515, // Rule ID 706 // 17929 GIM_CheckFeatures, GIFBS_HasNEON, 17930 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, 17931 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 17932 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 17933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17935 // (intrinsic_wo_chain:{ *:[v2i64] } 288:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQABSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) 17936 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv2i64, 17937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17939 GIR_EraseFromParent, /*InsnID*/0, 17940 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17941 // GIR_Coverage, 706, 17942 GIR_Done, 17943 // Label 1206: @42515 17944 GIM_Try, /*On fail goto*//*Label 1207*/ 42555, // Rule ID 707 // 17945 GIM_CheckFeatures, GIFBS_HasNEON, 17946 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, 17947 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 17948 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 17949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17950 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17951 // (intrinsic_wo_chain:{ *:[v8i8] } 293:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SQNEGv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) 17952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv8i8, 17953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17954 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17955 GIR_EraseFromParent, /*InsnID*/0, 17956 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17957 // GIR_Coverage, 707, 17958 GIR_Done, 17959 // Label 1207: @42555 17960 GIM_Try, /*On fail goto*//*Label 1208*/ 42595, // Rule ID 708 // 17961 GIM_CheckFeatures, GIFBS_HasNEON, 17962 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, 17963 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 17964 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 17965 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17967 // (intrinsic_wo_chain:{ *:[v16i8] } 293:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SQNEGv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) 17968 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv16i8, 17969 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17971 GIR_EraseFromParent, /*InsnID*/0, 17972 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17973 // GIR_Coverage, 708, 17974 GIR_Done, 17975 // Label 1208: @42595 17976 GIM_Try, /*On fail goto*//*Label 1209*/ 42635, // Rule ID 709 // 17977 GIM_CheckFeatures, GIFBS_HasNEON, 17978 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, 17979 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 17980 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 17981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 17982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 17983 // (intrinsic_wo_chain:{ *:[v4i16] } 293:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (SQNEGv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) 17984 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv4i16, 17985 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 17986 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 17987 GIR_EraseFromParent, /*InsnID*/0, 17988 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17989 // GIR_Coverage, 709, 17990 GIR_Done, 17991 // Label 1209: @42635 17992 GIM_Try, /*On fail goto*//*Label 1210*/ 42675, // Rule ID 710 // 17993 GIM_CheckFeatures, GIFBS_HasNEON, 17994 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, 17995 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 17996 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 17997 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 17998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 17999 // (intrinsic_wo_chain:{ *:[v8i16] } 293:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQNEGv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) 18000 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv8i16, 18001 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18002 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18003 GIR_EraseFromParent, /*InsnID*/0, 18004 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18005 // GIR_Coverage, 710, 18006 GIR_Done, 18007 // Label 1210: @42675 18008 GIM_Try, /*On fail goto*//*Label 1211*/ 42715, // Rule ID 711 // 18009 GIM_CheckFeatures, GIFBS_HasNEON, 18010 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, 18011 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 18012 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 18013 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18014 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18015 // (intrinsic_wo_chain:{ *:[v2i32] } 293:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (SQNEGv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) 18016 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv2i32, 18017 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18018 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18019 GIR_EraseFromParent, /*InsnID*/0, 18020 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18021 // GIR_Coverage, 711, 18022 GIR_Done, 18023 // Label 1211: @42715 18024 GIM_Try, /*On fail goto*//*Label 1212*/ 42755, // Rule ID 712 // 18025 GIM_CheckFeatures, GIFBS_HasNEON, 18026 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, 18027 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 18028 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 18029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 18030 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18031 // (intrinsic_wo_chain:{ *:[v4i32] } 293:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQNEGv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) 18032 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv4i32, 18033 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18034 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18035 GIR_EraseFromParent, /*InsnID*/0, 18036 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18037 // GIR_Coverage, 712, 18038 GIR_Done, 18039 // Label 1212: @42755 18040 GIM_Try, /*On fail goto*//*Label 1213*/ 42795, // Rule ID 713 // 18041 GIM_CheckFeatures, GIFBS_HasNEON, 18042 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, 18043 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 18044 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 18045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 18046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18047 // (intrinsic_wo_chain:{ *:[v2i64] } 293:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQNEGv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) 18048 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv2i64, 18049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18051 GIR_EraseFromParent, /*InsnID*/0, 18052 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18053 // GIR_Coverage, 713, 18054 GIR_Done, 18055 // Label 1213: @42795 18056 GIM_Try, /*On fail goto*//*Label 1214*/ 42835, // Rule ID 714 // 18057 GIM_CheckFeatures, GIFBS_HasNEON, 18058 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, 18059 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 18060 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 18061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18063 // (intrinsic_wo_chain:{ *:[v8i8] } 303:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQXTNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) 18064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv8i8, 18065 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18066 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18067 GIR_EraseFromParent, /*InsnID*/0, 18068 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18069 // GIR_Coverage, 714, 18070 GIR_Done, 18071 // Label 1214: @42835 18072 GIM_Try, /*On fail goto*//*Label 1215*/ 42875, // Rule ID 715 // 18073 GIM_CheckFeatures, GIFBS_HasNEON, 18074 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, 18075 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 18076 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 18077 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18079 // (intrinsic_wo_chain:{ *:[v4i16] } 303:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQXTNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) 18080 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv4i16, 18081 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18083 GIR_EraseFromParent, /*InsnID*/0, 18084 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18085 // GIR_Coverage, 715, 18086 GIR_Done, 18087 // Label 1215: @42875 18088 GIM_Try, /*On fail goto*//*Label 1216*/ 42915, // Rule ID 716 // 18089 GIM_CheckFeatures, GIFBS_HasNEON, 18090 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, 18091 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 18092 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 18093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18095 // (intrinsic_wo_chain:{ *:[v2i32] } 303:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQXTNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) 18096 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv2i32, 18097 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18098 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18099 GIR_EraseFromParent, /*InsnID*/0, 18100 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18101 // GIR_Coverage, 716, 18102 GIR_Done, 18103 // Label 1216: @42915 18104 GIM_Try, /*On fail goto*//*Label 1217*/ 42955, // Rule ID 717 // 18105 GIM_CheckFeatures, GIFBS_HasNEON, 18106 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, 18107 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 18108 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 18109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18111 // (intrinsic_wo_chain:{ *:[v8i8] } 304:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQXTUNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) 18112 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv8i8, 18113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18114 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18115 GIR_EraseFromParent, /*InsnID*/0, 18116 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18117 // GIR_Coverage, 717, 18118 GIR_Done, 18119 // Label 1217: @42955 18120 GIM_Try, /*On fail goto*//*Label 1218*/ 42995, // Rule ID 718 // 18121 GIM_CheckFeatures, GIFBS_HasNEON, 18122 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, 18123 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 18124 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 18125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18127 // (intrinsic_wo_chain:{ *:[v4i16] } 304:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQXTUNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) 18128 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv4i16, 18129 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18130 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18131 GIR_EraseFromParent, /*InsnID*/0, 18132 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18133 // GIR_Coverage, 718, 18134 GIR_Done, 18135 // Label 1218: @42995 18136 GIM_Try, /*On fail goto*//*Label 1219*/ 43035, // Rule ID 719 // 18137 GIM_CheckFeatures, GIFBS_HasNEON, 18138 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, 18139 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 18140 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 18141 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18142 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18143 // (intrinsic_wo_chain:{ *:[v2i32] } 304:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQXTUNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) 18144 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv2i32, 18145 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18146 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18147 GIR_EraseFromParent, /*InsnID*/0, 18148 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18149 // GIR_Coverage, 719, 18150 GIR_Done, 18151 // Label 1219: @43035 18152 GIM_Try, /*On fail goto*//*Label 1220*/ 43075, // Rule ID 733 // 18153 GIM_CheckFeatures, GIFBS_HasNEON, 18154 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, 18155 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 18156 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 18157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18159 // (intrinsic_wo_chain:{ *:[v4i16] } 329:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (UADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn) 18160 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv8i8_v4i16, 18161 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18163 GIR_EraseFromParent, /*InsnID*/0, 18164 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18165 // GIR_Coverage, 733, 18166 GIR_Done, 18167 // Label 1220: @43075 18168 GIM_Try, /*On fail goto*//*Label 1221*/ 43115, // Rule ID 734 // 18169 GIM_CheckFeatures, GIFBS_HasNEON, 18170 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, 18171 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 18172 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 18173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 18174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18175 // (intrinsic_wo_chain:{ *:[v8i16] } 329:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (UADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn) 18176 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv16i8_v8i16, 18177 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18178 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18179 GIR_EraseFromParent, /*InsnID*/0, 18180 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18181 // GIR_Coverage, 734, 18182 GIR_Done, 18183 // Label 1221: @43115 18184 GIM_Try, /*On fail goto*//*Label 1222*/ 43155, // Rule ID 735 // 18185 GIM_CheckFeatures, GIFBS_HasNEON, 18186 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, 18187 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 18188 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 18189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18190 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18191 // (intrinsic_wo_chain:{ *:[v2i32] } 329:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (UADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn) 18192 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv4i16_v2i32, 18193 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18194 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18195 GIR_EraseFromParent, /*InsnID*/0, 18196 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18197 // GIR_Coverage, 735, 18198 GIR_Done, 18199 // Label 1222: @43155 18200 GIM_Try, /*On fail goto*//*Label 1223*/ 43195, // Rule ID 736 // 18201 GIM_CheckFeatures, GIFBS_HasNEON, 18202 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, 18203 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 18204 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 18205 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 18206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18207 // (intrinsic_wo_chain:{ *:[v4i32] } 329:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (UADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn) 18208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv8i16_v4i32, 18209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18211 GIR_EraseFromParent, /*InsnID*/0, 18212 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18213 // GIR_Coverage, 736, 18214 GIR_Done, 18215 // Label 1223: @43195 18216 GIM_Try, /*On fail goto*//*Label 1224*/ 43235, // Rule ID 737 // 18217 GIM_CheckFeatures, GIFBS_HasNEON, 18218 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, 18219 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 18220 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 18221 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18222 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18223 // (intrinsic_wo_chain:{ *:[v1i64] } 329:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (UADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn) 18224 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv2i32_v1i64, 18225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18226 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18227 GIR_EraseFromParent, /*InsnID*/0, 18228 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18229 // GIR_Coverage, 737, 18230 GIR_Done, 18231 // Label 1224: @43235 18232 GIM_Try, /*On fail goto*//*Label 1225*/ 43275, // Rule ID 738 // 18233 GIM_CheckFeatures, GIFBS_HasNEON, 18234 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, 18235 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 18236 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 18237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 18238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18239 // (intrinsic_wo_chain:{ *:[v2i64] } 329:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (UADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn) 18240 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv4i32_v2i64, 18241 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18242 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18243 GIR_EraseFromParent, /*InsnID*/0, 18244 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18245 // GIR_Coverage, 738, 18246 GIR_Done, 18247 // Label 1225: @43275 18248 GIM_Try, /*On fail goto*//*Label 1226*/ 43315, // Rule ID 744 // 18249 GIM_CheckFeatures, GIFBS_HasNEON, 18250 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, 18251 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 18252 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 18253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18255 // (intrinsic_wo_chain:{ *:[v8i8] } 348:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (UQXTNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) 18256 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv8i8, 18257 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18258 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18259 GIR_EraseFromParent, /*InsnID*/0, 18260 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18261 // GIR_Coverage, 744, 18262 GIR_Done, 18263 // Label 1226: @43315 18264 GIM_Try, /*On fail goto*//*Label 1227*/ 43355, // Rule ID 745 // 18265 GIM_CheckFeatures, GIFBS_HasNEON, 18266 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, 18267 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 18268 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 18269 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18270 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18271 // (intrinsic_wo_chain:{ *:[v4i16] } 348:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (UQXTNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) 18272 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv4i16, 18273 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18274 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18275 GIR_EraseFromParent, /*InsnID*/0, 18276 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18277 // GIR_Coverage, 745, 18278 GIR_Done, 18279 // Label 1227: @43355 18280 GIM_Try, /*On fail goto*//*Label 1228*/ 43395, // Rule ID 746 // 18281 GIM_CheckFeatures, GIFBS_HasNEON, 18282 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, 18283 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 18284 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 18285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18287 // (intrinsic_wo_chain:{ *:[v2i32] } 348:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (UQXTNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) 18288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv2i32, 18289 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18290 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18291 GIR_EraseFromParent, /*InsnID*/0, 18292 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18293 // GIR_Coverage, 746, 18294 GIR_Done, 18295 // Label 1228: @43395 18296 GIM_Try, /*On fail goto*//*Label 1229*/ 43435, // Rule ID 747 // 18297 GIM_CheckFeatures, GIFBS_HasNEON, 18298 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urecpe, 18299 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 18300 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 18301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18303 // (intrinsic_wo_chain:{ *:[v2i32] } 349:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (URECPEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) 18304 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URECPEv2i32, 18305 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18306 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18307 GIR_EraseFromParent, /*InsnID*/0, 18308 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18309 // GIR_Coverage, 747, 18310 GIR_Done, 18311 // Label 1229: @43435 18312 GIM_Try, /*On fail goto*//*Label 1230*/ 43475, // Rule ID 748 // 18313 GIM_CheckFeatures, GIFBS_HasNEON, 18314 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urecpe, 18315 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 18316 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 18317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 18318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18319 // (intrinsic_wo_chain:{ *:[v4i32] } 349:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (URECPEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) 18320 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URECPEv4i32, 18321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18322 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18323 GIR_EraseFromParent, /*InsnID*/0, 18324 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18325 // GIR_Coverage, 748, 18326 GIR_Done, 18327 // Label 1230: @43475 18328 GIM_Try, /*On fail goto*//*Label 1231*/ 43515, // Rule ID 749 // 18329 GIM_CheckFeatures, GIFBS_HasNEON, 18330 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ursqrte, 18331 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 18332 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 18333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18335 // (intrinsic_wo_chain:{ *:[v2i32] } 352:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (URSQRTEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) 18336 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSQRTEv2i32, 18337 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18338 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18339 GIR_EraseFromParent, /*InsnID*/0, 18340 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18341 // GIR_Coverage, 749, 18342 GIR_Done, 18343 // Label 1231: @43515 18344 GIM_Try, /*On fail goto*//*Label 1232*/ 43555, // Rule ID 750 // 18345 GIM_CheckFeatures, GIFBS_HasNEON, 18346 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ursqrte, 18347 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 18348 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 18349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 18350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18351 // (intrinsic_wo_chain:{ *:[v4i32] } 352:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (URSQRTEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) 18352 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSQRTEv4i32, 18353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18355 GIR_EraseFromParent, /*InsnID*/0, 18356 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18357 // GIR_Coverage, 750, 18358 GIR_Done, 18359 // Label 1232: @43555 18360 GIM_Try, /*On fail goto*//*Label 1233*/ 43595, // Rule ID 1232 // 18361 GIM_CheckFeatures, GIFBS_HasNEON, 18362 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fcvtxn, 18363 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 18364 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 18366 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18367 // (intrinsic_wo_chain:{ *:[f32] } 367:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTXNv1i64:{ *:[f32] } FPR64:{ *:[f64] }:$Rn) 18368 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTXNv1i64, 18369 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18370 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18371 GIR_EraseFromParent, /*InsnID*/0, 18372 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18373 // GIR_Coverage, 1232, 18374 GIR_Done, 18375 // Label 1233: @43595 18376 GIM_Try, /*On fail goto*//*Label 1234*/ 43635, // Rule ID 1237 // 18377 GIM_CheckFeatures, GIFBS_HasNEON, 18378 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, 18379 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 18380 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18383 // (intrinsic_wo_chain:{ *:[i64] } 288:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn) => (SQABSv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn) 18384 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv1i64, 18385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18386 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18387 GIR_EraseFromParent, /*InsnID*/0, 18388 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18389 // GIR_Coverage, 1237, 18390 GIR_Done, 18391 // Label 1234: @43635 18392 GIM_Try, /*On fail goto*//*Label 1235*/ 43675, // Rule ID 1238 // 18393 GIM_CheckFeatures, GIFBS_HasNEON, 18394 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, 18395 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 18396 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 18397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 18398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 18399 // (intrinsic_wo_chain:{ *:[i32] } 288:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn) => (SQABSv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn) 18400 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv1i32, 18401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18403 GIR_EraseFromParent, /*InsnID*/0, 18404 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18405 // GIR_Coverage, 1238, 18406 GIR_Done, 18407 // Label 1235: @43675 18408 GIM_Try, /*On fail goto*//*Label 1236*/ 43715, // Rule ID 1239 // 18409 GIM_CheckFeatures, GIFBS_HasNEON, 18410 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, 18411 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 18412 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18415 // (intrinsic_wo_chain:{ *:[i64] } 293:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn) => (SQNEGv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn) 18416 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv1i64, 18417 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18418 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18419 GIR_EraseFromParent, /*InsnID*/0, 18420 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18421 // GIR_Coverage, 1239, 18422 GIR_Done, 18423 // Label 1236: @43715 18424 GIM_Try, /*On fail goto*//*Label 1237*/ 43755, // Rule ID 1240 // 18425 GIM_CheckFeatures, GIFBS_HasNEON, 18426 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, 18427 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 18428 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 18429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 18430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 18431 // (intrinsic_wo_chain:{ *:[i32] } 293:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn) => (SQNEGv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn) 18432 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv1i32, 18433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18435 GIR_EraseFromParent, /*InsnID*/0, 18436 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18437 // GIR_Coverage, 1240, 18438 GIR_Done, 18439 // Label 1237: @43755 18440 GIM_Try, /*On fail goto*//*Label 1238*/ 43795, // Rule ID 1241 // 18441 GIM_CheckFeatures, GIFBS_HasNEON, 18442 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_scalar_sqxtn, 18443 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 18444 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 18446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18447 // (intrinsic_wo_chain:{ *:[i32] } 274:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn) => (SQXTNv1i32:{ *:[i32] } FPR64:{ *:[i64] }:$Rn) 18448 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv1i32, 18449 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18450 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18451 GIR_EraseFromParent, /*InsnID*/0, 18452 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18453 // GIR_Coverage, 1241, 18454 GIR_Done, 18455 // Label 1238: @43795 18456 GIM_Try, /*On fail goto*//*Label 1239*/ 43835, // Rule ID 1242 // 18457 GIM_CheckFeatures, GIFBS_HasNEON, 18458 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_scalar_sqxtun, 18459 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 18460 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18461 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 18462 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18463 // (intrinsic_wo_chain:{ *:[i32] } 275:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn) => (SQXTUNv1i32:{ *:[i32] } FPR64:{ *:[i64] }:$Rn) 18464 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv1i32, 18465 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18466 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18467 GIR_EraseFromParent, /*InsnID*/0, 18468 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18469 // GIR_Coverage, 1242, 18470 GIR_Done, 18471 // Label 1239: @43835 18472 GIM_Try, /*On fail goto*//*Label 1240*/ 43875, // Rule ID 1248 // 18473 GIM_CheckFeatures, GIFBS_HasNEON, 18474 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_scalar_uqxtn, 18475 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 18476 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 18478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18479 // (intrinsic_wo_chain:{ *:[i32] } 276:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn) => (UQXTNv1i32:{ *:[i32] } FPR64:{ *:[i64] }:$Rn) 18480 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv1i32, 18481 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18482 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18483 GIR_EraseFromParent, /*InsnID*/0, 18484 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18485 // GIR_Coverage, 1248, 18486 GIR_Done, 18487 // Label 1240: @43875 18488 GIM_Try, /*On fail goto*//*Label 1241*/ 43915, // Rule ID 1448 // 18489 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 18490 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, 18491 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 18492 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 18493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 18494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18495 // (intrinsic_wo_chain:{ *:[f16] } 235:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMAXNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) 18496 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMVv4i16v, 18497 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18498 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18499 GIR_EraseFromParent, /*InsnID*/0, 18500 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18501 // GIR_Coverage, 1448, 18502 GIR_Done, 18503 // Label 1241: @43915 18504 GIM_Try, /*On fail goto*//*Label 1242*/ 43955, // Rule ID 1449 // 18505 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 18506 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, 18507 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 18508 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 18509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 18510 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18511 // (intrinsic_wo_chain:{ *:[f16] } 235:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMAXNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) 18512 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMVv8i16v, 18513 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18514 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18515 GIR_EraseFromParent, /*InsnID*/0, 18516 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18517 // GIR_Coverage, 1449, 18518 GIR_Done, 18519 // Label 1242: @43955 18520 GIM_Try, /*On fail goto*//*Label 1243*/ 43995, // Rule ID 1450 // 18521 GIM_CheckFeatures, GIFBS_HasNEON, 18522 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, 18523 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 18524 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 18525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 18526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18527 // (intrinsic_wo_chain:{ *:[f32] } 235:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMAXNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) 18528 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMVv4i32v, 18529 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18530 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18531 GIR_EraseFromParent, /*InsnID*/0, 18532 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18533 // GIR_Coverage, 1450, 18534 GIR_Done, 18535 // Label 1243: @43995 18536 GIM_Try, /*On fail goto*//*Label 1244*/ 44035, // Rule ID 1451 // 18537 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 18538 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, 18539 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 18540 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 18541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 18542 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18543 // (intrinsic_wo_chain:{ *:[f16] } 237:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMAXVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) 18544 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXVv4i16v, 18545 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18546 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18547 GIR_EraseFromParent, /*InsnID*/0, 18548 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18549 // GIR_Coverage, 1451, 18550 GIR_Done, 18551 // Label 1244: @44035 18552 GIM_Try, /*On fail goto*//*Label 1245*/ 44075, // Rule ID 1452 // 18553 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 18554 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, 18555 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 18556 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 18557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 18558 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18559 // (intrinsic_wo_chain:{ *:[f16] } 237:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMAXVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) 18560 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXVv8i16v, 18561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18563 GIR_EraseFromParent, /*InsnID*/0, 18564 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18565 // GIR_Coverage, 1452, 18566 GIR_Done, 18567 // Label 1245: @44075 18568 GIM_Try, /*On fail goto*//*Label 1246*/ 44115, // Rule ID 1453 // 18569 GIM_CheckFeatures, GIFBS_HasNEON, 18570 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, 18571 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 18572 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 18573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 18574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18575 // (intrinsic_wo_chain:{ *:[f32] } 237:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMAXVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) 18576 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXVv4i32v, 18577 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18578 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18579 GIR_EraseFromParent, /*InsnID*/0, 18580 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18581 // GIR_Coverage, 1453, 18582 GIR_Done, 18583 // Label 1246: @44115 18584 GIM_Try, /*On fail goto*//*Label 1247*/ 44155, // Rule ID 1454 // 18585 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 18586 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, 18587 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 18588 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 18589 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 18590 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18591 // (intrinsic_wo_chain:{ *:[f16] } 241:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMINNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) 18592 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMVv4i16v, 18593 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18594 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18595 GIR_EraseFromParent, /*InsnID*/0, 18596 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18597 // GIR_Coverage, 1454, 18598 GIR_Done, 18599 // Label 1247: @44155 18600 GIM_Try, /*On fail goto*//*Label 1248*/ 44195, // Rule ID 1455 // 18601 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 18602 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, 18603 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 18604 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 18605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 18606 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18607 // (intrinsic_wo_chain:{ *:[f16] } 241:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMINNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) 18608 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMVv8i16v, 18609 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18610 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18611 GIR_EraseFromParent, /*InsnID*/0, 18612 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18613 // GIR_Coverage, 1455, 18614 GIR_Done, 18615 // Label 1248: @44195 18616 GIM_Try, /*On fail goto*//*Label 1249*/ 44235, // Rule ID 1456 // 18617 GIM_CheckFeatures, GIFBS_HasNEON, 18618 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, 18619 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 18620 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 18621 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 18622 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18623 // (intrinsic_wo_chain:{ *:[f32] } 241:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMINNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) 18624 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMVv4i32v, 18625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18626 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18627 GIR_EraseFromParent, /*InsnID*/0, 18628 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18629 // GIR_Coverage, 1456, 18630 GIR_Done, 18631 // Label 1249: @44235 18632 GIM_Try, /*On fail goto*//*Label 1250*/ 44275, // Rule ID 1457 // 18633 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 18634 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, 18635 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 18636 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 18637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 18638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18639 // (intrinsic_wo_chain:{ *:[f16] } 243:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMINVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) 18640 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINVv4i16v, 18641 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18642 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18643 GIR_EraseFromParent, /*InsnID*/0, 18644 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18645 // GIR_Coverage, 1457, 18646 GIR_Done, 18647 // Label 1250: @44275 18648 GIM_Try, /*On fail goto*//*Label 1251*/ 44315, // Rule ID 1458 // 18649 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 18650 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, 18651 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 18652 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 18653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 18654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18655 // (intrinsic_wo_chain:{ *:[f16] } 243:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMINVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) 18656 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINVv8i16v, 18657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18659 GIR_EraseFromParent, /*InsnID*/0, 18660 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18661 // GIR_Coverage, 1458, 18662 GIR_Done, 18663 // Label 1251: @44315 18664 GIM_Try, /*On fail goto*//*Label 1252*/ 44355, // Rule ID 1459 // 18665 GIM_CheckFeatures, GIFBS_HasNEON, 18666 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, 18667 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 18668 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 18669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 18670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18671 // (intrinsic_wo_chain:{ *:[f32] } 243:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMINVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) 18672 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINVv4i32v, 18673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18675 GIR_EraseFromParent, /*InsnID*/0, 18676 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18677 // GIR_Coverage, 1459, 18678 GIR_Done, 18679 // Label 1252: @44355 18680 GIM_Try, /*On fail goto*//*Label 1253*/ 44395, // Rule ID 1744 // 18681 GIM_CheckFeatures, GIFBS_HasAES, 18682 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesmc, 18683 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 18684 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 18685 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 18686 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18687 // (intrinsic_wo_chain:{ *:[v16i8] } 193:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (AESMCrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) 18688 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESMCrr, 18689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18690 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18691 GIR_EraseFromParent, /*InsnID*/0, 18692 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18693 // GIR_Coverage, 1744, 18694 GIR_Done, 18695 // Label 1253: @44395 18696 GIM_Try, /*On fail goto*//*Label 1254*/ 44435, // Rule ID 1745 // 18697 GIM_CheckFeatures, GIFBS_HasAES, 18698 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesimc, 18699 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 18700 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 18701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 18702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18703 // (intrinsic_wo_chain:{ *:[v16i8] } 192:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (AESIMCrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) 18704 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESIMCrr, 18705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18706 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18707 GIR_EraseFromParent, /*InsnID*/0, 18708 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18709 // GIR_Coverage, 1745, 18710 GIR_Done, 18711 // Label 1254: @44435 18712 GIM_Try, /*On fail goto*//*Label 1255*/ 44475, // Rule ID 1753 // 18713 GIM_CheckFeatures, GIFBS_HasSHA2, 18714 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1h, 18715 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 18716 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 18717 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 18718 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 18719 // (intrinsic_wo_chain:{ *:[i32] } 195:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn) => (SHA1Hrr:{ *:[i32] } FPR32:{ *:[i32] }:$Rn) 18720 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Hrr, 18721 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18722 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18723 GIR_EraseFromParent, /*InsnID*/0, 18724 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18725 // GIR_Coverage, 1753, 18726 GIR_Done, 18727 // Label 1255: @44475 18728 GIM_Try, /*On fail goto*//*Label 1256*/ 44515, // Rule ID 1796 // 18729 GIM_CheckFeatures, GIFBS_HasNEON, 18730 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, 18731 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 18732 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18735 // (intrinsic_wo_chain:{ *:[v1i64] } 288:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn) => (SQABSv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn) 18736 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv1i64, 18737 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18738 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18739 GIR_EraseFromParent, /*InsnID*/0, 18740 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18741 // GIR_Coverage, 1796, 18742 GIR_Done, 18743 // Label 1256: @44515 18744 GIM_Try, /*On fail goto*//*Label 1257*/ 44553, // Rule ID 2266 // 18745 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, 18746 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 18747 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18748 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18750 // (intrinsic_wo_chain:{ *:[v1f64] } 248:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FRINTNDr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn) 18751 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNDr, 18752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18754 GIR_EraseFromParent, /*InsnID*/0, 18755 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18756 // GIR_Coverage, 2266, 18757 GIR_Done, 18758 // Label 1257: @44553 18759 GIM_Try, /*On fail goto*//*Label 1258*/ 44591, // Rule ID 2285 // 18760 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvthf2fp, 18761 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 18762 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 18763 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 18764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18765 // (intrinsic_wo_chain:{ *:[v4f32] } 362:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (FCVTLv4i16:{ *:[v4f32] } V64:{ *:[v4i16] }:$Rn) 18766 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTLv4i16, 18767 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18768 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18769 GIR_EraseFromParent, /*InsnID*/0, 18770 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18771 // GIR_Coverage, 2285, 18772 GIR_Done, 18773 // Label 1258: @44591 18774 GIM_Try, /*On fail goto*//*Label 1259*/ 44629, // Rule ID 2291 // 18775 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2hf, 18776 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 18777 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 18778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 18780 // (intrinsic_wo_chain:{ *:[v4i16] } 359:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTNv4i16:{ *:[v4i16] } V128:{ *:[v4f32] }:$Rn) 18781 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNv4i16, 18782 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18783 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18784 GIR_EraseFromParent, /*InsnID*/0, 18785 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18786 // GIR_Coverage, 2291, 18787 GIR_Done, 18788 // Label 1259: @44629 18789 GIM_Try, /*On fail goto*//*Label 1260*/ 44669, // Rule ID 2443 // 18790 GIM_CheckFeatures, GIFBS_HasNEON, 18791 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, 18792 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 18793 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18796 // (intrinsic_wo_chain:{ *:[v1i64] } 293:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn) => (SQNEGv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn) 18797 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv1i64, 18798 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18800 GIR_EraseFromParent, /*InsnID*/0, 18801 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18802 // GIR_Coverage, 2443, 18803 GIR_Done, 18804 // Label 1260: @44669 18805 GIM_Try, /*On fail goto*//*Label 1261*/ 44707, // Rule ID 2446 // 18806 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, 18807 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 18808 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18809 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18811 // (intrinsic_wo_chain:{ *:[v1i64] } 221:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTASv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) 18812 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv1i64, 18813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18814 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18815 GIR_EraseFromParent, /*InsnID*/0, 18816 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18817 // GIR_Coverage, 2446, 18818 GIR_Done, 18819 // Label 1261: @44707 18820 GIM_Try, /*On fail goto*//*Label 1262*/ 44745, // Rule ID 2447 // 18821 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, 18822 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 18823 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18824 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18825 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18826 // (intrinsic_wo_chain:{ *:[v1i64] } 222:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTAUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) 18827 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv1i64, 18828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18829 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18830 GIR_EraseFromParent, /*InsnID*/0, 18831 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18832 // GIR_Coverage, 2447, 18833 GIR_Done, 18834 // Label 1262: @44745 18835 GIM_Try, /*On fail goto*//*Label 1263*/ 44783, // Rule ID 2448 // 18836 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, 18837 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 18838 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18839 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18840 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18841 // (intrinsic_wo_chain:{ *:[v1i64] } 223:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTMSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) 18842 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv1i64, 18843 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18844 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18845 GIR_EraseFromParent, /*InsnID*/0, 18846 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18847 // GIR_Coverage, 2448, 18848 GIR_Done, 18849 // Label 1263: @44783 18850 GIM_Try, /*On fail goto*//*Label 1264*/ 44821, // Rule ID 2449 // 18851 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, 18852 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 18853 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18854 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18855 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18856 // (intrinsic_wo_chain:{ *:[v1i64] } 224:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTMUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) 18857 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv1i64, 18858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18860 GIR_EraseFromParent, /*InsnID*/0, 18861 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18862 // GIR_Coverage, 2449, 18863 GIR_Done, 18864 // Label 1264: @44821 18865 GIM_Try, /*On fail goto*//*Label 1265*/ 44859, // Rule ID 2450 // 18866 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, 18867 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 18868 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18871 // (intrinsic_wo_chain:{ *:[v1i64] } 225:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTNSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) 18872 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv1i64, 18873 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18874 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18875 GIR_EraseFromParent, /*InsnID*/0, 18876 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18877 // GIR_Coverage, 2450, 18878 GIR_Done, 18879 // Label 1265: @44859 18880 GIM_Try, /*On fail goto*//*Label 1266*/ 44897, // Rule ID 2451 // 18881 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, 18882 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 18883 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18885 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18886 // (intrinsic_wo_chain:{ *:[v1i64] } 226:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTNUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) 18887 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv1i64, 18888 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18890 GIR_EraseFromParent, /*InsnID*/0, 18891 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18892 // GIR_Coverage, 2451, 18893 GIR_Done, 18894 // Label 1266: @44897 18895 GIM_Try, /*On fail goto*//*Label 1267*/ 44935, // Rule ID 2452 // 18896 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, 18897 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 18898 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18901 // (intrinsic_wo_chain:{ *:[v1i64] } 227:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTPSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) 18902 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv1i64, 18903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18904 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18905 GIR_EraseFromParent, /*InsnID*/0, 18906 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18907 // GIR_Coverage, 2452, 18908 GIR_Done, 18909 // Label 1267: @44935 18910 GIM_Try, /*On fail goto*//*Label 1268*/ 44973, // Rule ID 2453 // 18911 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, 18912 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 18913 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18914 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18915 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18916 // (intrinsic_wo_chain:{ *:[v1i64] } 228:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTPUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) 18917 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv1i64, 18918 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18919 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18920 GIR_EraseFromParent, /*InsnID*/0, 18921 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18922 // GIR_Coverage, 2453, 18923 GIR_Done, 18924 // Label 1268: @44973 18925 GIM_Try, /*On fail goto*//*Label 1269*/ 45011, // Rule ID 2454 // 18926 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, 18927 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 18928 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 18929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 18930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 18931 // (intrinsic_wo_chain:{ *:[f16] } 245:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FRECPEv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) 18932 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1f16, 18933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18934 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18935 GIR_EraseFromParent, /*InsnID*/0, 18936 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18937 // GIR_Coverage, 2454, 18938 GIR_Done, 18939 // Label 1269: @45011 18940 GIM_Try, /*On fail goto*//*Label 1270*/ 45049, // Rule ID 2455 // 18941 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, 18942 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 18943 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 18944 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 18945 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 18946 // (intrinsic_wo_chain:{ *:[f32] } 245:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRECPEv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) 18947 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1i32, 18948 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18950 GIR_EraseFromParent, /*InsnID*/0, 18951 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18952 // GIR_Coverage, 2455, 18953 GIR_Done, 18954 // Label 1270: @45049 18955 GIM_Try, /*On fail goto*//*Label 1271*/ 45087, // Rule ID 2456 // 18956 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, 18957 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 18958 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18959 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18961 // (intrinsic_wo_chain:{ *:[f64] } 245:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRECPEv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) 18962 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1i64, 18963 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18965 GIR_EraseFromParent, /*InsnID*/0, 18966 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18967 // GIR_Coverage, 2456, 18968 GIR_Done, 18969 // Label 1271: @45087 18970 GIM_Try, /*On fail goto*//*Label 1272*/ 45125, // Rule ID 2457 // 18971 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, 18972 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 18973 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18974 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 18975 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 18976 // (intrinsic_wo_chain:{ *:[v1f64] } 245:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FRECPEv1i64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn) 18977 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1i64, 18978 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18979 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18980 GIR_EraseFromParent, /*InsnID*/0, 18981 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18982 // GIR_Coverage, 2457, 18983 GIR_Done, 18984 // Label 1272: @45125 18985 GIM_Try, /*On fail goto*//*Label 1273*/ 45163, // Rule ID 2469 // 18986 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpx, 18987 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 18988 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 18989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 18990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 18991 // (intrinsic_wo_chain:{ *:[f16] } 247:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FRECPXv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) 18992 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPXv1f16, 18993 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 18994 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 18995 GIR_EraseFromParent, /*InsnID*/0, 18996 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18997 // GIR_Coverage, 2469, 18998 GIR_Done, 18999 // Label 1273: @45163 19000 GIM_Try, /*On fail goto*//*Label 1274*/ 45201, // Rule ID 2470 // 19001 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpx, 19002 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 19003 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 19004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 19005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 19006 // (intrinsic_wo_chain:{ *:[f32] } 247:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRECPXv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) 19007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPXv1i32, 19008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19010 GIR_EraseFromParent, /*InsnID*/0, 19011 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19012 // GIR_Coverage, 2470, 19013 GIR_Done, 19014 // Label 1274: @45201 19015 GIM_Try, /*On fail goto*//*Label 1275*/ 45239, // Rule ID 2471 // 19016 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpx, 19017 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 19018 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 19019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19021 // (intrinsic_wo_chain:{ *:[f64] } 247:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRECPXv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) 19022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPXv1i64, 19023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19025 GIR_EraseFromParent, /*InsnID*/0, 19026 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19027 // GIR_Coverage, 2471, 19028 GIR_Done, 19029 // Label 1275: @45239 19030 GIM_Try, /*On fail goto*//*Label 1276*/ 45277, // Rule ID 2472 // 19031 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, 19032 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 19033 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 19034 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 19035 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 19036 // (intrinsic_wo_chain:{ *:[f16] } 249:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FRSQRTEv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) 19037 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1f16, 19038 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19039 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19040 GIR_EraseFromParent, /*InsnID*/0, 19041 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19042 // GIR_Coverage, 2472, 19043 GIR_Done, 19044 // Label 1276: @45277 19045 GIM_Try, /*On fail goto*//*Label 1277*/ 45315, // Rule ID 2473 // 19046 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, 19047 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 19048 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 19049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 19050 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 19051 // (intrinsic_wo_chain:{ *:[f32] } 249:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRSQRTEv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) 19052 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1i32, 19053 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19055 GIR_EraseFromParent, /*InsnID*/0, 19056 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19057 // GIR_Coverage, 2473, 19058 GIR_Done, 19059 // Label 1277: @45315 19060 GIM_Try, /*On fail goto*//*Label 1278*/ 45353, // Rule ID 2474 // 19061 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, 19062 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 19063 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 19064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19065 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19066 // (intrinsic_wo_chain:{ *:[f64] } 249:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRSQRTEv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) 19067 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1i64, 19068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19070 GIR_EraseFromParent, /*InsnID*/0, 19071 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19072 // GIR_Coverage, 2474, 19073 GIR_Done, 19074 // Label 1278: @45353 19075 GIM_Try, /*On fail goto*//*Label 1279*/ 45391, // Rule ID 2475 // 19076 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, 19077 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 19078 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 19079 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19080 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19081 // (intrinsic_wo_chain:{ *:[v1f64] } 249:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FRSQRTEv1i64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn) 19082 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1i64, 19083 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19084 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19085 GIR_EraseFromParent, /*InsnID*/0, 19086 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19087 // GIR_Coverage, 2475, 19088 GIR_Done, 19089 // Label 1279: @45391 19090 GIM_Try, /*On fail goto*//*Label 1280*/ 45429, // Rule ID 2602 // 19091 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddv, 19092 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 19093 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 19094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 19095 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19096 // (intrinsic_wo_chain:{ *:[f32] } 220:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FADDPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) 19097 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p, 19098 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19099 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19100 GIR_EraseFromParent, /*InsnID*/0, 19101 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19102 // GIR_Coverage, 2602, 19103 GIR_Done, 19104 // Label 1280: @45429 19105 GIM_Try, /*On fail goto*//*Label 1281*/ 45467, // Rule ID 2604 // 19106 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddv, 19107 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 19108 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 19109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19111 // (intrinsic_wo_chain:{ *:[f64] } 220:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FADDPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) 19112 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i64p, 19113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19114 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19115 GIR_EraseFromParent, /*InsnID*/0, 19116 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19117 // GIR_Coverage, 2604, 19118 GIR_Done, 19119 // Label 1281: @45467 19120 GIM_Try, /*On fail goto*//*Label 1282*/ 45505, // Rule ID 2605 // 19121 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, 19122 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 19123 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 19124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 19125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19126 // (intrinsic_wo_chain:{ *:[f32] } 235:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMAXNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) 19127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2i32p, 19128 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19129 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19130 GIR_EraseFromParent, /*InsnID*/0, 19131 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19132 // GIR_Coverage, 2605, 19133 GIR_Done, 19134 // Label 1282: @45505 19135 GIM_Try, /*On fail goto*//*Label 1283*/ 45543, // Rule ID 2606 // 19136 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, 19137 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 19138 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 19139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19141 // (intrinsic_wo_chain:{ *:[f64] } 235:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMAXNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) 19142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2i64p, 19143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19144 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19145 GIR_EraseFromParent, /*InsnID*/0, 19146 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19147 // GIR_Coverage, 2606, 19148 GIR_Done, 19149 // Label 1283: @45543 19150 GIM_Try, /*On fail goto*//*Label 1284*/ 45581, // Rule ID 2607 // 19151 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, 19152 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 19153 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 19154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 19155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19156 // (intrinsic_wo_chain:{ *:[f32] } 237:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMAXPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) 19157 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2i32p, 19158 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19159 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19160 GIR_EraseFromParent, /*InsnID*/0, 19161 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19162 // GIR_Coverage, 2607, 19163 GIR_Done, 19164 // Label 1284: @45581 19165 GIM_Try, /*On fail goto*//*Label 1285*/ 45619, // Rule ID 2608 // 19166 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, 19167 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 19168 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 19169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19171 // (intrinsic_wo_chain:{ *:[f64] } 237:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMAXPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) 19172 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2i64p, 19173 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19174 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19175 GIR_EraseFromParent, /*InsnID*/0, 19176 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19177 // GIR_Coverage, 2608, 19178 GIR_Done, 19179 // Label 1285: @45619 19180 GIM_Try, /*On fail goto*//*Label 1286*/ 45657, // Rule ID 2609 // 19181 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, 19182 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 19183 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 19184 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 19185 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19186 // (intrinsic_wo_chain:{ *:[f32] } 241:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMINNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) 19187 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2i32p, 19188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19190 GIR_EraseFromParent, /*InsnID*/0, 19191 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19192 // GIR_Coverage, 2609, 19193 GIR_Done, 19194 // Label 1286: @45657 19195 GIM_Try, /*On fail goto*//*Label 1287*/ 45695, // Rule ID 2610 // 19196 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, 19197 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 19198 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 19199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19201 // (intrinsic_wo_chain:{ *:[f64] } 241:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMINNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) 19202 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2i64p, 19203 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19205 GIR_EraseFromParent, /*InsnID*/0, 19206 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19207 // GIR_Coverage, 2610, 19208 GIR_Done, 19209 // Label 1287: @45695 19210 GIM_Try, /*On fail goto*//*Label 1288*/ 45733, // Rule ID 2611 // 19211 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, 19212 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 19213 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 19214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 19215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19216 // (intrinsic_wo_chain:{ *:[f32] } 243:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMINPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) 19217 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2i32p, 19218 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19219 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19220 GIR_EraseFromParent, /*InsnID*/0, 19221 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19222 // GIR_Coverage, 2611, 19223 GIR_Done, 19224 // Label 1288: @45733 19225 GIM_Try, /*On fail goto*//*Label 1289*/ 45771, // Rule ID 2612 // 19226 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, 19227 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 19228 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 19229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19230 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19231 // (intrinsic_wo_chain:{ *:[f64] } 243:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMINPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) 19232 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2i64p, 19233 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19234 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19235 GIR_EraseFromParent, /*InsnID*/0, 19236 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19237 // GIR_Coverage, 2612, 19238 GIR_Done, 19239 // Label 1289: @45771 19240 GIM_Reject, 19241 // Label 1076: @45772 19242 GIM_Try, /*On fail goto*//*Label 1290*/ 68800, 19243 GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, 19244 GIM_Try, /*On fail goto*//*Label 1291*/ 45872, // Rule ID 2926 // 19245 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, 19246 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 19247 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 19248 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 19249 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 19250 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 19251 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, 19252 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 19253 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 19254 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 19255 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, 19256 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] 19257 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 19258 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, 19259 // MIs[2] Operand 1 19260 // No operand predicates 19261 GIM_CheckIsSafeToFold, /*InsnID*/1, 19262 GIM_CheckIsSafeToFold, /*InsnID*/2, 19263 // (intrinsic_wo_chain:{ *:[f16] } 361:{ *:[iPTR] }, (and:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) 19264 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 19265 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 19266 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 19267 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/7, // Rn 19268 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 19269 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFh, 19270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19271 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 19272 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm 19273 GIR_EraseFromParent, /*InsnID*/0, 19274 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19275 // GIR_Coverage, 2926, 19276 GIR_Done, 19277 // Label 1291: @45872 19278 GIM_Try, /*On fail goto*//*Label 1292*/ 45956, // Rule ID 1164 // 19279 GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, 19280 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, 19281 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 19282 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 19283 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 19284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19286 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19287 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 19288 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 19289 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, 19290 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 19291 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, 19292 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19293 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 19294 GIM_CheckIsSafeToFold, /*InsnID*/1, 19295 // (intrinsic_wo_chain:{ *:[v4i16] } 289:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 294:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SQRDMLAHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 19296 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv4i16, 19297 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19298 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 19299 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 19300 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 19301 GIR_EraseFromParent, /*InsnID*/0, 19302 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19303 // GIR_Coverage, 1164, 19304 GIR_Done, 19305 // Label 1292: @45956 19306 GIM_Try, /*On fail goto*//*Label 1293*/ 46040, // Rule ID 1165 // 19307 GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, 19308 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, 19309 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 19310 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 19311 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 19312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 19313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19314 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19315 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 19316 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 19317 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, 19318 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 19319 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, 19320 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19321 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 19322 GIM_CheckIsSafeToFold, /*InsnID*/1, 19323 // (intrinsic_wo_chain:{ *:[v8i16] } 289:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 294:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (SQRDMLAHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 19324 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv8i16, 19325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 19327 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 19328 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 19329 GIR_EraseFromParent, /*InsnID*/0, 19330 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19331 // GIR_Coverage, 1165, 19332 GIR_Done, 19333 // Label 1293: @46040 19334 GIM_Try, /*On fail goto*//*Label 1294*/ 46124, // Rule ID 1166 // 19335 GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, 19336 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, 19337 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 19338 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 19339 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 19340 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19342 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19343 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 19344 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 19345 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, 19346 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 19347 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, 19348 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19349 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 19350 GIM_CheckIsSafeToFold, /*InsnID*/1, 19351 // (intrinsic_wo_chain:{ *:[v2i32] } 289:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 294:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SQRDMLAHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 19352 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv2i32, 19353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 19355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 19356 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 19357 GIR_EraseFromParent, /*InsnID*/0, 19358 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19359 // GIR_Coverage, 1166, 19360 GIR_Done, 19361 // Label 1294: @46124 19362 GIM_Try, /*On fail goto*//*Label 1295*/ 46208, // Rule ID 1167 // 19363 GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, 19364 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, 19365 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 19366 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 19367 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 19368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 19369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19370 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19371 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 19372 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 19373 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, 19374 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 19375 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, 19376 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19377 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 19378 GIM_CheckIsSafeToFold, /*InsnID*/1, 19379 // (intrinsic_wo_chain:{ *:[v4i32] } 289:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 294:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (SQRDMLAHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 19380 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv4i32, 19381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 19383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 19384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 19385 GIR_EraseFromParent, /*InsnID*/0, 19386 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19387 // GIR_Coverage, 1167, 19388 GIR_Done, 19389 // Label 1295: @46208 19390 GIM_Try, /*On fail goto*//*Label 1296*/ 46292, // Rule ID 1168 // 19391 GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, 19392 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, 19393 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 19394 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 19395 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 19396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19398 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19399 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 19400 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 19401 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, 19402 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 19403 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, 19404 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19405 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 19406 GIM_CheckIsSafeToFold, /*InsnID*/1, 19407 // (intrinsic_wo_chain:{ *:[v4i16] } 302:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 294:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SQRDMLSHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 19408 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv4i16, 19409 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19410 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 19411 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 19412 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 19413 GIR_EraseFromParent, /*InsnID*/0, 19414 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19415 // GIR_Coverage, 1168, 19416 GIR_Done, 19417 // Label 1296: @46292 19418 GIM_Try, /*On fail goto*//*Label 1297*/ 46376, // Rule ID 1169 // 19419 GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, 19420 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, 19421 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 19422 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 19423 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 19424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 19425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19426 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19427 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 19428 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 19429 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, 19430 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 19431 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, 19432 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19433 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 19434 GIM_CheckIsSafeToFold, /*InsnID*/1, 19435 // (intrinsic_wo_chain:{ *:[v8i16] } 302:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 294:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (SQRDMLSHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 19436 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv8i16, 19437 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19438 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 19439 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 19440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 19441 GIR_EraseFromParent, /*InsnID*/0, 19442 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19443 // GIR_Coverage, 1169, 19444 GIR_Done, 19445 // Label 1297: @46376 19446 GIM_Try, /*On fail goto*//*Label 1298*/ 46460, // Rule ID 1170 // 19447 GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, 19448 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, 19449 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 19450 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 19451 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 19452 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19453 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19454 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19455 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 19456 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 19457 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, 19458 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 19459 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, 19460 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19461 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 19462 GIM_CheckIsSafeToFold, /*InsnID*/1, 19463 // (intrinsic_wo_chain:{ *:[v2i32] } 302:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 294:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SQRDMLSHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 19464 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv2i32, 19465 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19466 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 19467 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 19468 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 19469 GIR_EraseFromParent, /*InsnID*/0, 19470 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19471 // GIR_Coverage, 1170, 19472 GIR_Done, 19473 // Label 1298: @46460 19474 GIM_Try, /*On fail goto*//*Label 1299*/ 46544, // Rule ID 1171 // 19475 GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, 19476 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, 19477 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 19478 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 19479 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 19480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 19481 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19482 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19483 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 19484 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 19485 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, 19486 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 19487 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, 19488 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19489 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 19490 GIM_CheckIsSafeToFold, /*InsnID*/1, 19491 // (intrinsic_wo_chain:{ *:[v4i32] } 302:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 294:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (SQRDMLSHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 19492 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv4i32, 19493 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19494 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 19495 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 19496 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 19497 GIR_EraseFromParent, /*InsnID*/0, 19498 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19499 // GIR_Coverage, 1171, 19500 GIR_Done, 19501 // Label 1299: @46544 19502 GIM_Try, /*On fail goto*//*Label 1300*/ 46628, // Rule ID 1306 // 19503 GIM_CheckFeatures, GIFBS_HasNEON, 19504 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, 19505 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 19506 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 19507 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 19508 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 19509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19510 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19511 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 19512 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 19513 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, 19514 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 19515 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, 19516 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19517 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 19518 GIM_CheckIsSafeToFold, /*InsnID*/1, 19519 // (intrinsic_wo_chain:{ *:[v4i32] } 289:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 291:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SQDMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 19520 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv4i16_v4i32, 19521 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19522 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 19523 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 19524 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 19525 GIR_EraseFromParent, /*InsnID*/0, 19526 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19527 // GIR_Coverage, 1306, 19528 GIR_Done, 19529 // Label 1300: @46628 19530 GIM_Try, /*On fail goto*//*Label 1301*/ 46712, // Rule ID 1308 // 19531 GIM_CheckFeatures, GIFBS_HasNEON, 19532 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, 19533 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 19534 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 19535 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 19536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 19537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19538 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19539 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 19540 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 19541 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, 19542 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 19543 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, 19544 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19545 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 19546 GIM_CheckIsSafeToFold, /*InsnID*/1, 19547 // (intrinsic_wo_chain:{ *:[v2i64] } 289:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 291:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SQDMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 19548 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv2i32_v2i64, 19549 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19550 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 19551 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 19552 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 19553 GIR_EraseFromParent, /*InsnID*/0, 19554 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19555 // GIR_Coverage, 1308, 19556 GIR_Done, 19557 // Label 1301: @46712 19558 GIM_Try, /*On fail goto*//*Label 1302*/ 46796, // Rule ID 1310 // 19559 GIM_CheckFeatures, GIFBS_HasNEON, 19560 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, 19561 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 19562 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 19563 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 19564 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 19565 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19566 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19567 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 19568 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 19569 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, 19570 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 19571 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, 19572 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19573 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 19574 GIM_CheckIsSafeToFold, /*InsnID*/1, 19575 // (intrinsic_wo_chain:{ *:[v4i32] } 302:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 291:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SQDMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 19576 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv4i16_v4i32, 19577 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19578 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 19579 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 19580 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 19581 GIR_EraseFromParent, /*InsnID*/0, 19582 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19583 // GIR_Coverage, 1310, 19584 GIR_Done, 19585 // Label 1302: @46796 19586 GIM_Try, /*On fail goto*//*Label 1303*/ 46880, // Rule ID 1312 // 19587 GIM_CheckFeatures, GIFBS_HasNEON, 19588 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, 19589 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 19590 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 19591 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 19592 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 19593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19594 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19595 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 19596 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 19597 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, 19598 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 19599 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, 19600 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19601 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 19602 GIM_CheckIsSafeToFold, /*InsnID*/1, 19603 // (intrinsic_wo_chain:{ *:[v2i64] } 302:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 291:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SQDMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 19604 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv2i32_v2i64, 19605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19606 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 19607 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 19608 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 19609 GIR_EraseFromParent, /*InsnID*/0, 19610 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19611 // GIR_Coverage, 1312, 19612 GIR_Done, 19613 // Label 1303: @46880 19614 GIM_Try, /*On fail goto*//*Label 1304*/ 46964, // Rule ID 2430 // 19615 GIM_CheckFeatures, GIFBS_HasRDM, 19616 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, 19617 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 19618 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 19619 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 19620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 19621 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 19622 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19623 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 19624 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 19625 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, 19626 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 19627 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 19628 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 19629 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 19630 GIM_CheckIsSafeToFold, /*InsnID*/1, 19631 // (intrinsic_wo_chain:{ *:[i32] } 289:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, (intrinsic_wo_chain:{ *:[i32] } 294:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)) => (SQRDMLAHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) 19632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv1i32, 19633 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19634 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 19635 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 19636 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 19637 GIR_EraseFromParent, /*InsnID*/0, 19638 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19639 // GIR_Coverage, 2430, 19640 GIR_Done, 19641 // Label 1304: @46964 19642 GIM_Try, /*On fail goto*//*Label 1305*/ 47048, // Rule ID 2431 // 19643 GIM_CheckFeatures, GIFBS_HasRDM, 19644 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, 19645 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 19646 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 19647 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 19648 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 19649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 19650 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19651 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 19652 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 19653 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, 19654 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 19655 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 19656 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 19657 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 19658 GIM_CheckIsSafeToFold, /*InsnID*/1, 19659 // (intrinsic_wo_chain:{ *:[i32] } 302:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, (intrinsic_wo_chain:{ *:[i32] } 294:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)) => (SQRDMLSHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) 19660 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv1i32, 19661 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19662 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 19663 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 19664 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 19665 GIR_EraseFromParent, /*InsnID*/0, 19666 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19667 // GIR_Coverage, 2431, 19668 GIR_Done, 19669 // Label 1305: @47048 19670 GIM_Try, /*On fail goto*//*Label 1306*/ 47130, // Rule ID 2432 // 19671 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, 19672 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 19673 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 19674 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 19675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19676 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19677 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19678 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 19679 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 19680 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, 19681 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 19682 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 19683 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 19684 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 19685 GIM_CheckIsSafeToFold, /*InsnID*/1, 19686 // (intrinsic_wo_chain:{ *:[i64] } 289:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 292:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)) => (SQDMLALi32:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) 19687 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALi32, 19688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 19690 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 19691 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 19692 GIR_EraseFromParent, /*InsnID*/0, 19693 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19694 // GIR_Coverage, 2432, 19695 GIR_Done, 19696 // Label 1306: @47130 19697 GIM_Try, /*On fail goto*//*Label 1307*/ 47212, // Rule ID 2433 // 19698 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, 19699 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 19700 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 19701 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 19702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19703 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19704 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19705 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 19706 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 19707 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, 19708 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 19709 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 19710 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 19711 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 19712 GIM_CheckIsSafeToFold, /*InsnID*/1, 19713 // (intrinsic_wo_chain:{ *:[i64] } 302:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 292:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)) => (SQDMLSLi32:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) 19714 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLi32, 19715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 19717 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 19718 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 19719 GIR_EraseFromParent, /*InsnID*/0, 19720 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19721 // GIR_Coverage, 2433, 19722 GIR_Done, 19723 // Label 1307: @47212 19724 GIM_Try, /*On fail goto*//*Label 1308*/ 47271, // Rule ID 1568 // 19725 GIM_CheckFeatures, GIFBS_HasNEON, 19726 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, 19727 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 19728 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 19729 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 19730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 19731 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19732 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19733 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 19734 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, 19735 // MIs[1] Operand 1 19736 // No operand predicates 19737 GIM_CheckIsSafeToFold, /*InsnID*/1, 19738 // (intrinsic_wo_chain:{ *:[i32] } 296:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SQRSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) 19739 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNs, 19740 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19741 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19742 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 19743 GIR_EraseFromParent, /*InsnID*/0, 19744 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19745 // GIR_Coverage, 1568, 19746 GIR_Done, 19747 // Label 1308: @47271 19748 GIM_Try, /*On fail goto*//*Label 1309*/ 47330, // Rule ID 1569 // 19749 GIM_CheckFeatures, GIFBS_HasNEON, 19750 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, 19751 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 19752 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 19753 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 19754 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 19755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19756 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19757 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 19758 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, 19759 // MIs[1] Operand 1 19760 // No operand predicates 19761 GIM_CheckIsSafeToFold, /*InsnID*/1, 19762 // (intrinsic_wo_chain:{ *:[i32] } 297:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SQRSHRUNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) 19763 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNs, 19764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19766 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 19767 GIR_EraseFromParent, /*InsnID*/0, 19768 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19769 // GIR_Coverage, 1569, 19770 GIR_Done, 19771 // Label 1309: @47330 19772 GIM_Try, /*On fail goto*//*Label 1310*/ 47389, // Rule ID 1574 // 19773 GIM_CheckFeatures, GIFBS_HasNEON, 19774 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, 19775 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 19776 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 19777 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 19778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 19779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19780 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19781 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 19782 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, 19783 // MIs[1] Operand 1 19784 // No operand predicates 19785 GIM_CheckIsSafeToFold, /*InsnID*/1, 19786 // (intrinsic_wo_chain:{ *:[i32] } 300:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SQSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) 19787 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNs, 19788 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19789 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19790 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 19791 GIR_EraseFromParent, /*InsnID*/0, 19792 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19793 // GIR_Coverage, 1574, 19794 GIR_Done, 19795 // Label 1310: @47389 19796 GIM_Try, /*On fail goto*//*Label 1311*/ 47448, // Rule ID 1575 // 19797 GIM_CheckFeatures, GIFBS_HasNEON, 19798 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, 19799 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 19800 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 19801 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 19802 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 19803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19804 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19805 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 19806 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, 19807 // MIs[1] Operand 1 19808 // No operand predicates 19809 GIM_CheckIsSafeToFold, /*InsnID*/1, 19810 // (intrinsic_wo_chain:{ *:[i32] } 301:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SQSHRUNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) 19811 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNs, 19812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19814 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 19815 GIR_EraseFromParent, /*InsnID*/0, 19816 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19817 // GIR_Coverage, 1575, 19818 GIR_Done, 19819 // Label 1311: @47448 19820 GIM_Try, /*On fail goto*//*Label 1312*/ 47507, // Rule ID 1580 // 19821 GIM_CheckFeatures, GIFBS_HasNEON, 19822 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, 19823 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 19824 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 19825 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 19826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 19827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19828 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19829 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 19830 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, 19831 // MIs[1] Operand 1 19832 // No operand predicates 19833 GIM_CheckIsSafeToFold, /*InsnID*/1, 19834 // (intrinsic_wo_chain:{ *:[i32] } 344:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (UQRSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) 19835 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNs, 19836 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19837 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19838 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 19839 GIR_EraseFromParent, /*InsnID*/0, 19840 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19841 // GIR_Coverage, 1580, 19842 GIR_Done, 19843 // Label 1312: @47507 19844 GIM_Try, /*On fail goto*//*Label 1313*/ 47566, // Rule ID 1583 // 19845 GIM_CheckFeatures, GIFBS_HasNEON, 19846 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, 19847 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 19848 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 19849 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 19850 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 19851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 19852 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19853 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 19854 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, 19855 // MIs[1] Operand 1 19856 // No operand predicates 19857 GIM_CheckIsSafeToFold, /*InsnID*/1, 19858 // (intrinsic_wo_chain:{ *:[i32] } 346:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (UQSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) 19859 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNs, 19860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19861 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19862 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 19863 GIR_EraseFromParent, /*InsnID*/0, 19864 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19865 // GIR_Coverage, 1583, 19866 GIR_Done, 19867 // Label 1313: @47566 19868 GIM_Try, /*On fail goto*//*Label 1314*/ 47625, // Rule ID 1603 // 19869 GIM_CheckFeatures, GIFBS_HasNEON, 19870 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rshrn, 19871 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 19872 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 19873 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 19874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19876 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19877 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 19878 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, 19879 // MIs[1] Operand 1 19880 // No operand predicates 19881 GIM_CheckIsSafeToFold, /*InsnID*/1, 19882 // (intrinsic_wo_chain:{ *:[v8i8] } 268:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (RSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) 19883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv8i8_shift, 19884 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19885 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19886 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 19887 GIR_EraseFromParent, /*InsnID*/0, 19888 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19889 // GIR_Coverage, 1603, 19890 GIR_Done, 19891 // Label 1314: @47625 19892 GIM_Try, /*On fail goto*//*Label 1315*/ 47684, // Rule ID 1604 // 19893 GIM_CheckFeatures, GIFBS_HasNEON, 19894 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rshrn, 19895 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 19896 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 19897 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 19898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19900 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19901 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 19902 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, 19903 // MIs[1] Operand 1 19904 // No operand predicates 19905 GIM_CheckIsSafeToFold, /*InsnID*/1, 19906 // (intrinsic_wo_chain:{ *:[v4i16] } 268:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (RSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) 19907 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv4i16_shift, 19908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19909 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19910 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 19911 GIR_EraseFromParent, /*InsnID*/0, 19912 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19913 // GIR_Coverage, 1604, 19914 GIR_Done, 19915 // Label 1315: @47684 19916 GIM_Try, /*On fail goto*//*Label 1316*/ 47743, // Rule ID 1605 // 19917 GIM_CheckFeatures, GIFBS_HasNEON, 19918 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rshrn, 19919 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 19920 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 19921 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 19922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19924 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19925 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 19926 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, 19927 // MIs[1] Operand 1 19928 // No operand predicates 19929 GIM_CheckIsSafeToFold, /*InsnID*/1, 19930 // (intrinsic_wo_chain:{ *:[v2i32] } 268:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (RSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) 19931 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv2i32_shift, 19932 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19934 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 19935 GIR_EraseFromParent, /*InsnID*/0, 19936 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19937 // GIR_Coverage, 1605, 19938 GIR_Done, 19939 // Label 1316: @47743 19940 GIM_Try, /*On fail goto*//*Label 1317*/ 47802, // Rule ID 1623 // 19941 GIM_CheckFeatures, GIFBS_HasNEON, 19942 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, 19943 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 19944 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 19945 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 19946 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19948 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19949 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 19950 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, 19951 // MIs[1] Operand 1 19952 // No operand predicates 19953 GIM_CheckIsSafeToFold, /*InsnID*/1, 19954 // (intrinsic_wo_chain:{ *:[v8i8] } 296:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (SQRSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) 19955 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv8i8_shift, 19956 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19957 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19958 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 19959 GIR_EraseFromParent, /*InsnID*/0, 19960 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19961 // GIR_Coverage, 1623, 19962 GIR_Done, 19963 // Label 1317: @47802 19964 GIM_Try, /*On fail goto*//*Label 1318*/ 47861, // Rule ID 1624 // 19965 GIM_CheckFeatures, GIFBS_HasNEON, 19966 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, 19967 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 19968 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 19969 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 19970 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19972 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19973 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 19974 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, 19975 // MIs[1] Operand 1 19976 // No operand predicates 19977 GIM_CheckIsSafeToFold, /*InsnID*/1, 19978 // (intrinsic_wo_chain:{ *:[v4i16] } 296:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (SQRSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) 19979 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv4i16_shift, 19980 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 19981 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 19982 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 19983 GIR_EraseFromParent, /*InsnID*/0, 19984 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19985 // GIR_Coverage, 1624, 19986 GIR_Done, 19987 // Label 1318: @47861 19988 GIM_Try, /*On fail goto*//*Label 1319*/ 47920, // Rule ID 1625 // 19989 GIM_CheckFeatures, GIFBS_HasNEON, 19990 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, 19991 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 19992 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 19993 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 19994 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 19995 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 19996 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 19997 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 19998 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, 19999 // MIs[1] Operand 1 20000 // No operand predicates 20001 GIM_CheckIsSafeToFold, /*InsnID*/1, 20002 // (intrinsic_wo_chain:{ *:[v2i32] } 296:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (SQRSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) 20003 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv2i32_shift, 20004 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20005 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20006 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20007 GIR_EraseFromParent, /*InsnID*/0, 20008 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20009 // GIR_Coverage, 1625, 20010 GIR_Done, 20011 // Label 1319: @47920 20012 GIM_Try, /*On fail goto*//*Label 1320*/ 47979, // Rule ID 1626 // 20013 GIM_CheckFeatures, GIFBS_HasNEON, 20014 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, 20015 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 20016 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 20017 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20018 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20020 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20021 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20022 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, 20023 // MIs[1] Operand 1 20024 // No operand predicates 20025 GIM_CheckIsSafeToFold, /*InsnID*/1, 20026 // (intrinsic_wo_chain:{ *:[v8i8] } 297:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (SQRSHRUNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) 20027 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv8i8_shift, 20028 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20030 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20031 GIR_EraseFromParent, /*InsnID*/0, 20032 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20033 // GIR_Coverage, 1626, 20034 GIR_Done, 20035 // Label 1320: @47979 20036 GIM_Try, /*On fail goto*//*Label 1321*/ 48038, // Rule ID 1627 // 20037 GIM_CheckFeatures, GIFBS_HasNEON, 20038 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, 20039 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 20040 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 20041 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20044 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20045 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20046 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, 20047 // MIs[1] Operand 1 20048 // No operand predicates 20049 GIM_CheckIsSafeToFold, /*InsnID*/1, 20050 // (intrinsic_wo_chain:{ *:[v4i16] } 297:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (SQRSHRUNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) 20051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv4i16_shift, 20052 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20053 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20054 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20055 GIR_EraseFromParent, /*InsnID*/0, 20056 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20057 // GIR_Coverage, 1627, 20058 GIR_Done, 20059 // Label 1321: @48038 20060 GIM_Try, /*On fail goto*//*Label 1322*/ 48097, // Rule ID 1628 // 20061 GIM_CheckFeatures, GIFBS_HasNEON, 20062 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, 20063 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 20064 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 20065 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20066 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20068 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20069 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20070 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, 20071 // MIs[1] Operand 1 20072 // No operand predicates 20073 GIM_CheckIsSafeToFold, /*InsnID*/1, 20074 // (intrinsic_wo_chain:{ *:[v2i32] } 297:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (SQRSHRUNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) 20075 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv2i32_shift, 20076 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20077 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20078 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20079 GIR_EraseFromParent, /*InsnID*/0, 20080 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20081 // GIR_Coverage, 1628, 20082 GIR_Done, 20083 // Label 1322: @48097 20084 GIM_Try, /*On fail goto*//*Label 1323*/ 48156, // Rule ID 1643 // 20085 GIM_CheckFeatures, GIFBS_HasNEON, 20086 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, 20087 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 20088 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 20089 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20092 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20093 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20094 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, 20095 // MIs[1] Operand 1 20096 // No operand predicates 20097 GIM_CheckIsSafeToFold, /*InsnID*/1, 20098 // (intrinsic_wo_chain:{ *:[v8i8] } 300:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (SQSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) 20099 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv8i8_shift, 20100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20101 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20102 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20103 GIR_EraseFromParent, /*InsnID*/0, 20104 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20105 // GIR_Coverage, 1643, 20106 GIR_Done, 20107 // Label 1323: @48156 20108 GIM_Try, /*On fail goto*//*Label 1324*/ 48215, // Rule ID 1644 // 20109 GIM_CheckFeatures, GIFBS_HasNEON, 20110 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, 20111 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 20112 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 20113 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20114 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20115 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20116 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20117 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20118 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, 20119 // MIs[1] Operand 1 20120 // No operand predicates 20121 GIM_CheckIsSafeToFold, /*InsnID*/1, 20122 // (intrinsic_wo_chain:{ *:[v4i16] } 300:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (SQSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) 20123 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv4i16_shift, 20124 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20126 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20127 GIR_EraseFromParent, /*InsnID*/0, 20128 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20129 // GIR_Coverage, 1644, 20130 GIR_Done, 20131 // Label 1324: @48215 20132 GIM_Try, /*On fail goto*//*Label 1325*/ 48274, // Rule ID 1645 // 20133 GIM_CheckFeatures, GIFBS_HasNEON, 20134 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, 20135 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 20136 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 20137 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20140 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20141 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20142 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, 20143 // MIs[1] Operand 1 20144 // No operand predicates 20145 GIM_CheckIsSafeToFold, /*InsnID*/1, 20146 // (intrinsic_wo_chain:{ *:[v2i32] } 300:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (SQSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) 20147 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv2i32_shift, 20148 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20149 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20150 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20151 GIR_EraseFromParent, /*InsnID*/0, 20152 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20153 // GIR_Coverage, 1645, 20154 GIR_Done, 20155 // Label 1325: @48274 20156 GIM_Try, /*On fail goto*//*Label 1326*/ 48333, // Rule ID 1646 // 20157 GIM_CheckFeatures, GIFBS_HasNEON, 20158 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, 20159 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 20160 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 20161 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20162 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20163 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20164 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20165 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20166 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, 20167 // MIs[1] Operand 1 20168 // No operand predicates 20169 GIM_CheckIsSafeToFold, /*InsnID*/1, 20170 // (intrinsic_wo_chain:{ *:[v8i8] } 301:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (SQSHRUNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) 20171 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv8i8_shift, 20172 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20173 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20174 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20175 GIR_EraseFromParent, /*InsnID*/0, 20176 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20177 // GIR_Coverage, 1646, 20178 GIR_Done, 20179 // Label 1326: @48333 20180 GIM_Try, /*On fail goto*//*Label 1327*/ 48392, // Rule ID 1647 // 20181 GIM_CheckFeatures, GIFBS_HasNEON, 20182 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, 20183 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 20184 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 20185 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20186 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20188 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20189 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20190 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, 20191 // MIs[1] Operand 1 20192 // No operand predicates 20193 GIM_CheckIsSafeToFold, /*InsnID*/1, 20194 // (intrinsic_wo_chain:{ *:[v4i16] } 301:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (SQSHRUNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) 20195 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv4i16_shift, 20196 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20197 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20198 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20199 GIR_EraseFromParent, /*InsnID*/0, 20200 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20201 // GIR_Coverage, 1647, 20202 GIR_Done, 20203 // Label 1327: @48392 20204 GIM_Try, /*On fail goto*//*Label 1328*/ 48451, // Rule ID 1648 // 20205 GIM_CheckFeatures, GIFBS_HasNEON, 20206 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, 20207 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 20208 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 20209 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20210 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20211 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20212 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20213 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20214 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, 20215 // MIs[1] Operand 1 20216 // No operand predicates 20217 GIM_CheckIsSafeToFold, /*InsnID*/1, 20218 // (intrinsic_wo_chain:{ *:[v2i32] } 301:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (SQSHRUNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) 20219 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv2i32_shift, 20220 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20221 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20222 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20223 GIR_EraseFromParent, /*InsnID*/0, 20224 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20225 // GIR_Coverage, 1648, 20226 GIR_Done, 20227 // Label 1328: @48451 20228 GIM_Try, /*On fail goto*//*Label 1329*/ 48510, // Rule ID 1695 // 20229 GIM_CheckFeatures, GIFBS_HasNEON, 20230 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, 20231 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 20232 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 20233 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20236 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20237 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20238 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, 20239 // MIs[1] Operand 1 20240 // No operand predicates 20241 GIM_CheckIsSafeToFold, /*InsnID*/1, 20242 // (intrinsic_wo_chain:{ *:[v8i8] } 344:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (UQRSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) 20243 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv8i8_shift, 20244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20245 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20246 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20247 GIR_EraseFromParent, /*InsnID*/0, 20248 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20249 // GIR_Coverage, 1695, 20250 GIR_Done, 20251 // Label 1329: @48510 20252 GIM_Try, /*On fail goto*//*Label 1330*/ 48569, // Rule ID 1696 // 20253 GIM_CheckFeatures, GIFBS_HasNEON, 20254 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, 20255 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 20256 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 20257 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20258 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20260 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20261 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20262 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, 20263 // MIs[1] Operand 1 20264 // No operand predicates 20265 GIM_CheckIsSafeToFold, /*InsnID*/1, 20266 // (intrinsic_wo_chain:{ *:[v4i16] } 344:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (UQRSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) 20267 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv4i16_shift, 20268 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20270 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20271 GIR_EraseFromParent, /*InsnID*/0, 20272 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20273 // GIR_Coverage, 1696, 20274 GIR_Done, 20275 // Label 1330: @48569 20276 GIM_Try, /*On fail goto*//*Label 1331*/ 48628, // Rule ID 1697 // 20277 GIM_CheckFeatures, GIFBS_HasNEON, 20278 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, 20279 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 20280 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 20281 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20282 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20284 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20285 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20286 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, 20287 // MIs[1] Operand 1 20288 // No operand predicates 20289 GIM_CheckIsSafeToFold, /*InsnID*/1, 20290 // (intrinsic_wo_chain:{ *:[v2i32] } 344:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (UQRSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) 20291 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv2i32_shift, 20292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20293 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20294 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20295 GIR_EraseFromParent, /*InsnID*/0, 20296 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20297 // GIR_Coverage, 1697, 20298 GIR_Done, 20299 // Label 1331: @48628 20300 GIM_Try, /*On fail goto*//*Label 1332*/ 48687, // Rule ID 1705 // 20301 GIM_CheckFeatures, GIFBS_HasNEON, 20302 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, 20303 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 20304 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 20305 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20308 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20309 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20310 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, 20311 // MIs[1] Operand 1 20312 // No operand predicates 20313 GIM_CheckIsSafeToFold, /*InsnID*/1, 20314 // (intrinsic_wo_chain:{ *:[v8i8] } 346:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (UQSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) 20315 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv8i8_shift, 20316 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20317 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20318 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20319 GIR_EraseFromParent, /*InsnID*/0, 20320 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20321 // GIR_Coverage, 1705, 20322 GIR_Done, 20323 // Label 1332: @48687 20324 GIM_Try, /*On fail goto*//*Label 1333*/ 48746, // Rule ID 1706 // 20325 GIM_CheckFeatures, GIFBS_HasNEON, 20326 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, 20327 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 20328 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 20329 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20332 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20333 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20334 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, 20335 // MIs[1] Operand 1 20336 // No operand predicates 20337 GIM_CheckIsSafeToFold, /*InsnID*/1, 20338 // (intrinsic_wo_chain:{ *:[v4i16] } 346:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (UQSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) 20339 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv4i16_shift, 20340 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20341 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20342 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20343 GIR_EraseFromParent, /*InsnID*/0, 20344 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20345 // GIR_Coverage, 1706, 20346 GIR_Done, 20347 // Label 1333: @48746 20348 GIM_Try, /*On fail goto*//*Label 1334*/ 48805, // Rule ID 1707 // 20349 GIM_CheckFeatures, GIFBS_HasNEON, 20350 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, 20351 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 20352 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 20353 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20356 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20357 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20358 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, 20359 // MIs[1] Operand 1 20360 // No operand predicates 20361 GIM_CheckIsSafeToFold, /*InsnID*/1, 20362 // (intrinsic_wo_chain:{ *:[v2i32] } 346:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (UQSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) 20363 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv2i32_shift, 20364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20366 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20367 GIR_EraseFromParent, /*InsnID*/0, 20368 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20369 // GIR_Coverage, 1707, 20370 GIR_Done, 20371 // Label 1334: @48805 20372 GIM_Try, /*On fail goto*//*Label 1335*/ 48862, // Rule ID 2912 // 20373 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, 20374 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 20375 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 20376 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20377 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 20378 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 20379 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20380 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20381 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, 20382 // MIs[1] Operand 1 20383 // No operand predicates 20384 GIM_CheckIsSafeToFold, /*InsnID*/1, 20385 // (intrinsic_wo_chain:{ *:[i32] } 357:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (FCVTZSs:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) 20386 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSs, 20387 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20389 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20390 GIR_EraseFromParent, /*InsnID*/0, 20391 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20392 // GIR_Coverage, 2912, 20393 GIR_Done, 20394 // Label 1335: @48862 20395 GIM_Try, /*On fail goto*//*Label 1336*/ 48919, // Rule ID 2913 // 20396 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, 20397 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 20398 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 20399 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20400 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 20401 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 20402 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20403 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20404 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, 20405 // MIs[1] Operand 1 20406 // No operand predicates 20407 GIM_CheckIsSafeToFold, /*InsnID*/1, 20408 // (intrinsic_wo_chain:{ *:[i32] } 358:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (FCVTZUs:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) 20409 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUs, 20410 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20411 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20412 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20413 GIR_EraseFromParent, /*InsnID*/0, 20414 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20415 // GIR_Coverage, 2913, 20416 GIR_Done, 20417 // Label 1336: @48919 20418 GIM_Try, /*On fail goto*//*Label 1337*/ 48976, // Rule ID 2914 // 20419 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, 20420 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 20421 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 20422 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 20425 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20426 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20427 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, 20428 // MIs[1] Operand 1 20429 // No operand predicates 20430 GIM_CheckIsSafeToFold, /*InsnID*/1, 20431 // (intrinsic_wo_chain:{ *:[i64] } 357:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (FCVTZSd:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) 20432 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSd, 20433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20435 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20436 GIR_EraseFromParent, /*InsnID*/0, 20437 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20438 // GIR_Coverage, 2914, 20439 GIR_Done, 20440 // Label 1337: @48976 20441 GIM_Try, /*On fail goto*//*Label 1338*/ 49033, // Rule ID 2915 // 20442 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, 20443 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 20444 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 20445 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20447 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 20448 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20449 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20450 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, 20451 // MIs[1] Operand 1 20452 // No operand predicates 20453 GIM_CheckIsSafeToFold, /*InsnID*/1, 20454 // (intrinsic_wo_chain:{ *:[i64] } 358:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (FCVTZUd:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) 20455 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUd, 20456 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20458 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20459 GIR_EraseFromParent, /*InsnID*/0, 20460 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20461 // GIR_Coverage, 2915, 20462 GIR_Done, 20463 // Label 1338: @49033 20464 GIM_Try, /*On fail goto*//*Label 1339*/ 49090, // Rule ID 2916 // 20465 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, 20466 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 20467 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 20468 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 20471 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20472 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20473 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, 20474 // MIs[1] Operand 1 20475 // No operand predicates 20476 GIM_CheckIsSafeToFold, /*InsnID*/1, 20477 // (intrinsic_wo_chain:{ *:[v1i64] } 357:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (FCVTZSd:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) 20478 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSd, 20479 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20480 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20481 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20482 GIR_EraseFromParent, /*InsnID*/0, 20483 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20484 // GIR_Coverage, 2916, 20485 GIR_Done, 20486 // Label 1339: @49090 20487 GIM_Try, /*On fail goto*//*Label 1340*/ 49147, // Rule ID 2917 // 20488 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, 20489 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 20490 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 20491 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 20494 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20495 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20496 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, 20497 // MIs[1] Operand 1 20498 // No operand predicates 20499 GIM_CheckIsSafeToFold, /*InsnID*/1, 20500 // (intrinsic_wo_chain:{ *:[v1i64] } 358:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (FCVTZUd:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) 20501 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUd, 20502 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20504 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20505 GIR_EraseFromParent, /*InsnID*/0, 20506 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20507 // GIR_Coverage, 2917, 20508 GIR_Done, 20509 // Label 1340: @49147 20510 GIM_Try, /*On fail goto*//*Label 1341*/ 49204, // Rule ID 2918 // 20511 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, 20512 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 20513 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 20514 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 20516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 20517 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20518 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20519 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, 20520 // MIs[1] Operand 1 20521 // No operand predicates 20522 GIM_CheckIsSafeToFold, /*InsnID*/1, 20523 // (intrinsic_wo_chain:{ *:[f32] } 361:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (UCVTFs:{ *:[f32] } FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) 20524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFs, 20525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20527 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20528 GIR_EraseFromParent, /*InsnID*/0, 20529 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20530 // GIR_Coverage, 2918, 20531 GIR_Done, 20532 // Label 1341: @49204 20533 GIM_Try, /*On fail goto*//*Label 1342*/ 49261, // Rule ID 2919 // 20534 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, 20535 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 20536 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 20537 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20539 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 20540 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20541 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20542 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, 20543 // MIs[1] Operand 1 20544 // No operand predicates 20545 GIM_CheckIsSafeToFold, /*InsnID*/1, 20546 // (intrinsic_wo_chain:{ *:[f64] } 361:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (UCVTFd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) 20547 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFd, 20548 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20549 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20550 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20551 GIR_EraseFromParent, /*InsnID*/0, 20552 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20553 // GIR_Coverage, 2919, 20554 GIR_Done, 20555 // Label 1342: @49261 20556 GIM_Try, /*On fail goto*//*Label 1343*/ 49318, // Rule ID 2920 // 20557 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, 20558 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 20559 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 20560 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20561 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20562 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 20563 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20564 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20565 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, 20566 // MIs[1] Operand 1 20567 // No operand predicates 20568 GIM_CheckIsSafeToFold, /*InsnID*/1, 20569 // (intrinsic_wo_chain:{ *:[v1f64] } 360:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (SCVTFd:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) 20570 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFd, 20571 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20572 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20573 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20574 GIR_EraseFromParent, /*InsnID*/0, 20575 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20576 // GIR_Coverage, 2920, 20577 GIR_Done, 20578 // Label 1343: @49318 20579 GIM_Try, /*On fail goto*//*Label 1344*/ 49375, // Rule ID 2921 // 20580 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, 20581 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 20582 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 20583 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 20586 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20587 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20588 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, 20589 // MIs[1] Operand 1 20590 // No operand predicates 20591 GIM_CheckIsSafeToFold, /*InsnID*/1, 20592 // (intrinsic_wo_chain:{ *:[f64] } 360:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (SCVTFd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) 20593 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFd, 20594 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20595 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20596 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20597 GIR_EraseFromParent, /*InsnID*/0, 20598 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20599 // GIR_Coverage, 2921, 20600 GIR_Done, 20601 // Label 1344: @49375 20602 GIM_Try, /*On fail goto*//*Label 1345*/ 49432, // Rule ID 2922 // 20603 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, 20604 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 20605 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 20606 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20607 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 20609 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20610 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20611 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, 20612 // MIs[1] Operand 1 20613 // No operand predicates 20614 GIM_CheckIsSafeToFold, /*InsnID*/1, 20615 // (intrinsic_wo_chain:{ *:[v1f64] } 361:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (UCVTFd:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) 20616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFd, 20617 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20619 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20620 GIR_EraseFromParent, /*InsnID*/0, 20621 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20622 // GIR_Coverage, 2922, 20623 GIR_Done, 20624 // Label 1345: @49432 20625 GIM_Try, /*On fail goto*//*Label 1346*/ 49489, // Rule ID 2923 // 20626 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, 20627 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 20628 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 20629 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 20631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 20632 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20633 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20634 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, 20635 // MIs[1] Operand 1 20636 // No operand predicates 20637 GIM_CheckIsSafeToFold, /*InsnID*/1, 20638 // (intrinsic_wo_chain:{ *:[f32] } 360:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SCVTFs:{ *:[f32] } FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) 20639 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFs, 20640 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20641 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20642 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20643 GIR_EraseFromParent, /*InsnID*/0, 20644 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20645 // GIR_Coverage, 2923, 20646 GIR_Done, 20647 // Label 1346: @49489 20648 GIM_Try, /*On fail goto*//*Label 1347*/ 49563, // Rule ID 2925 // 20649 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, 20650 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 20651 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 20652 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 20654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 20655 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20656 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20657 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, 20658 // MIs[1] Operand 1 20659 // No operand predicates 20660 GIM_CheckIsSafeToFold, /*InsnID*/1, 20661 // (intrinsic_wo_chain:{ *:[f16] } 360:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (SCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) 20662 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 20663 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 20664 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 20665 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/7, // Rn 20666 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 20667 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFh, 20668 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20669 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 20670 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20671 GIR_EraseFromParent, /*InsnID*/0, 20672 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20673 // GIR_Coverage, 2925, 20674 GIR_Done, 20675 // Label 1347: @49563 20676 GIM_Try, /*On fail goto*//*Label 1348*/ 49637, // Rule ID 2927 // 20677 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, 20678 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 20679 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 20680 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20681 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 20682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 20683 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20684 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20685 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, 20686 // MIs[1] Operand 1 20687 // No operand predicates 20688 GIM_CheckIsSafeToFold, /*InsnID*/1, 20689 // (intrinsic_wo_chain:{ *:[f16] } 361:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) 20690 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 20691 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 20692 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 20693 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/7, // Rn 20694 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 20695 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFh, 20696 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20697 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 20698 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20699 GIR_EraseFromParent, /*InsnID*/0, 20700 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20701 // GIR_Coverage, 2927, 20702 GIR_Done, 20703 // Label 1348: @49637 20704 GIM_Try, /*On fail goto*//*Label 1349*/ 49711, // Rule ID 2928 // 20705 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, 20706 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 20707 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 20708 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 20710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 20711 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20712 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20713 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, 20714 // MIs[1] Operand 1 20715 // No operand predicates 20716 GIM_CheckIsSafeToFold, /*InsnID*/1, 20717 // (intrinsic_wo_chain:{ *:[f16] } 361:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) 20718 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 20719 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 20720 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 20721 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/7, // Rn 20722 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 20723 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFh, 20724 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20725 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 20726 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20727 GIR_EraseFromParent, /*InsnID*/0, 20728 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20729 // GIR_Coverage, 2928, 20730 GIR_Done, 20731 // Label 1349: @49711 20732 GIM_Try, /*On fail goto*//*Label 1350*/ 49767, // Rule ID 1588 // 20733 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 20734 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, 20735 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 20736 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 20737 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 20740 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20741 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20742 // MIs[1] Operand 1 20743 // No operand predicates 20744 GIM_CheckIsSafeToFold, /*InsnID*/1, 20745 // (intrinsic_wo_chain:{ *:[v4i16] } 357:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv4i16_shift:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm) 20746 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv4i16_shift, 20747 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20748 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20749 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20750 GIR_EraseFromParent, /*InsnID*/0, 20751 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20752 // GIR_Coverage, 1588, 20753 GIR_Done, 20754 // Label 1350: @49767 20755 GIM_Try, /*On fail goto*//*Label 1351*/ 49823, // Rule ID 1589 // 20756 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 20757 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, 20758 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 20759 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 20760 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20761 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 20762 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20763 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20764 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20765 // MIs[1] Operand 1 20766 // No operand predicates 20767 GIM_CheckIsSafeToFold, /*InsnID*/1, 20768 // (intrinsic_wo_chain:{ *:[v8i16] } 357:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv8i16_shift:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm) 20769 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv8i16_shift, 20770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20771 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20772 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20773 GIR_EraseFromParent, /*InsnID*/0, 20774 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20775 // GIR_Coverage, 1589, 20776 GIR_Done, 20777 // Label 1351: @49823 20778 GIM_Try, /*On fail goto*//*Label 1352*/ 49879, // Rule ID 1590 // 20779 GIM_CheckFeatures, GIFBS_HasNEON, 20780 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, 20781 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 20782 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 20783 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20784 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20785 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 20786 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20787 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20788 // MIs[1] Operand 1 20789 // No operand predicates 20790 GIM_CheckIsSafeToFold, /*InsnID*/1, 20791 // (intrinsic_wo_chain:{ *:[v2i32] } 357:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv2i32_shift:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm) 20792 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv2i32_shift, 20793 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20794 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20795 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20796 GIR_EraseFromParent, /*InsnID*/0, 20797 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20798 // GIR_Coverage, 1590, 20799 GIR_Done, 20800 // Label 1352: @49879 20801 GIM_Try, /*On fail goto*//*Label 1353*/ 49935, // Rule ID 1591 // 20802 GIM_CheckFeatures, GIFBS_HasNEON, 20803 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, 20804 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 20805 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 20806 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20807 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 20808 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20809 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20810 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20811 // MIs[1] Operand 1 20812 // No operand predicates 20813 GIM_CheckIsSafeToFold, /*InsnID*/1, 20814 // (intrinsic_wo_chain:{ *:[v4i32] } 357:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv4i32_shift:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm) 20815 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv4i32_shift, 20816 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20817 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20818 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20819 GIR_EraseFromParent, /*InsnID*/0, 20820 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20821 // GIR_Coverage, 1591, 20822 GIR_Done, 20823 // Label 1353: @49935 20824 GIM_Try, /*On fail goto*//*Label 1354*/ 49991, // Rule ID 1592 // 20825 GIM_CheckFeatures, GIFBS_HasNEON, 20826 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, 20827 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 20828 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 20829 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20830 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 20831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20832 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20833 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20834 // MIs[1] Operand 1 20835 // No operand predicates 20836 GIM_CheckIsSafeToFold, /*InsnID*/1, 20837 // (intrinsic_wo_chain:{ *:[v2i64] } 357:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv2i64_shift:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm) 20838 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv2i64_shift, 20839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20840 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20841 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20842 GIR_EraseFromParent, /*InsnID*/0, 20843 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20844 // GIR_Coverage, 1592, 20845 GIR_Done, 20846 // Label 1354: @49991 20847 GIM_Try, /*On fail goto*//*Label 1355*/ 50047, // Rule ID 1593 // 20848 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 20849 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, 20850 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 20851 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 20852 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20853 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20854 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 20855 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20856 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20857 // MIs[1] Operand 1 20858 // No operand predicates 20859 GIM_CheckIsSafeToFold, /*InsnID*/1, 20860 // (intrinsic_wo_chain:{ *:[v4i16] } 358:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv4i16_shift:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm) 20861 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv4i16_shift, 20862 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20863 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20864 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20865 GIR_EraseFromParent, /*InsnID*/0, 20866 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20867 // GIR_Coverage, 1593, 20868 GIR_Done, 20869 // Label 1355: @50047 20870 GIM_Try, /*On fail goto*//*Label 1356*/ 50103, // Rule ID 1594 // 20871 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 20872 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, 20873 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 20874 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 20875 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20876 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 20877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20878 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20879 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20880 // MIs[1] Operand 1 20881 // No operand predicates 20882 GIM_CheckIsSafeToFold, /*InsnID*/1, 20883 // (intrinsic_wo_chain:{ *:[v8i16] } 358:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv8i16_shift:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm) 20884 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv8i16_shift, 20885 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20886 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20887 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20888 GIR_EraseFromParent, /*InsnID*/0, 20889 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20890 // GIR_Coverage, 1594, 20891 GIR_Done, 20892 // Label 1356: @50103 20893 GIM_Try, /*On fail goto*//*Label 1357*/ 50159, // Rule ID 1595 // 20894 GIM_CheckFeatures, GIFBS_HasNEON, 20895 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, 20896 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 20897 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 20898 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 20901 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20902 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20903 // MIs[1] Operand 1 20904 // No operand predicates 20905 GIM_CheckIsSafeToFold, /*InsnID*/1, 20906 // (intrinsic_wo_chain:{ *:[v2i32] } 358:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv2i32_shift:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm) 20907 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv2i32_shift, 20908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20909 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20910 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20911 GIR_EraseFromParent, /*InsnID*/0, 20912 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20913 // GIR_Coverage, 1595, 20914 GIR_Done, 20915 // Label 1357: @50159 20916 GIM_Try, /*On fail goto*//*Label 1358*/ 50215, // Rule ID 1596 // 20917 GIM_CheckFeatures, GIFBS_HasNEON, 20918 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, 20919 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 20920 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 20921 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 20923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20924 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20925 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20926 // MIs[1] Operand 1 20927 // No operand predicates 20928 GIM_CheckIsSafeToFold, /*InsnID*/1, 20929 // (intrinsic_wo_chain:{ *:[v4i32] } 358:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv4i32_shift:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm) 20930 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv4i32_shift, 20931 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20932 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20933 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20934 GIR_EraseFromParent, /*InsnID*/0, 20935 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20936 // GIR_Coverage, 1596, 20937 GIR_Done, 20938 // Label 1358: @50215 20939 GIM_Try, /*On fail goto*//*Label 1359*/ 50271, // Rule ID 1597 // 20940 GIM_CheckFeatures, GIFBS_HasNEON, 20941 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, 20942 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 20943 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 20944 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20945 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 20946 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20947 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20948 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20949 // MIs[1] Operand 1 20950 // No operand predicates 20951 GIM_CheckIsSafeToFold, /*InsnID*/1, 20952 // (intrinsic_wo_chain:{ *:[v2i64] } 358:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv2i64_shift:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm) 20953 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv2i64_shift, 20954 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20956 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20957 GIR_EraseFromParent, /*InsnID*/0, 20958 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20959 // GIR_Coverage, 1597, 20960 GIR_Done, 20961 // Label 1359: @50271 20962 GIM_Try, /*On fail goto*//*Label 1360*/ 50327, // Rule ID 1598 // 20963 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 20964 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, 20965 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 20966 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 20967 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20968 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 20969 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 20970 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20971 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20972 // MIs[1] Operand 1 20973 // No operand predicates 20974 GIM_CheckIsSafeToFold, /*InsnID*/1, 20975 // (intrinsic_wo_chain:{ *:[v4f16] } 360:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv4i16_shift:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) 20976 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv4i16_shift, 20977 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 20978 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 20979 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 20980 GIR_EraseFromParent, /*InsnID*/0, 20981 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20982 // GIR_Coverage, 1598, 20983 GIR_Done, 20984 // Label 1360: @50327 20985 GIM_Try, /*On fail goto*//*Label 1361*/ 50383, // Rule ID 1599 // 20986 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 20987 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, 20988 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 20989 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 20990 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 20991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 20992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 20993 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 20994 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 20995 // MIs[1] Operand 1 20996 // No operand predicates 20997 GIM_CheckIsSafeToFold, /*InsnID*/1, 20998 // (intrinsic_wo_chain:{ *:[v8f16] } 360:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv8i16_shift:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) 20999 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv8i16_shift, 21000 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21001 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21002 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 21003 GIR_EraseFromParent, /*InsnID*/0, 21004 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21005 // GIR_Coverage, 1599, 21006 GIR_Done, 21007 // Label 1361: @50383 21008 GIM_Try, /*On fail goto*//*Label 1362*/ 50439, // Rule ID 1600 // 21009 GIM_CheckFeatures, GIFBS_HasNEON, 21010 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, 21011 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 21012 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 21013 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 21014 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 21015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 21016 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 21017 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 21018 // MIs[1] Operand 1 21019 // No operand predicates 21020 GIM_CheckIsSafeToFold, /*InsnID*/1, 21021 // (intrinsic_wo_chain:{ *:[v2f32] } 360:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv2i32_shift:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) 21022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv2i32_shift, 21023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21025 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 21026 GIR_EraseFromParent, /*InsnID*/0, 21027 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21028 // GIR_Coverage, 1600, 21029 GIR_Done, 21030 // Label 1362: @50439 21031 GIM_Try, /*On fail goto*//*Label 1363*/ 50495, // Rule ID 1601 // 21032 GIM_CheckFeatures, GIFBS_HasNEON, 21033 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, 21034 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 21035 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 21036 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 21037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21038 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21039 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 21040 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 21041 // MIs[1] Operand 1 21042 // No operand predicates 21043 GIM_CheckIsSafeToFold, /*InsnID*/1, 21044 // (intrinsic_wo_chain:{ *:[v4f32] } 360:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv4i32_shift:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) 21045 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv4i32_shift, 21046 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21048 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 21049 GIR_EraseFromParent, /*InsnID*/0, 21050 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21051 // GIR_Coverage, 1601, 21052 GIR_Done, 21053 // Label 1363: @50495 21054 GIM_Try, /*On fail goto*//*Label 1364*/ 50551, // Rule ID 1602 // 21055 GIM_CheckFeatures, GIFBS_HasNEON, 21056 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, 21057 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 21058 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 21059 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 21060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21062 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 21063 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 21064 // MIs[1] Operand 1 21065 // No operand predicates 21066 GIM_CheckIsSafeToFold, /*InsnID*/1, 21067 // (intrinsic_wo_chain:{ *:[v2f64] } 360:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv2i64_shift:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) 21068 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv2i64_shift, 21069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21070 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21071 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 21072 GIR_EraseFromParent, /*InsnID*/0, 21073 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21074 // GIR_Coverage, 1602, 21075 GIR_Done, 21076 // Label 1364: @50551 21077 GIM_Try, /*On fail goto*//*Label 1365*/ 50607, // Rule ID 1690 // 21078 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 21079 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, 21080 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 21081 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 21082 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 21083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 21084 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 21085 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 21086 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 21087 // MIs[1] Operand 1 21088 // No operand predicates 21089 GIM_CheckIsSafeToFold, /*InsnID*/1, 21090 // (intrinsic_wo_chain:{ *:[v4f16] } 361:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv4i16_shift:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) 21091 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv4i16_shift, 21092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21094 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 21095 GIR_EraseFromParent, /*InsnID*/0, 21096 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21097 // GIR_Coverage, 1690, 21098 GIR_Done, 21099 // Label 1365: @50607 21100 GIM_Try, /*On fail goto*//*Label 1366*/ 50663, // Rule ID 1691 // 21101 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 21102 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, 21103 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 21104 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 21105 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 21106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21108 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 21109 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 21110 // MIs[1] Operand 1 21111 // No operand predicates 21112 GIM_CheckIsSafeToFold, /*InsnID*/1, 21113 // (intrinsic_wo_chain:{ *:[v8f16] } 361:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv8i16_shift:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) 21114 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv8i16_shift, 21115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21117 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 21118 GIR_EraseFromParent, /*InsnID*/0, 21119 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21120 // GIR_Coverage, 1691, 21121 GIR_Done, 21122 // Label 1366: @50663 21123 GIM_Try, /*On fail goto*//*Label 1367*/ 50719, // Rule ID 1692 // 21124 GIM_CheckFeatures, GIFBS_HasNEON, 21125 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, 21126 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 21127 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 21128 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 21129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 21130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 21131 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 21132 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 21133 // MIs[1] Operand 1 21134 // No operand predicates 21135 GIM_CheckIsSafeToFold, /*InsnID*/1, 21136 // (intrinsic_wo_chain:{ *:[v2f32] } 361:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv2i32_shift:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) 21137 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv2i32_shift, 21138 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21140 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 21141 GIR_EraseFromParent, /*InsnID*/0, 21142 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21143 // GIR_Coverage, 1692, 21144 GIR_Done, 21145 // Label 1367: @50719 21146 GIM_Try, /*On fail goto*//*Label 1368*/ 50775, // Rule ID 1693 // 21147 GIM_CheckFeatures, GIFBS_HasNEON, 21148 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, 21149 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 21150 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 21151 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 21152 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21154 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 21155 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 21156 // MIs[1] Operand 1 21157 // No operand predicates 21158 GIM_CheckIsSafeToFold, /*InsnID*/1, 21159 // (intrinsic_wo_chain:{ *:[v4f32] } 361:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv4i32_shift:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) 21160 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv4i32_shift, 21161 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21163 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 21164 GIR_EraseFromParent, /*InsnID*/0, 21165 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21166 // GIR_Coverage, 1693, 21167 GIR_Done, 21168 // Label 1368: @50775 21169 GIM_Try, /*On fail goto*//*Label 1369*/ 50831, // Rule ID 1694 // 21170 GIM_CheckFeatures, GIFBS_HasNEON, 21171 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, 21172 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 21173 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 21174 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 21175 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21177 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 21178 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 21179 // MIs[1] Operand 1 21180 // No operand predicates 21181 GIM_CheckIsSafeToFold, /*InsnID*/1, 21182 // (intrinsic_wo_chain:{ *:[v2f64] } 361:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv2i64_shift:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) 21183 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv2i64_shift, 21184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21186 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 21187 GIR_EraseFromParent, /*InsnID*/0, 21188 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21189 // GIR_Coverage, 1694, 21190 GIR_Done, 21191 // Label 1369: @50831 21192 GIM_Try, /*On fail goto*//*Label 1370*/ 50883, // Rule ID 71 // 21193 GIM_CheckFeatures, GIFBS_HasCRC, 21194 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32b, 21195 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 21196 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 21197 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 21198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 21199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 21200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 21201 // (intrinsic_wo_chain:{ *:[i32] } 182:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32Brr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 21202 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Brr, 21203 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21206 GIR_EraseFromParent, /*InsnID*/0, 21207 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21208 // GIR_Coverage, 71, 21209 GIR_Done, 21210 // Label 1370: @50883 21211 GIM_Try, /*On fail goto*//*Label 1371*/ 50935, // Rule ID 72 // 21212 GIM_CheckFeatures, GIFBS_HasCRC, 21213 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32h, 21214 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 21215 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 21216 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 21217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 21218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 21219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 21220 // (intrinsic_wo_chain:{ *:[i32] } 187:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32Hrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 21221 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Hrr, 21222 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21225 GIR_EraseFromParent, /*InsnID*/0, 21226 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21227 // GIR_Coverage, 72, 21228 GIR_Done, 21229 // Label 1371: @50935 21230 GIM_Try, /*On fail goto*//*Label 1372*/ 50987, // Rule ID 73 // 21231 GIM_CheckFeatures, GIFBS_HasCRC, 21232 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32w, 21233 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 21234 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 21235 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 21236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 21237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 21238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 21239 // (intrinsic_wo_chain:{ *:[i32] } 188:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32Wrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 21240 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Wrr, 21241 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21242 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21243 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21244 GIR_EraseFromParent, /*InsnID*/0, 21245 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21246 // GIR_Coverage, 73, 21247 GIR_Done, 21248 // Label 1372: @50987 21249 GIM_Try, /*On fail goto*//*Label 1373*/ 51039, // Rule ID 74 // 21250 GIM_CheckFeatures, GIFBS_HasCRC, 21251 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32x, 21252 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 21253 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 21254 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 21255 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 21256 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 21257 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, 21258 // (intrinsic_wo_chain:{ *:[i32] } 189:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (CRC32Xrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm) 21259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Xrr, 21260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21262 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21263 GIR_EraseFromParent, /*InsnID*/0, 21264 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21265 // GIR_Coverage, 74, 21266 GIR_Done, 21267 // Label 1373: @51039 21268 GIM_Try, /*On fail goto*//*Label 1374*/ 51091, // Rule ID 75 // 21269 GIM_CheckFeatures, GIFBS_HasCRC, 21270 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32cb, 21271 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 21272 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 21273 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 21274 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 21275 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 21276 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 21277 // (intrinsic_wo_chain:{ *:[i32] } 183:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32CBrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 21278 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CBrr, 21279 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21280 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21281 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21282 GIR_EraseFromParent, /*InsnID*/0, 21283 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21284 // GIR_Coverage, 75, 21285 GIR_Done, 21286 // Label 1374: @51091 21287 GIM_Try, /*On fail goto*//*Label 1375*/ 51143, // Rule ID 76 // 21288 GIM_CheckFeatures, GIFBS_HasCRC, 21289 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32ch, 21290 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 21291 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 21292 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 21293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 21294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 21295 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 21296 // (intrinsic_wo_chain:{ *:[i32] } 184:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32CHrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 21297 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CHrr, 21298 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21299 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21300 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21301 GIR_EraseFromParent, /*InsnID*/0, 21302 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21303 // GIR_Coverage, 76, 21304 GIR_Done, 21305 // Label 1375: @51143 21306 GIM_Try, /*On fail goto*//*Label 1376*/ 51195, // Rule ID 77 // 21307 GIM_CheckFeatures, GIFBS_HasCRC, 21308 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32cw, 21309 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 21310 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 21311 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 21312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 21313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 21314 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 21315 // (intrinsic_wo_chain:{ *:[i32] } 185:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32CWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 21316 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CWrr, 21317 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21318 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21319 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21320 GIR_EraseFromParent, /*InsnID*/0, 21321 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21322 // GIR_Coverage, 77, 21323 GIR_Done, 21324 // Label 1376: @51195 21325 GIM_Try, /*On fail goto*//*Label 1377*/ 51247, // Rule ID 78 // 21326 GIM_CheckFeatures, GIFBS_HasCRC, 21327 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32cx, 21328 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 21329 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 21330 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 21331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 21332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 21333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, 21334 // (intrinsic_wo_chain:{ *:[i32] } 186:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (CRC32CXrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm) 21335 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CXrr, 21336 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21337 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21338 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21339 GIR_EraseFromParent, /*InsnID*/0, 21340 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21341 // GIR_Coverage, 78, 21342 GIR_Done, 21343 // Label 1377: @51247 21344 GIM_Try, /*On fail goto*//*Label 1378*/ 51299, // Rule ID 720 // 21345 GIM_CheckFeatures, GIFBS_HasNEON, 21346 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, 21347 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 21348 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 21349 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 21350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 21351 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 21352 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 21353 // (intrinsic_wo_chain:{ *:[v8i8] } 319:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) => (SUQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) 21354 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv8i8, 21355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21356 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 21357 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 21358 GIR_EraseFromParent, /*InsnID*/0, 21359 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21360 // GIR_Coverage, 720, 21361 GIR_Done, 21362 // Label 1378: @51299 21363 GIM_Try, /*On fail goto*//*Label 1379*/ 51351, // Rule ID 721 // 21364 GIM_CheckFeatures, GIFBS_HasNEON, 21365 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, 21366 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 21367 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 21368 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 21369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21372 // (intrinsic_wo_chain:{ *:[v16i8] } 319:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (SUQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) 21373 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv16i8, 21374 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21375 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 21376 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 21377 GIR_EraseFromParent, /*InsnID*/0, 21378 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21379 // GIR_Coverage, 721, 21380 GIR_Done, 21381 // Label 1379: @51351 21382 GIM_Try, /*On fail goto*//*Label 1380*/ 51403, // Rule ID 722 // 21383 GIM_CheckFeatures, GIFBS_HasNEON, 21384 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, 21385 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 21386 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 21387 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 21388 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 21389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 21390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 21391 // (intrinsic_wo_chain:{ *:[v4i16] } 319:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) => (SUQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) 21392 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv4i16, 21393 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21394 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 21395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 21396 GIR_EraseFromParent, /*InsnID*/0, 21397 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21398 // GIR_Coverage, 722, 21399 GIR_Done, 21400 // Label 1380: @51403 21401 GIM_Try, /*On fail goto*//*Label 1381*/ 51455, // Rule ID 723 // 21402 GIM_CheckFeatures, GIFBS_HasNEON, 21403 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, 21404 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 21405 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 21406 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 21407 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21408 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21409 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21410 // (intrinsic_wo_chain:{ *:[v8i16] } 319:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn) => (SUQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn) 21411 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv8i16, 21412 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21413 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 21414 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 21415 GIR_EraseFromParent, /*InsnID*/0, 21416 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21417 // GIR_Coverage, 723, 21418 GIR_Done, 21419 // Label 1381: @51455 21420 GIM_Try, /*On fail goto*//*Label 1382*/ 51507, // Rule ID 724 // 21421 GIM_CheckFeatures, GIFBS_HasNEON, 21422 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, 21423 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 21424 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 21425 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 21426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 21427 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 21428 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 21429 // (intrinsic_wo_chain:{ *:[v2i32] } 319:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) => (SUQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) 21430 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv2i32, 21431 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21432 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 21433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 21434 GIR_EraseFromParent, /*InsnID*/0, 21435 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21436 // GIR_Coverage, 724, 21437 GIR_Done, 21438 // Label 1382: @51507 21439 GIM_Try, /*On fail goto*//*Label 1383*/ 51559, // Rule ID 725 // 21440 GIM_CheckFeatures, GIFBS_HasNEON, 21441 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, 21442 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 21443 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 21444 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 21445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21447 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21448 // (intrinsic_wo_chain:{ *:[v4i32] } 319:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (SUQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) 21449 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv4i32, 21450 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21451 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 21452 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 21453 GIR_EraseFromParent, /*InsnID*/0, 21454 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21455 // GIR_Coverage, 725, 21456 GIR_Done, 21457 // Label 1383: @51559 21458 GIM_Try, /*On fail goto*//*Label 1384*/ 51611, // Rule ID 726 // 21459 GIM_CheckFeatures, GIFBS_HasNEON, 21460 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, 21461 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 21462 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 21463 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 21464 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21467 // (intrinsic_wo_chain:{ *:[v2i64] } 319:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn) => (SUQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn) 21468 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv2i64, 21469 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21470 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 21471 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 21472 GIR_EraseFromParent, /*InsnID*/0, 21473 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21474 // GIR_Coverage, 726, 21475 GIR_Done, 21476 // Label 1384: @51611 21477 GIM_Try, /*On fail goto*//*Label 1385*/ 51663, // Rule ID 751 // 21478 GIM_CheckFeatures, GIFBS_HasNEON, 21479 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, 21480 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 21481 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 21482 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 21483 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 21484 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 21485 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 21486 // (intrinsic_wo_chain:{ *:[v8i8] } 355:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) => (USQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) 21487 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv8i8, 21488 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21489 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 21490 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 21491 GIR_EraseFromParent, /*InsnID*/0, 21492 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21493 // GIR_Coverage, 751, 21494 GIR_Done, 21495 // Label 1385: @51663 21496 GIM_Try, /*On fail goto*//*Label 1386*/ 51715, // Rule ID 752 // 21497 GIM_CheckFeatures, GIFBS_HasNEON, 21498 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, 21499 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 21500 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 21501 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 21502 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21504 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21505 // (intrinsic_wo_chain:{ *:[v16i8] } 355:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (USQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) 21506 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv16i8, 21507 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21508 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 21509 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 21510 GIR_EraseFromParent, /*InsnID*/0, 21511 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21512 // GIR_Coverage, 752, 21513 GIR_Done, 21514 // Label 1386: @51715 21515 GIM_Try, /*On fail goto*//*Label 1387*/ 51767, // Rule ID 753 // 21516 GIM_CheckFeatures, GIFBS_HasNEON, 21517 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, 21518 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 21519 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 21520 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 21521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 21522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 21523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 21524 // (intrinsic_wo_chain:{ *:[v4i16] } 355:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) => (USQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) 21525 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv4i16, 21526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 21528 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 21529 GIR_EraseFromParent, /*InsnID*/0, 21530 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21531 // GIR_Coverage, 753, 21532 GIR_Done, 21533 // Label 1387: @51767 21534 GIM_Try, /*On fail goto*//*Label 1388*/ 51819, // Rule ID 754 // 21535 GIM_CheckFeatures, GIFBS_HasNEON, 21536 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, 21537 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 21538 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 21539 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 21540 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21542 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21543 // (intrinsic_wo_chain:{ *:[v8i16] } 355:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn) => (USQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn) 21544 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv8i16, 21545 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21546 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 21547 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 21548 GIR_EraseFromParent, /*InsnID*/0, 21549 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21550 // GIR_Coverage, 754, 21551 GIR_Done, 21552 // Label 1388: @51819 21553 GIM_Try, /*On fail goto*//*Label 1389*/ 51871, // Rule ID 755 // 21554 GIM_CheckFeatures, GIFBS_HasNEON, 21555 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, 21556 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 21557 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 21558 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 21559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 21560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 21561 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 21562 // (intrinsic_wo_chain:{ *:[v2i32] } 355:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) => (USQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) 21563 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv2i32, 21564 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21565 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 21566 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 21567 GIR_EraseFromParent, /*InsnID*/0, 21568 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21569 // GIR_Coverage, 755, 21570 GIR_Done, 21571 // Label 1389: @51871 21572 GIM_Try, /*On fail goto*//*Label 1390*/ 51923, // Rule ID 756 // 21573 GIM_CheckFeatures, GIFBS_HasNEON, 21574 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, 21575 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 21576 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 21577 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 21578 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21581 // (intrinsic_wo_chain:{ *:[v4i32] } 355:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (USQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) 21582 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv4i32, 21583 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21584 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 21585 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 21586 GIR_EraseFromParent, /*InsnID*/0, 21587 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21588 // GIR_Coverage, 756, 21589 GIR_Done, 21590 // Label 1390: @51923 21591 GIM_Try, /*On fail goto*//*Label 1391*/ 51975, // Rule ID 757 // 21592 GIM_CheckFeatures, GIFBS_HasNEON, 21593 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, 21594 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 21595 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 21596 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 21597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21599 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21600 // (intrinsic_wo_chain:{ *:[v2i64] } 355:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn) => (USQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn) 21601 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv2i64, 21602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 21604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 21605 GIR_EraseFromParent, /*InsnID*/0, 21606 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21607 // GIR_Coverage, 757, 21608 GIR_Done, 21609 // Label 1391: @51975 21610 GIM_Try, /*On fail goto*//*Label 1392*/ 52027, // Rule ID 768 // 21611 GIM_CheckFeatures, GIFBS_HasNEON, 21612 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, 21613 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 21614 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 21615 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 21616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 21617 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 21618 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 21619 // (intrinsic_wo_chain:{ *:[v8i8] } 215:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ADDPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 21620 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv8i8, 21621 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21622 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21624 GIR_EraseFromParent, /*InsnID*/0, 21625 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21626 // GIR_Coverage, 768, 21627 GIR_Done, 21628 // Label 1392: @52027 21629 GIM_Try, /*On fail goto*//*Label 1393*/ 52079, // Rule ID 769 // 21630 GIM_CheckFeatures, GIFBS_HasNEON, 21631 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, 21632 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 21633 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 21634 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 21635 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21638 // (intrinsic_wo_chain:{ *:[v16i8] } 215:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ADDPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 21639 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv16i8, 21640 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21641 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21642 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21643 GIR_EraseFromParent, /*InsnID*/0, 21644 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21645 // GIR_Coverage, 769, 21646 GIR_Done, 21647 // Label 1393: @52079 21648 GIM_Try, /*On fail goto*//*Label 1394*/ 52131, // Rule ID 770 // 21649 GIM_CheckFeatures, GIFBS_HasNEON, 21650 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, 21651 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 21652 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 21653 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 21654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 21655 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 21656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 21657 // (intrinsic_wo_chain:{ *:[v4i16] } 215:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (ADDPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 21658 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv4i16, 21659 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21660 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21661 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21662 GIR_EraseFromParent, /*InsnID*/0, 21663 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21664 // GIR_Coverage, 770, 21665 GIR_Done, 21666 // Label 1394: @52131 21667 GIM_Try, /*On fail goto*//*Label 1395*/ 52183, // Rule ID 771 // 21668 GIM_CheckFeatures, GIFBS_HasNEON, 21669 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, 21670 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 21671 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 21672 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 21673 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21674 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21676 // (intrinsic_wo_chain:{ *:[v8i16] } 215:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ADDPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 21677 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv8i16, 21678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21679 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21680 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21681 GIR_EraseFromParent, /*InsnID*/0, 21682 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21683 // GIR_Coverage, 771, 21684 GIR_Done, 21685 // Label 1395: @52183 21686 GIM_Try, /*On fail goto*//*Label 1396*/ 52235, // Rule ID 772 // 21687 GIM_CheckFeatures, GIFBS_HasNEON, 21688 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, 21689 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 21690 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 21691 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 21692 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 21693 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 21694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 21695 // (intrinsic_wo_chain:{ *:[v2i32] } 215:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (ADDPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 21696 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i32, 21697 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21698 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21699 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21700 GIR_EraseFromParent, /*InsnID*/0, 21701 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21702 // GIR_Coverage, 772, 21703 GIR_Done, 21704 // Label 1396: @52235 21705 GIM_Try, /*On fail goto*//*Label 1397*/ 52287, // Rule ID 773 // 21706 GIM_CheckFeatures, GIFBS_HasNEON, 21707 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, 21708 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 21709 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 21710 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 21711 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21712 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21714 // (intrinsic_wo_chain:{ *:[v4i32] } 215:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ADDPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 21715 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv4i32, 21716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21717 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21718 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21719 GIR_EraseFromParent, /*InsnID*/0, 21720 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21721 // GIR_Coverage, 773, 21722 GIR_Done, 21723 // Label 1397: @52287 21724 GIM_Try, /*On fail goto*//*Label 1398*/ 52339, // Rule ID 774 // 21725 GIM_CheckFeatures, GIFBS_HasNEON, 21726 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, 21727 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 21728 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 21729 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 21730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21731 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21732 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21733 // (intrinsic_wo_chain:{ *:[v2i64] } 215:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ADDPv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) 21734 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i64, 21735 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21736 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21737 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21738 GIR_EraseFromParent, /*InsnID*/0, 21739 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21740 // GIR_Coverage, 774, 21741 GIR_Done, 21742 // Label 1398: @52339 21743 GIM_Try, /*On fail goto*//*Label 1399*/ 52391, // Rule ID 817 // 21744 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 21745 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, 21746 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 21747 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 21748 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 21749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 21750 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 21751 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 21752 // (intrinsic_wo_chain:{ *:[v4f16] } 217:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FABDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) 21753 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv4f16, 21754 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21755 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21756 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21757 GIR_EraseFromParent, /*InsnID*/0, 21758 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21759 // GIR_Coverage, 817, 21760 GIR_Done, 21761 // Label 1399: @52391 21762 GIM_Try, /*On fail goto*//*Label 1400*/ 52443, // Rule ID 818 // 21763 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 21764 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, 21765 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 21766 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 21767 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 21768 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21769 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21770 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21771 // (intrinsic_wo_chain:{ *:[v8f16] } 217:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FABDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) 21772 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv8f16, 21773 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21774 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21775 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21776 GIR_EraseFromParent, /*InsnID*/0, 21777 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21778 // GIR_Coverage, 818, 21779 GIR_Done, 21780 // Label 1400: @52443 21781 GIM_Try, /*On fail goto*//*Label 1401*/ 52495, // Rule ID 819 // 21782 GIM_CheckFeatures, GIFBS_HasNEON, 21783 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, 21784 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 21785 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 21786 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 21787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 21788 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 21789 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 21790 // (intrinsic_wo_chain:{ *:[v2f32] } 217:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FABDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) 21791 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv2f32, 21792 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21793 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21794 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21795 GIR_EraseFromParent, /*InsnID*/0, 21796 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21797 // GIR_Coverage, 819, 21798 GIR_Done, 21799 // Label 1401: @52495 21800 GIM_Try, /*On fail goto*//*Label 1402*/ 52547, // Rule ID 820 // 21801 GIM_CheckFeatures, GIFBS_HasNEON, 21802 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, 21803 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 21804 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 21805 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 21806 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21807 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21808 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21809 // (intrinsic_wo_chain:{ *:[v4f32] } 217:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FABDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) 21810 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv4f32, 21811 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21814 GIR_EraseFromParent, /*InsnID*/0, 21815 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21816 // GIR_Coverage, 820, 21817 GIR_Done, 21818 // Label 1402: @52547 21819 GIM_Try, /*On fail goto*//*Label 1403*/ 52599, // Rule ID 821 // 21820 GIM_CheckFeatures, GIFBS_HasNEON, 21821 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, 21822 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 21823 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 21824 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 21825 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21828 // (intrinsic_wo_chain:{ *:[v2f64] } 217:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FABDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) 21829 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv2f64, 21830 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21832 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21833 GIR_EraseFromParent, /*InsnID*/0, 21834 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21835 // GIR_Coverage, 821, 21836 GIR_Done, 21837 // Label 1403: @52599 21838 GIM_Try, /*On fail goto*//*Label 1404*/ 52651, // Rule ID 822 // 21839 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 21840 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, 21841 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 21842 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 21843 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 21844 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 21845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 21846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 21847 // (intrinsic_wo_chain:{ *:[v4i16] } 218:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FACGEv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) 21848 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv4f16, 21849 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21852 GIR_EraseFromParent, /*InsnID*/0, 21853 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21854 // GIR_Coverage, 822, 21855 GIR_Done, 21856 // Label 1404: @52651 21857 GIM_Try, /*On fail goto*//*Label 1405*/ 52703, // Rule ID 823 // 21858 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 21859 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, 21860 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 21861 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 21862 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 21863 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21864 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21865 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21866 // (intrinsic_wo_chain:{ *:[v8i16] } 218:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FACGEv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) 21867 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv8f16, 21868 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21869 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21870 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21871 GIR_EraseFromParent, /*InsnID*/0, 21872 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21873 // GIR_Coverage, 823, 21874 GIR_Done, 21875 // Label 1405: @52703 21876 GIM_Try, /*On fail goto*//*Label 1406*/ 52755, // Rule ID 824 // 21877 GIM_CheckFeatures, GIFBS_HasNEON, 21878 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, 21879 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 21880 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 21881 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 21882 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 21883 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 21884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 21885 // (intrinsic_wo_chain:{ *:[v2i32] } 218:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FACGEv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) 21886 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv2f32, 21887 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21888 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21890 GIR_EraseFromParent, /*InsnID*/0, 21891 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21892 // GIR_Coverage, 824, 21893 GIR_Done, 21894 // Label 1406: @52755 21895 GIM_Try, /*On fail goto*//*Label 1407*/ 52807, // Rule ID 825 // 21896 GIM_CheckFeatures, GIFBS_HasNEON, 21897 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, 21898 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 21899 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 21900 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 21901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21904 // (intrinsic_wo_chain:{ *:[v4i32] } 218:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FACGEv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) 21905 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv4f32, 21906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21909 GIR_EraseFromParent, /*InsnID*/0, 21910 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21911 // GIR_Coverage, 825, 21912 GIR_Done, 21913 // Label 1407: @52807 21914 GIM_Try, /*On fail goto*//*Label 1408*/ 52859, // Rule ID 826 // 21915 GIM_CheckFeatures, GIFBS_HasNEON, 21916 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, 21917 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 21918 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 21919 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 21920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21921 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21923 // (intrinsic_wo_chain:{ *:[v2i64] } 218:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FACGEv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) 21924 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv2f64, 21925 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21926 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21927 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21928 GIR_EraseFromParent, /*InsnID*/0, 21929 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21930 // GIR_Coverage, 826, 21931 GIR_Done, 21932 // Label 1408: @52859 21933 GIM_Try, /*On fail goto*//*Label 1409*/ 52911, // Rule ID 827 // 21934 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 21935 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, 21936 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 21937 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 21938 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 21939 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 21940 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 21941 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 21942 // (intrinsic_wo_chain:{ *:[v4i16] } 219:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FACGTv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) 21943 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv4f16, 21944 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21947 GIR_EraseFromParent, /*InsnID*/0, 21948 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21949 // GIR_Coverage, 827, 21950 GIR_Done, 21951 // Label 1409: @52911 21952 GIM_Try, /*On fail goto*//*Label 1410*/ 52963, // Rule ID 828 // 21953 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 21954 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, 21955 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 21956 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 21957 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 21958 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21959 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21961 // (intrinsic_wo_chain:{ *:[v8i16] } 219:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FACGTv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) 21962 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv8f16, 21963 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21966 GIR_EraseFromParent, /*InsnID*/0, 21967 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21968 // GIR_Coverage, 828, 21969 GIR_Done, 21970 // Label 1410: @52963 21971 GIM_Try, /*On fail goto*//*Label 1411*/ 53015, // Rule ID 829 // 21972 GIM_CheckFeatures, GIFBS_HasNEON, 21973 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, 21974 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 21975 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 21976 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 21977 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 21978 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 21979 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 21980 // (intrinsic_wo_chain:{ *:[v2i32] } 219:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FACGTv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) 21981 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv2f32, 21982 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 21983 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 21984 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 21985 GIR_EraseFromParent, /*InsnID*/0, 21986 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21987 // GIR_Coverage, 829, 21988 GIR_Done, 21989 // Label 1411: @53015 21990 GIM_Try, /*On fail goto*//*Label 1412*/ 53067, // Rule ID 830 // 21991 GIM_CheckFeatures, GIFBS_HasNEON, 21992 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, 21993 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 21994 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 21995 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 21996 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 21997 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 21998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 21999 // (intrinsic_wo_chain:{ *:[v4i32] } 219:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FACGTv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) 22000 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv4f32, 22001 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22002 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22003 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22004 GIR_EraseFromParent, /*InsnID*/0, 22005 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22006 // GIR_Coverage, 830, 22007 GIR_Done, 22008 // Label 1412: @53067 22009 GIM_Try, /*On fail goto*//*Label 1413*/ 53119, // Rule ID 831 // 22010 GIM_CheckFeatures, GIFBS_HasNEON, 22011 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, 22012 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 22013 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 22014 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 22015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22018 // (intrinsic_wo_chain:{ *:[v2i64] } 219:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FACGTv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) 22019 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv2f64, 22020 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22021 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22022 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22023 GIR_EraseFromParent, /*InsnID*/0, 22024 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22025 // GIR_Coverage, 831, 22026 GIR_Done, 22027 // Label 1413: @53119 22028 GIM_Try, /*On fail goto*//*Label 1414*/ 53171, // Rule ID 832 // 22029 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 22030 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, 22031 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 22032 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 22033 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 22034 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22035 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22037 // (intrinsic_wo_chain:{ *:[v4f16] } 215:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FADDPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) 22038 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv4f16, 22039 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22040 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22041 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22042 GIR_EraseFromParent, /*InsnID*/0, 22043 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22044 // GIR_Coverage, 832, 22045 GIR_Done, 22046 // Label 1414: @53171 22047 GIM_Try, /*On fail goto*//*Label 1415*/ 53223, // Rule ID 833 // 22048 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 22049 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, 22050 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 22051 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 22052 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 22053 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22054 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22056 // (intrinsic_wo_chain:{ *:[v8f16] } 215:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FADDPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) 22057 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv8f16, 22058 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22059 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22060 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22061 GIR_EraseFromParent, /*InsnID*/0, 22062 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22063 // GIR_Coverage, 833, 22064 GIR_Done, 22065 // Label 1415: @53223 22066 GIM_Try, /*On fail goto*//*Label 1416*/ 53275, // Rule ID 834 // 22067 GIM_CheckFeatures, GIFBS_HasNEON, 22068 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, 22069 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 22070 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 22071 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 22072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22075 // (intrinsic_wo_chain:{ *:[v2f32] } 215:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FADDPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) 22076 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2f32, 22077 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22078 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22079 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22080 GIR_EraseFromParent, /*InsnID*/0, 22081 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22082 // GIR_Coverage, 834, 22083 GIR_Done, 22084 // Label 1416: @53275 22085 GIM_Try, /*On fail goto*//*Label 1417*/ 53327, // Rule ID 835 // 22086 GIM_CheckFeatures, GIFBS_HasNEON, 22087 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, 22088 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 22089 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 22090 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 22091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22092 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22094 // (intrinsic_wo_chain:{ *:[v4f32] } 215:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FADDPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) 22095 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv4f32, 22096 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22097 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22098 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22099 GIR_EraseFromParent, /*InsnID*/0, 22100 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22101 // GIR_Coverage, 835, 22102 GIR_Done, 22103 // Label 1417: @53327 22104 GIM_Try, /*On fail goto*//*Label 1418*/ 53379, // Rule ID 836 // 22105 GIM_CheckFeatures, GIFBS_HasNEON, 22106 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, 22107 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 22108 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 22109 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 22110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22113 // (intrinsic_wo_chain:{ *:[v2f64] } 215:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FADDPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) 22114 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2f64, 22115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22117 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22118 GIR_EraseFromParent, /*InsnID*/0, 22119 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22120 // GIR_Coverage, 836, 22121 GIR_Done, 22122 // Label 1418: @53379 22123 GIM_Try, /*On fail goto*//*Label 1419*/ 53431, // Rule ID 862 // 22124 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 22125 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, 22126 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 22127 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 22128 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 22129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22132 // (intrinsic_wo_chain:{ *:[v4f16] } 234:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMAXNMPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) 22133 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv4f16, 22134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22135 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22137 GIR_EraseFromParent, /*InsnID*/0, 22138 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22139 // GIR_Coverage, 862, 22140 GIR_Done, 22141 // Label 1419: @53431 22142 GIM_Try, /*On fail goto*//*Label 1420*/ 53483, // Rule ID 863 // 22143 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 22144 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, 22145 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 22146 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 22147 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 22148 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22151 // (intrinsic_wo_chain:{ *:[v8f16] } 234:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMAXNMPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) 22152 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv8f16, 22153 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22155 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22156 GIR_EraseFromParent, /*InsnID*/0, 22157 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22158 // GIR_Coverage, 863, 22159 GIR_Done, 22160 // Label 1420: @53483 22161 GIM_Try, /*On fail goto*//*Label 1421*/ 53535, // Rule ID 864 // 22162 GIM_CheckFeatures, GIFBS_HasNEON, 22163 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, 22164 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 22165 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 22166 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 22167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22168 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22170 // (intrinsic_wo_chain:{ *:[v2f32] } 234:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMAXNMPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) 22171 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2f32, 22172 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22173 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22174 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22175 GIR_EraseFromParent, /*InsnID*/0, 22176 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22177 // GIR_Coverage, 864, 22178 GIR_Done, 22179 // Label 1421: @53535 22180 GIM_Try, /*On fail goto*//*Label 1422*/ 53587, // Rule ID 865 // 22181 GIM_CheckFeatures, GIFBS_HasNEON, 22182 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, 22183 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 22184 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 22185 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 22186 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22189 // (intrinsic_wo_chain:{ *:[v4f32] } 234:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMAXNMPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) 22190 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv4f32, 22191 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22192 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22193 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22194 GIR_EraseFromParent, /*InsnID*/0, 22195 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22196 // GIR_Coverage, 865, 22197 GIR_Done, 22198 // Label 1422: @53587 22199 GIM_Try, /*On fail goto*//*Label 1423*/ 53639, // Rule ID 866 // 22200 GIM_CheckFeatures, GIFBS_HasNEON, 22201 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, 22202 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 22203 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 22204 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 22205 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22207 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22208 // (intrinsic_wo_chain:{ *:[v2f64] } 234:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMAXNMPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) 22209 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2f64, 22210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22211 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22212 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22213 GIR_EraseFromParent, /*InsnID*/0, 22214 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22215 // GIR_Coverage, 866, 22216 GIR_Done, 22217 // Label 1423: @53639 22218 GIM_Try, /*On fail goto*//*Label 1424*/ 53691, // Rule ID 872 // 22219 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 22220 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, 22221 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 22222 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 22223 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 22224 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22227 // (intrinsic_wo_chain:{ *:[v4f16] } 236:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMAXPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) 22228 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv4f16, 22229 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22230 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22231 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22232 GIR_EraseFromParent, /*InsnID*/0, 22233 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22234 // GIR_Coverage, 872, 22235 GIR_Done, 22236 // Label 1424: @53691 22237 GIM_Try, /*On fail goto*//*Label 1425*/ 53743, // Rule ID 873 // 22238 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 22239 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, 22240 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 22241 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 22242 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 22243 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22244 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22246 // (intrinsic_wo_chain:{ *:[v8f16] } 236:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMAXPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) 22247 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv8f16, 22248 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22249 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22251 GIR_EraseFromParent, /*InsnID*/0, 22252 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22253 // GIR_Coverage, 873, 22254 GIR_Done, 22255 // Label 1425: @53743 22256 GIM_Try, /*On fail goto*//*Label 1426*/ 53795, // Rule ID 874 // 22257 GIM_CheckFeatures, GIFBS_HasNEON, 22258 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, 22259 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 22260 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 22261 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 22262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22265 // (intrinsic_wo_chain:{ *:[v2f32] } 236:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMAXPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) 22266 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2f32, 22267 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22268 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22270 GIR_EraseFromParent, /*InsnID*/0, 22271 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22272 // GIR_Coverage, 874, 22273 GIR_Done, 22274 // Label 1426: @53795 22275 GIM_Try, /*On fail goto*//*Label 1427*/ 53847, // Rule ID 875 // 22276 GIM_CheckFeatures, GIFBS_HasNEON, 22277 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, 22278 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 22279 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 22280 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 22281 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22282 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22284 // (intrinsic_wo_chain:{ *:[v4f32] } 236:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMAXPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) 22285 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv4f32, 22286 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22287 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22288 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22289 GIR_EraseFromParent, /*InsnID*/0, 22290 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22291 // GIR_Coverage, 875, 22292 GIR_Done, 22293 // Label 1427: @53847 22294 GIM_Try, /*On fail goto*//*Label 1428*/ 53899, // Rule ID 876 // 22295 GIM_CheckFeatures, GIFBS_HasNEON, 22296 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, 22297 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 22298 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 22299 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 22300 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22303 // (intrinsic_wo_chain:{ *:[v2f64] } 236:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMAXPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) 22304 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2f64, 22305 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22306 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22307 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22308 GIR_EraseFromParent, /*InsnID*/0, 22309 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22310 // GIR_Coverage, 876, 22311 GIR_Done, 22312 // Label 1428: @53899 22313 GIM_Try, /*On fail goto*//*Label 1429*/ 53951, // Rule ID 882 // 22314 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 22315 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, 22316 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 22317 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 22318 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 22319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22321 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22322 // (intrinsic_wo_chain:{ *:[v4f16] } 240:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMINNMPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) 22323 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv4f16, 22324 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22327 GIR_EraseFromParent, /*InsnID*/0, 22328 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22329 // GIR_Coverage, 882, 22330 GIR_Done, 22331 // Label 1429: @53951 22332 GIM_Try, /*On fail goto*//*Label 1430*/ 54003, // Rule ID 883 // 22333 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 22334 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, 22335 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 22336 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 22337 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 22338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22339 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22340 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22341 // (intrinsic_wo_chain:{ *:[v8f16] } 240:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMINNMPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) 22342 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv8f16, 22343 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22344 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22345 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22346 GIR_EraseFromParent, /*InsnID*/0, 22347 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22348 // GIR_Coverage, 883, 22349 GIR_Done, 22350 // Label 1430: @54003 22351 GIM_Try, /*On fail goto*//*Label 1431*/ 54055, // Rule ID 884 // 22352 GIM_CheckFeatures, GIFBS_HasNEON, 22353 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, 22354 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 22355 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 22356 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 22357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22360 // (intrinsic_wo_chain:{ *:[v2f32] } 240:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMINNMPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) 22361 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2f32, 22362 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22365 GIR_EraseFromParent, /*InsnID*/0, 22366 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22367 // GIR_Coverage, 884, 22368 GIR_Done, 22369 // Label 1431: @54055 22370 GIM_Try, /*On fail goto*//*Label 1432*/ 54107, // Rule ID 885 // 22371 GIM_CheckFeatures, GIFBS_HasNEON, 22372 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, 22373 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 22374 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 22375 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 22376 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22377 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22378 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22379 // (intrinsic_wo_chain:{ *:[v4f32] } 240:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMINNMPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) 22380 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv4f32, 22381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22384 GIR_EraseFromParent, /*InsnID*/0, 22385 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22386 // GIR_Coverage, 885, 22387 GIR_Done, 22388 // Label 1432: @54107 22389 GIM_Try, /*On fail goto*//*Label 1433*/ 54159, // Rule ID 886 // 22390 GIM_CheckFeatures, GIFBS_HasNEON, 22391 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, 22392 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 22393 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 22394 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 22395 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22398 // (intrinsic_wo_chain:{ *:[v2f64] } 240:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMINNMPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) 22399 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2f64, 22400 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22403 GIR_EraseFromParent, /*InsnID*/0, 22404 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22405 // GIR_Coverage, 886, 22406 GIR_Done, 22407 // Label 1433: @54159 22408 GIM_Try, /*On fail goto*//*Label 1434*/ 54211, // Rule ID 892 // 22409 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 22410 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, 22411 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 22412 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 22413 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 22414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22417 // (intrinsic_wo_chain:{ *:[v4f16] } 242:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMINPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) 22418 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv4f16, 22419 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22420 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22422 GIR_EraseFromParent, /*InsnID*/0, 22423 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22424 // GIR_Coverage, 892, 22425 GIR_Done, 22426 // Label 1434: @54211 22427 GIM_Try, /*On fail goto*//*Label 1435*/ 54263, // Rule ID 893 // 22428 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 22429 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, 22430 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 22431 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 22432 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 22433 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22434 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22436 // (intrinsic_wo_chain:{ *:[v8f16] } 242:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMINPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) 22437 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv8f16, 22438 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22439 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22441 GIR_EraseFromParent, /*InsnID*/0, 22442 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22443 // GIR_Coverage, 893, 22444 GIR_Done, 22445 // Label 1435: @54263 22446 GIM_Try, /*On fail goto*//*Label 1436*/ 54315, // Rule ID 894 // 22447 GIM_CheckFeatures, GIFBS_HasNEON, 22448 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, 22449 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 22450 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 22451 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 22452 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22453 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22454 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22455 // (intrinsic_wo_chain:{ *:[v2f32] } 242:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMINPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) 22456 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2f32, 22457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22458 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22459 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22460 GIR_EraseFromParent, /*InsnID*/0, 22461 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22462 // GIR_Coverage, 894, 22463 GIR_Done, 22464 // Label 1436: @54315 22465 GIM_Try, /*On fail goto*//*Label 1437*/ 54367, // Rule ID 895 // 22466 GIM_CheckFeatures, GIFBS_HasNEON, 22467 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, 22468 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 22469 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 22470 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 22471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22472 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22474 // (intrinsic_wo_chain:{ *:[v4f32] } 242:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMINPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) 22475 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv4f32, 22476 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22478 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22479 GIR_EraseFromParent, /*InsnID*/0, 22480 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22481 // GIR_Coverage, 895, 22482 GIR_Done, 22483 // Label 1437: @54367 22484 GIM_Try, /*On fail goto*//*Label 1438*/ 54419, // Rule ID 896 // 22485 GIM_CheckFeatures, GIFBS_HasNEON, 22486 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, 22487 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 22488 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 22489 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 22490 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22491 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22493 // (intrinsic_wo_chain:{ *:[v2f64] } 242:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMINPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) 22494 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2f64, 22495 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22496 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22497 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22498 GIR_EraseFromParent, /*InsnID*/0, 22499 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22500 // GIR_Coverage, 896, 22501 GIR_Done, 22502 // Label 1438: @54419 22503 GIM_Try, /*On fail goto*//*Label 1439*/ 54471, // Rule ID 912 // 22504 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 22505 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, 22506 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 22507 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 22508 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 22509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22510 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22511 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22512 // (intrinsic_wo_chain:{ *:[v4f16] } 244:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMULXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) 22513 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv4f16, 22514 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22515 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22516 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22517 GIR_EraseFromParent, /*InsnID*/0, 22518 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22519 // GIR_Coverage, 912, 22520 GIR_Done, 22521 // Label 1439: @54471 22522 GIM_Try, /*On fail goto*//*Label 1440*/ 54523, // Rule ID 913 // 22523 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 22524 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, 22525 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 22526 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 22527 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 22528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22530 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22531 // (intrinsic_wo_chain:{ *:[v8f16] } 244:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMULXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) 22532 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv8f16, 22533 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22534 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22536 GIR_EraseFromParent, /*InsnID*/0, 22537 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22538 // GIR_Coverage, 913, 22539 GIR_Done, 22540 // Label 1440: @54523 22541 GIM_Try, /*On fail goto*//*Label 1441*/ 54575, // Rule ID 914 // 22542 GIM_CheckFeatures, GIFBS_HasNEON, 22543 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, 22544 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 22545 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 22546 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 22547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22549 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22550 // (intrinsic_wo_chain:{ *:[v2f32] } 244:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMULXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) 22551 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv2f32, 22552 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22553 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22554 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22555 GIR_EraseFromParent, /*InsnID*/0, 22556 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22557 // GIR_Coverage, 914, 22558 GIR_Done, 22559 // Label 1441: @54575 22560 GIM_Try, /*On fail goto*//*Label 1442*/ 54627, // Rule ID 915 // 22561 GIM_CheckFeatures, GIFBS_HasNEON, 22562 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, 22563 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 22564 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 22565 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 22566 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22567 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22569 // (intrinsic_wo_chain:{ *:[v4f32] } 244:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMULXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) 22570 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv4f32, 22571 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22572 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22573 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22574 GIR_EraseFromParent, /*InsnID*/0, 22575 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22576 // GIR_Coverage, 915, 22577 GIR_Done, 22578 // Label 1442: @54627 22579 GIM_Try, /*On fail goto*//*Label 1443*/ 54679, // Rule ID 916 // 22580 GIM_CheckFeatures, GIFBS_HasNEON, 22581 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, 22582 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 22583 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 22584 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 22585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22587 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22588 // (intrinsic_wo_chain:{ *:[v2f64] } 244:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMULXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) 22589 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv2f64, 22590 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22591 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22592 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22593 GIR_EraseFromParent, /*InsnID*/0, 22594 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22595 // GIR_Coverage, 916, 22596 GIR_Done, 22597 // Label 1443: @54679 22598 GIM_Try, /*On fail goto*//*Label 1444*/ 54731, // Rule ID 922 // 22599 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 22600 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, 22601 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 22602 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 22603 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 22604 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22606 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22607 // (intrinsic_wo_chain:{ *:[v4f16] } 246:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FRECPSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) 22608 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv4f16, 22609 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22610 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22611 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22612 GIR_EraseFromParent, /*InsnID*/0, 22613 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22614 // GIR_Coverage, 922, 22615 GIR_Done, 22616 // Label 1444: @54731 22617 GIM_Try, /*On fail goto*//*Label 1445*/ 54783, // Rule ID 923 // 22618 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 22619 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, 22620 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 22621 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 22622 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 22623 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22624 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22626 // (intrinsic_wo_chain:{ *:[v8f16] } 246:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FRECPSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) 22627 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv8f16, 22628 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22629 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22630 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22631 GIR_EraseFromParent, /*InsnID*/0, 22632 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22633 // GIR_Coverage, 923, 22634 GIR_Done, 22635 // Label 1445: @54783 22636 GIM_Try, /*On fail goto*//*Label 1446*/ 54835, // Rule ID 924 // 22637 GIM_CheckFeatures, GIFBS_HasNEON, 22638 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, 22639 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 22640 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 22641 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 22642 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22643 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22644 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22645 // (intrinsic_wo_chain:{ *:[v2f32] } 246:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FRECPSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) 22646 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv2f32, 22647 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22648 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22649 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22650 GIR_EraseFromParent, /*InsnID*/0, 22651 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22652 // GIR_Coverage, 924, 22653 GIR_Done, 22654 // Label 1446: @54835 22655 GIM_Try, /*On fail goto*//*Label 1447*/ 54887, // Rule ID 925 // 22656 GIM_CheckFeatures, GIFBS_HasNEON, 22657 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, 22658 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 22659 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 22660 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 22661 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22662 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22663 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22664 // (intrinsic_wo_chain:{ *:[v4f32] } 246:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FRECPSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) 22665 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv4f32, 22666 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22667 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22668 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22669 GIR_EraseFromParent, /*InsnID*/0, 22670 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22671 // GIR_Coverage, 925, 22672 GIR_Done, 22673 // Label 1447: @54887 22674 GIM_Try, /*On fail goto*//*Label 1448*/ 54939, // Rule ID 926 // 22675 GIM_CheckFeatures, GIFBS_HasNEON, 22676 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, 22677 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 22678 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 22679 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 22680 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22681 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22683 // (intrinsic_wo_chain:{ *:[v2f64] } 246:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FRECPSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) 22684 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv2f64, 22685 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22686 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22688 GIR_EraseFromParent, /*InsnID*/0, 22689 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22690 // GIR_Coverage, 926, 22691 GIR_Done, 22692 // Label 1448: @54939 22693 GIM_Try, /*On fail goto*//*Label 1449*/ 54991, // Rule ID 927 // 22694 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 22695 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, 22696 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 22697 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 22698 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 22699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22702 // (intrinsic_wo_chain:{ *:[v4f16] } 250:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FRSQRTSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) 22703 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv4f16, 22704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22706 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22707 GIR_EraseFromParent, /*InsnID*/0, 22708 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22709 // GIR_Coverage, 927, 22710 GIR_Done, 22711 // Label 1449: @54991 22712 GIM_Try, /*On fail goto*//*Label 1450*/ 55043, // Rule ID 928 // 22713 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 22714 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, 22715 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 22716 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 22717 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 22718 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22719 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22720 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22721 // (intrinsic_wo_chain:{ *:[v8f16] } 250:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FRSQRTSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) 22722 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv8f16, 22723 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22724 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22725 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22726 GIR_EraseFromParent, /*InsnID*/0, 22727 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22728 // GIR_Coverage, 928, 22729 GIR_Done, 22730 // Label 1450: @55043 22731 GIM_Try, /*On fail goto*//*Label 1451*/ 55095, // Rule ID 929 // 22732 GIM_CheckFeatures, GIFBS_HasNEON, 22733 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, 22734 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 22735 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 22736 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 22737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22740 // (intrinsic_wo_chain:{ *:[v2f32] } 250:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FRSQRTSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) 22741 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv2f32, 22742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22744 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22745 GIR_EraseFromParent, /*InsnID*/0, 22746 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22747 // GIR_Coverage, 929, 22748 GIR_Done, 22749 // Label 1451: @55095 22750 GIM_Try, /*On fail goto*//*Label 1452*/ 55147, // Rule ID 930 // 22751 GIM_CheckFeatures, GIFBS_HasNEON, 22752 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, 22753 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 22754 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 22755 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 22756 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22759 // (intrinsic_wo_chain:{ *:[v4f32] } 250:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FRSQRTSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) 22760 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv4f32, 22761 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22762 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22764 GIR_EraseFromParent, /*InsnID*/0, 22765 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22766 // GIR_Coverage, 930, 22767 GIR_Done, 22768 // Label 1452: @55147 22769 GIM_Try, /*On fail goto*//*Label 1453*/ 55199, // Rule ID 931 // 22770 GIM_CheckFeatures, GIFBS_HasNEON, 22771 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, 22772 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 22773 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 22774 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 22775 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22776 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22778 // (intrinsic_wo_chain:{ *:[v2f64] } 250:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FRSQRTSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) 22779 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv2f64, 22780 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22781 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22782 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22783 GIR_EraseFromParent, /*InsnID*/0, 22784 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22785 // GIR_Coverage, 931, 22786 GIR_Done, 22787 // Label 1453: @55199 22788 GIM_Try, /*On fail goto*//*Label 1454*/ 55251, // Rule ID 955 // 22789 GIM_CheckFeatures, GIFBS_HasNEON, 22790 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_pmul, 22791 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 22792 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 22793 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 22794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22797 // (intrinsic_wo_chain:{ *:[v8i8] } 263:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (PMULv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 22798 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PMULv8i8, 22799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22800 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22801 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22802 GIR_EraseFromParent, /*InsnID*/0, 22803 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22804 // GIR_Coverage, 955, 22805 GIR_Done, 22806 // Label 1454: @55251 22807 GIM_Try, /*On fail goto*//*Label 1455*/ 55303, // Rule ID 956 // 22808 GIM_CheckFeatures, GIFBS_HasNEON, 22809 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_pmul, 22810 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 22811 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 22812 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 22813 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22814 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22816 // (intrinsic_wo_chain:{ *:[v16i8] } 263:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (PMULv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 22817 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PMULv16i8, 22818 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22819 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22820 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22821 GIR_EraseFromParent, /*InsnID*/0, 22822 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22823 // GIR_Coverage, 956, 22824 GIR_Done, 22825 // Label 1455: @55303 22826 GIM_Try, /*On fail goto*//*Label 1456*/ 55355, // Rule ID 963 // 22827 GIM_CheckFeatures, GIFBS_HasNEON, 22828 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, 22829 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 22830 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 22831 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 22832 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22833 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22834 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22835 // (intrinsic_wo_chain:{ *:[v8i8] } 270:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SABDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 22836 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv8i8, 22837 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22838 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22840 GIR_EraseFromParent, /*InsnID*/0, 22841 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22842 // GIR_Coverage, 963, 22843 GIR_Done, 22844 // Label 1456: @55355 22845 GIM_Try, /*On fail goto*//*Label 1457*/ 55407, // Rule ID 964 // 22846 GIM_CheckFeatures, GIFBS_HasNEON, 22847 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, 22848 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 22849 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 22850 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 22851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22853 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22854 // (intrinsic_wo_chain:{ *:[v16i8] } 270:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SABDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 22855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv16i8, 22856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22857 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22859 GIR_EraseFromParent, /*InsnID*/0, 22860 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22861 // GIR_Coverage, 964, 22862 GIR_Done, 22863 // Label 1457: @55407 22864 GIM_Try, /*On fail goto*//*Label 1458*/ 55459, // Rule ID 965 // 22865 GIM_CheckFeatures, GIFBS_HasNEON, 22866 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, 22867 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 22868 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 22869 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 22870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22873 // (intrinsic_wo_chain:{ *:[v4i16] } 270:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SABDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 22874 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv4i16, 22875 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22876 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22878 GIR_EraseFromParent, /*InsnID*/0, 22879 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22880 // GIR_Coverage, 965, 22881 GIR_Done, 22882 // Label 1458: @55459 22883 GIM_Try, /*On fail goto*//*Label 1459*/ 55511, // Rule ID 966 // 22884 GIM_CheckFeatures, GIFBS_HasNEON, 22885 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, 22886 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 22887 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 22888 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 22889 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22890 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22892 // (intrinsic_wo_chain:{ *:[v8i16] } 270:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SABDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 22893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv8i16, 22894 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22897 GIR_EraseFromParent, /*InsnID*/0, 22898 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22899 // GIR_Coverage, 966, 22900 GIR_Done, 22901 // Label 1459: @55511 22902 GIM_Try, /*On fail goto*//*Label 1460*/ 55563, // Rule ID 967 // 22903 GIM_CheckFeatures, GIFBS_HasNEON, 22904 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, 22905 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 22906 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 22907 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 22908 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22909 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22910 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22911 // (intrinsic_wo_chain:{ *:[v2i32] } 270:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SABDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 22912 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv2i32, 22913 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22914 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22915 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22916 GIR_EraseFromParent, /*InsnID*/0, 22917 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22918 // GIR_Coverage, 967, 22919 GIR_Done, 22920 // Label 1460: @55563 22921 GIM_Try, /*On fail goto*//*Label 1461*/ 55615, // Rule ID 968 // 22922 GIM_CheckFeatures, GIFBS_HasNEON, 22923 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, 22924 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 22925 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 22926 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 22927 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22928 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22930 // (intrinsic_wo_chain:{ *:[v4i32] } 270:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SABDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 22931 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv4i32, 22932 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22934 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22935 GIR_EraseFromParent, /*InsnID*/0, 22936 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22937 // GIR_Coverage, 968, 22938 GIR_Done, 22939 // Label 1461: @55615 22940 GIM_Try, /*On fail goto*//*Label 1462*/ 55667, // Rule ID 969 // 22941 GIM_CheckFeatures, GIFBS_HasNEON, 22942 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shadd, 22943 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 22944 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 22945 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 22946 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22949 // (intrinsic_wo_chain:{ *:[v8i8] } 278:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SHADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 22950 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHADDv8i8, 22951 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22952 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22954 GIR_EraseFromParent, /*InsnID*/0, 22955 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22956 // GIR_Coverage, 969, 22957 GIR_Done, 22958 // Label 1462: @55667 22959 GIM_Try, /*On fail goto*//*Label 1463*/ 55719, // Rule ID 970 // 22960 GIM_CheckFeatures, GIFBS_HasNEON, 22961 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shadd, 22962 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 22963 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 22964 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 22965 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 22966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 22967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 22968 // (intrinsic_wo_chain:{ *:[v16i8] } 278:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SHADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 22969 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHADDv16i8, 22970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22971 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22973 GIR_EraseFromParent, /*InsnID*/0, 22974 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22975 // GIR_Coverage, 970, 22976 GIR_Done, 22977 // Label 1463: @55719 22978 GIM_Try, /*On fail goto*//*Label 1464*/ 55771, // Rule ID 971 // 22979 GIM_CheckFeatures, GIFBS_HasNEON, 22980 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shadd, 22981 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 22982 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 22983 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 22984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 22985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 22986 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 22987 // (intrinsic_wo_chain:{ *:[v4i16] } 278:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SHADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 22988 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHADDv4i16, 22989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 22990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 22991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 22992 GIR_EraseFromParent, /*InsnID*/0, 22993 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22994 // GIR_Coverage, 971, 22995 GIR_Done, 22996 // Label 1464: @55771 22997 GIM_Try, /*On fail goto*//*Label 1465*/ 55823, // Rule ID 972 // 22998 GIM_CheckFeatures, GIFBS_HasNEON, 22999 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shadd, 23000 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 23001 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 23002 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 23003 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23006 // (intrinsic_wo_chain:{ *:[v8i16] } 278:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SHADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 23007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHADDv8i16, 23008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23011 GIR_EraseFromParent, /*InsnID*/0, 23012 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23013 // GIR_Coverage, 972, 23014 GIR_Done, 23015 // Label 1465: @55823 23016 GIM_Try, /*On fail goto*//*Label 1466*/ 55875, // Rule ID 973 // 23017 GIM_CheckFeatures, GIFBS_HasNEON, 23018 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shadd, 23019 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 23020 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 23021 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 23022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23023 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23024 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23025 // (intrinsic_wo_chain:{ *:[v2i32] } 278:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SHADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 23026 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHADDv2i32, 23027 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23028 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23030 GIR_EraseFromParent, /*InsnID*/0, 23031 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23032 // GIR_Coverage, 973, 23033 GIR_Done, 23034 // Label 1466: @55875 23035 GIM_Try, /*On fail goto*//*Label 1467*/ 55927, // Rule ID 974 // 23036 GIM_CheckFeatures, GIFBS_HasNEON, 23037 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shadd, 23038 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 23039 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 23040 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 23041 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23044 // (intrinsic_wo_chain:{ *:[v4i32] } 278:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 23045 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHADDv4i32, 23046 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23049 GIR_EraseFromParent, /*InsnID*/0, 23050 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23051 // GIR_Coverage, 974, 23052 GIR_Done, 23053 // Label 1467: @55927 23054 GIM_Try, /*On fail goto*//*Label 1468*/ 55979, // Rule ID 975 // 23055 GIM_CheckFeatures, GIFBS_HasNEON, 23056 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, 23057 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 23058 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 23059 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 23060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23063 // (intrinsic_wo_chain:{ *:[v8i8] } 280:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SHSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 23064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv8i8, 23065 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23066 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23067 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23068 GIR_EraseFromParent, /*InsnID*/0, 23069 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23070 // GIR_Coverage, 975, 23071 GIR_Done, 23072 // Label 1468: @55979 23073 GIM_Try, /*On fail goto*//*Label 1469*/ 56031, // Rule ID 976 // 23074 GIM_CheckFeatures, GIFBS_HasNEON, 23075 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, 23076 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 23077 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 23078 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 23079 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23080 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23081 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23082 // (intrinsic_wo_chain:{ *:[v16i8] } 280:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SHSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 23083 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv16i8, 23084 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23085 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23087 GIR_EraseFromParent, /*InsnID*/0, 23088 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23089 // GIR_Coverage, 976, 23090 GIR_Done, 23091 // Label 1469: @56031 23092 GIM_Try, /*On fail goto*//*Label 1470*/ 56083, // Rule ID 977 // 23093 GIM_CheckFeatures, GIFBS_HasNEON, 23094 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, 23095 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 23096 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 23097 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 23098 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23101 // (intrinsic_wo_chain:{ *:[v4i16] } 280:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SHSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 23102 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv4i16, 23103 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23104 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23105 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23106 GIR_EraseFromParent, /*InsnID*/0, 23107 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23108 // GIR_Coverage, 977, 23109 GIR_Done, 23110 // Label 1470: @56083 23111 GIM_Try, /*On fail goto*//*Label 1471*/ 56135, // Rule ID 978 // 23112 GIM_CheckFeatures, GIFBS_HasNEON, 23113 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, 23114 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 23115 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 23116 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 23117 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23119 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23120 // (intrinsic_wo_chain:{ *:[v8i16] } 280:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SHSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 23121 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv8i16, 23122 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23123 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23124 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23125 GIR_EraseFromParent, /*InsnID*/0, 23126 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23127 // GIR_Coverage, 978, 23128 GIR_Done, 23129 // Label 1471: @56135 23130 GIM_Try, /*On fail goto*//*Label 1472*/ 56187, // Rule ID 979 // 23131 GIM_CheckFeatures, GIFBS_HasNEON, 23132 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, 23133 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 23134 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 23135 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 23136 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23139 // (intrinsic_wo_chain:{ *:[v2i32] } 280:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SHSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 23140 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv2i32, 23141 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23142 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23144 GIR_EraseFromParent, /*InsnID*/0, 23145 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23146 // GIR_Coverage, 979, 23147 GIR_Done, 23148 // Label 1472: @56187 23149 GIM_Try, /*On fail goto*//*Label 1473*/ 56239, // Rule ID 980 // 23150 GIM_CheckFeatures, GIFBS_HasNEON, 23151 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, 23152 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 23153 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 23154 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 23155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23158 // (intrinsic_wo_chain:{ *:[v4i32] } 280:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 23159 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv4i32, 23160 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23161 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23163 GIR_EraseFromParent, /*InsnID*/0, 23164 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23165 // GIR_Coverage, 980, 23166 GIR_Done, 23167 // Label 1473: @56239 23168 GIM_Try, /*On fail goto*//*Label 1474*/ 56291, // Rule ID 981 // 23169 GIM_CheckFeatures, GIFBS_HasNEON, 23170 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, 23171 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 23172 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 23173 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 23174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23175 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23177 // (intrinsic_wo_chain:{ *:[v8i8] } 282:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMAXPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 23178 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv8i8, 23179 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23180 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23181 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23182 GIR_EraseFromParent, /*InsnID*/0, 23183 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23184 // GIR_Coverage, 981, 23185 GIR_Done, 23186 // Label 1474: @56291 23187 GIM_Try, /*On fail goto*//*Label 1475*/ 56343, // Rule ID 982 // 23188 GIM_CheckFeatures, GIFBS_HasNEON, 23189 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, 23190 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 23191 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 23192 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 23193 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23194 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23196 // (intrinsic_wo_chain:{ *:[v16i8] } 282:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMAXPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 23197 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv16i8, 23198 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23199 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23200 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23201 GIR_EraseFromParent, /*InsnID*/0, 23202 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23203 // GIR_Coverage, 982, 23204 GIR_Done, 23205 // Label 1475: @56343 23206 GIM_Try, /*On fail goto*//*Label 1476*/ 56395, // Rule ID 983 // 23207 GIM_CheckFeatures, GIFBS_HasNEON, 23208 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, 23209 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 23210 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 23211 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 23212 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23213 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23215 // (intrinsic_wo_chain:{ *:[v4i16] } 282:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMAXPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 23216 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv4i16, 23217 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23218 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23219 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23220 GIR_EraseFromParent, /*InsnID*/0, 23221 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23222 // GIR_Coverage, 983, 23223 GIR_Done, 23224 // Label 1476: @56395 23225 GIM_Try, /*On fail goto*//*Label 1477*/ 56447, // Rule ID 984 // 23226 GIM_CheckFeatures, GIFBS_HasNEON, 23227 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, 23228 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 23229 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 23230 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 23231 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23232 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23234 // (intrinsic_wo_chain:{ *:[v8i16] } 282:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SMAXPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 23235 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv8i16, 23236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23239 GIR_EraseFromParent, /*InsnID*/0, 23240 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23241 // GIR_Coverage, 984, 23242 GIR_Done, 23243 // Label 1477: @56447 23244 GIM_Try, /*On fail goto*//*Label 1478*/ 56499, // Rule ID 985 // 23245 GIM_CheckFeatures, GIFBS_HasNEON, 23246 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, 23247 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 23248 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 23249 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 23250 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23252 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23253 // (intrinsic_wo_chain:{ *:[v2i32] } 282:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMAXPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 23254 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv2i32, 23255 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23256 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23257 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23258 GIR_EraseFromParent, /*InsnID*/0, 23259 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23260 // GIR_Coverage, 985, 23261 GIR_Done, 23262 // Label 1478: @56499 23263 GIM_Try, /*On fail goto*//*Label 1479*/ 56551, // Rule ID 986 // 23264 GIM_CheckFeatures, GIFBS_HasNEON, 23265 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, 23266 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 23267 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 23268 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 23269 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23270 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23272 // (intrinsic_wo_chain:{ *:[v4i32] } 282:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SMAXPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 23273 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv4i32, 23274 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23275 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23276 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23277 GIR_EraseFromParent, /*InsnID*/0, 23278 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23279 // GIR_Coverage, 986, 23280 GIR_Done, 23281 // Label 1479: @56551 23282 GIM_Try, /*On fail goto*//*Label 1480*/ 56603, // Rule ID 993 // 23283 GIM_CheckFeatures, GIFBS_HasNEON, 23284 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, 23285 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 23286 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 23287 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 23288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23291 // (intrinsic_wo_chain:{ *:[v8i8] } 285:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMINPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 23292 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv8i8, 23293 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23294 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23295 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23296 GIR_EraseFromParent, /*InsnID*/0, 23297 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23298 // GIR_Coverage, 993, 23299 GIR_Done, 23300 // Label 1480: @56603 23301 GIM_Try, /*On fail goto*//*Label 1481*/ 56655, // Rule ID 994 // 23302 GIM_CheckFeatures, GIFBS_HasNEON, 23303 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, 23304 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 23305 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 23306 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 23307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23310 // (intrinsic_wo_chain:{ *:[v16i8] } 285:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMINPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 23311 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv16i8, 23312 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23313 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23315 GIR_EraseFromParent, /*InsnID*/0, 23316 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23317 // GIR_Coverage, 994, 23318 GIR_Done, 23319 // Label 1481: @56655 23320 GIM_Try, /*On fail goto*//*Label 1482*/ 56707, // Rule ID 995 // 23321 GIM_CheckFeatures, GIFBS_HasNEON, 23322 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, 23323 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 23324 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 23325 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 23326 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23327 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23329 // (intrinsic_wo_chain:{ *:[v4i16] } 285:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMINPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 23330 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv4i16, 23331 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23332 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23334 GIR_EraseFromParent, /*InsnID*/0, 23335 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23336 // GIR_Coverage, 995, 23337 GIR_Done, 23338 // Label 1482: @56707 23339 GIM_Try, /*On fail goto*//*Label 1483*/ 56759, // Rule ID 996 // 23340 GIM_CheckFeatures, GIFBS_HasNEON, 23341 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, 23342 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 23343 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 23344 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 23345 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23346 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23347 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23348 // (intrinsic_wo_chain:{ *:[v8i16] } 285:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SMINPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 23349 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv8i16, 23350 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23351 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23352 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23353 GIR_EraseFromParent, /*InsnID*/0, 23354 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23355 // GIR_Coverage, 996, 23356 GIR_Done, 23357 // Label 1483: @56759 23358 GIM_Try, /*On fail goto*//*Label 1484*/ 56811, // Rule ID 997 // 23359 GIM_CheckFeatures, GIFBS_HasNEON, 23360 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, 23361 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 23362 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 23363 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 23364 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23366 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23367 // (intrinsic_wo_chain:{ *:[v2i32] } 285:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMINPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 23368 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv2i32, 23369 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23370 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23371 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23372 GIR_EraseFromParent, /*InsnID*/0, 23373 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23374 // GIR_Coverage, 997, 23375 GIR_Done, 23376 // Label 1484: @56811 23377 GIM_Try, /*On fail goto*//*Label 1485*/ 56863, // Rule ID 998 // 23378 GIM_CheckFeatures, GIFBS_HasNEON, 23379 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, 23380 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 23381 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 23382 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 23383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23386 // (intrinsic_wo_chain:{ *:[v4i32] } 285:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SMINPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 23387 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv4i32, 23388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23389 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23390 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23391 GIR_EraseFromParent, /*InsnID*/0, 23392 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23393 // GIR_Coverage, 998, 23394 GIR_Done, 23395 // Label 1485: @56863 23396 GIM_Try, /*On fail goto*//*Label 1486*/ 56915, // Rule ID 1005 // 23397 GIM_CheckFeatures, GIFBS_HasNEON, 23398 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, 23399 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 23400 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 23401 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 23402 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23405 // (intrinsic_wo_chain:{ *:[v8i8] } 289:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 23406 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv8i8, 23407 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23408 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23409 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23410 GIR_EraseFromParent, /*InsnID*/0, 23411 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23412 // GIR_Coverage, 1005, 23413 GIR_Done, 23414 // Label 1486: @56915 23415 GIM_Try, /*On fail goto*//*Label 1487*/ 56967, // Rule ID 1006 // 23416 GIM_CheckFeatures, GIFBS_HasNEON, 23417 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, 23418 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 23419 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 23420 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 23421 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23422 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23424 // (intrinsic_wo_chain:{ *:[v16i8] } 289:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 23425 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv16i8, 23426 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23427 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23428 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23429 GIR_EraseFromParent, /*InsnID*/0, 23430 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23431 // GIR_Coverage, 1006, 23432 GIR_Done, 23433 // Label 1487: @56967 23434 GIM_Try, /*On fail goto*//*Label 1488*/ 57019, // Rule ID 1007 // 23435 GIM_CheckFeatures, GIFBS_HasNEON, 23436 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, 23437 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 23438 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 23439 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 23440 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23442 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23443 // (intrinsic_wo_chain:{ *:[v4i16] } 289:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 23444 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv4i16, 23445 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23447 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23448 GIR_EraseFromParent, /*InsnID*/0, 23449 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23450 // GIR_Coverage, 1007, 23451 GIR_Done, 23452 // Label 1488: @57019 23453 GIM_Try, /*On fail goto*//*Label 1489*/ 57071, // Rule ID 1008 // 23454 GIM_CheckFeatures, GIFBS_HasNEON, 23455 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, 23456 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 23457 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 23458 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 23459 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23460 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23461 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23462 // (intrinsic_wo_chain:{ *:[v8i16] } 289:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 23463 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv8i16, 23464 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23465 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23466 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23467 GIR_EraseFromParent, /*InsnID*/0, 23468 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23469 // GIR_Coverage, 1008, 23470 GIR_Done, 23471 // Label 1489: @57071 23472 GIM_Try, /*On fail goto*//*Label 1490*/ 57123, // Rule ID 1009 // 23473 GIM_CheckFeatures, GIFBS_HasNEON, 23474 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, 23475 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 23476 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 23477 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 23478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23481 // (intrinsic_wo_chain:{ *:[v2i32] } 289:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 23482 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv2i32, 23483 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23486 GIR_EraseFromParent, /*InsnID*/0, 23487 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23488 // GIR_Coverage, 1009, 23489 GIR_Done, 23490 // Label 1490: @57123 23491 GIM_Try, /*On fail goto*//*Label 1491*/ 57175, // Rule ID 1010 // 23492 GIM_CheckFeatures, GIFBS_HasNEON, 23493 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, 23494 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 23495 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 23496 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 23497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23500 // (intrinsic_wo_chain:{ *:[v4i32] } 289:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 23501 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv4i32, 23502 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23505 GIR_EraseFromParent, /*InsnID*/0, 23506 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23507 // GIR_Coverage, 1010, 23508 GIR_Done, 23509 // Label 1491: @57175 23510 GIM_Try, /*On fail goto*//*Label 1492*/ 57227, // Rule ID 1011 // 23511 GIM_CheckFeatures, GIFBS_HasNEON, 23512 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, 23513 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 23514 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 23515 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 23516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23519 // (intrinsic_wo_chain:{ *:[v2i64] } 289:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) 23520 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv2i64, 23521 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23522 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23523 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23524 GIR_EraseFromParent, /*InsnID*/0, 23525 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23526 // GIR_Coverage, 1011, 23527 GIR_Done, 23528 // Label 1492: @57227 23529 GIM_Try, /*On fail goto*//*Label 1493*/ 57279, // Rule ID 1012 // 23530 GIM_CheckFeatures, GIFBS_HasNEON, 23531 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, 23532 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 23533 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 23534 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 23535 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23538 // (intrinsic_wo_chain:{ *:[v4i16] } 290:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQDMULHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 23539 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv4i16, 23540 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23541 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23543 GIR_EraseFromParent, /*InsnID*/0, 23544 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23545 // GIR_Coverage, 1012, 23546 GIR_Done, 23547 // Label 1493: @57279 23548 GIM_Try, /*On fail goto*//*Label 1494*/ 57331, // Rule ID 1013 // 23549 GIM_CheckFeatures, GIFBS_HasNEON, 23550 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, 23551 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 23552 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 23553 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 23554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23555 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23557 // (intrinsic_wo_chain:{ *:[v8i16] } 290:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQDMULHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 23558 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv8i16, 23559 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23560 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23562 GIR_EraseFromParent, /*InsnID*/0, 23563 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23564 // GIR_Coverage, 1013, 23565 GIR_Done, 23566 // Label 1494: @57331 23567 GIM_Try, /*On fail goto*//*Label 1495*/ 57383, // Rule ID 1014 // 23568 GIM_CheckFeatures, GIFBS_HasNEON, 23569 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, 23570 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 23571 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 23572 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 23573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23576 // (intrinsic_wo_chain:{ *:[v2i32] } 290:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQDMULHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 23577 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv2i32, 23578 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23579 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23580 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23581 GIR_EraseFromParent, /*InsnID*/0, 23582 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23583 // GIR_Coverage, 1014, 23584 GIR_Done, 23585 // Label 1495: @57383 23586 GIM_Try, /*On fail goto*//*Label 1496*/ 57435, // Rule ID 1015 // 23587 GIM_CheckFeatures, GIFBS_HasNEON, 23588 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, 23589 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 23590 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 23591 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 23592 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23595 // (intrinsic_wo_chain:{ *:[v4i32] } 290:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQDMULHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 23596 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv4i32, 23597 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23598 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23599 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23600 GIR_EraseFromParent, /*InsnID*/0, 23601 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23602 // GIR_Coverage, 1015, 23603 GIR_Done, 23604 // Label 1496: @57435 23605 GIM_Try, /*On fail goto*//*Label 1497*/ 57487, // Rule ID 1016 // 23606 GIM_CheckFeatures, GIFBS_HasNEON, 23607 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, 23608 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 23609 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 23610 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 23611 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23614 // (intrinsic_wo_chain:{ *:[v4i16] } 294:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQRDMULHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 23615 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv4i16, 23616 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23617 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23619 GIR_EraseFromParent, /*InsnID*/0, 23620 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23621 // GIR_Coverage, 1016, 23622 GIR_Done, 23623 // Label 1497: @57487 23624 GIM_Try, /*On fail goto*//*Label 1498*/ 57539, // Rule ID 1017 // 23625 GIM_CheckFeatures, GIFBS_HasNEON, 23626 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, 23627 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 23628 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 23629 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 23630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23632 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23633 // (intrinsic_wo_chain:{ *:[v8i16] } 294:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQRDMULHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 23634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv8i16, 23635 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23636 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23637 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23638 GIR_EraseFromParent, /*InsnID*/0, 23639 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23640 // GIR_Coverage, 1017, 23641 GIR_Done, 23642 // Label 1498: @57539 23643 GIM_Try, /*On fail goto*//*Label 1499*/ 57591, // Rule ID 1018 // 23644 GIM_CheckFeatures, GIFBS_HasNEON, 23645 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, 23646 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 23647 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 23648 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 23649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23652 // (intrinsic_wo_chain:{ *:[v2i32] } 294:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQRDMULHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 23653 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv2i32, 23654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23655 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23656 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23657 GIR_EraseFromParent, /*InsnID*/0, 23658 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23659 // GIR_Coverage, 1018, 23660 GIR_Done, 23661 // Label 1499: @57591 23662 GIM_Try, /*On fail goto*//*Label 1500*/ 57643, // Rule ID 1019 // 23663 GIM_CheckFeatures, GIFBS_HasNEON, 23664 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, 23665 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 23666 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 23667 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 23668 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23671 // (intrinsic_wo_chain:{ *:[v4i32] } 294:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQRDMULHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 23672 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv4i32, 23673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23676 GIR_EraseFromParent, /*InsnID*/0, 23677 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23678 // GIR_Coverage, 1019, 23679 GIR_Done, 23680 // Label 1500: @57643 23681 GIM_Try, /*On fail goto*//*Label 1501*/ 57695, // Rule ID 1020 // 23682 GIM_CheckFeatures, GIFBS_HasNEON, 23683 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, 23684 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 23685 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 23686 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 23687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23689 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23690 // (intrinsic_wo_chain:{ *:[v8i8] } 295:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 23691 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv8i8, 23692 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23693 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23694 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23695 GIR_EraseFromParent, /*InsnID*/0, 23696 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23697 // GIR_Coverage, 1020, 23698 GIR_Done, 23699 // Label 1501: @57695 23700 GIM_Try, /*On fail goto*//*Label 1502*/ 57747, // Rule ID 1021 // 23701 GIM_CheckFeatures, GIFBS_HasNEON, 23702 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, 23703 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 23704 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 23705 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 23706 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23707 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23708 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23709 // (intrinsic_wo_chain:{ *:[v16i8] } 295:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 23710 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv16i8, 23711 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23712 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23713 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23714 GIR_EraseFromParent, /*InsnID*/0, 23715 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23716 // GIR_Coverage, 1021, 23717 GIR_Done, 23718 // Label 1502: @57747 23719 GIM_Try, /*On fail goto*//*Label 1503*/ 57799, // Rule ID 1022 // 23720 GIM_CheckFeatures, GIFBS_HasNEON, 23721 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, 23722 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 23723 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 23724 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 23725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23726 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23728 // (intrinsic_wo_chain:{ *:[v4i16] } 295:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 23729 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv4i16, 23730 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23731 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23732 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23733 GIR_EraseFromParent, /*InsnID*/0, 23734 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23735 // GIR_Coverage, 1022, 23736 GIR_Done, 23737 // Label 1503: @57799 23738 GIM_Try, /*On fail goto*//*Label 1504*/ 57851, // Rule ID 1023 // 23739 GIM_CheckFeatures, GIFBS_HasNEON, 23740 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, 23741 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 23742 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 23743 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 23744 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23745 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23746 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23747 // (intrinsic_wo_chain:{ *:[v8i16] } 295:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 23748 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv8i16, 23749 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23750 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23751 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23752 GIR_EraseFromParent, /*InsnID*/0, 23753 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23754 // GIR_Coverage, 1023, 23755 GIR_Done, 23756 // Label 1504: @57851 23757 GIM_Try, /*On fail goto*//*Label 1505*/ 57903, // Rule ID 1024 // 23758 GIM_CheckFeatures, GIFBS_HasNEON, 23759 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, 23760 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 23761 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 23762 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 23763 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23766 // (intrinsic_wo_chain:{ *:[v2i32] } 295:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 23767 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv2i32, 23768 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23771 GIR_EraseFromParent, /*InsnID*/0, 23772 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23773 // GIR_Coverage, 1024, 23774 GIR_Done, 23775 // Label 1505: @57903 23776 GIM_Try, /*On fail goto*//*Label 1506*/ 57955, // Rule ID 1025 // 23777 GIM_CheckFeatures, GIFBS_HasNEON, 23778 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, 23779 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 23780 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 23781 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 23782 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23783 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23784 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23785 // (intrinsic_wo_chain:{ *:[v4i32] } 295:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 23786 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv4i32, 23787 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23788 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23789 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23790 GIR_EraseFromParent, /*InsnID*/0, 23791 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23792 // GIR_Coverage, 1025, 23793 GIR_Done, 23794 // Label 1506: @57955 23795 GIM_Try, /*On fail goto*//*Label 1507*/ 58007, // Rule ID 1026 // 23796 GIM_CheckFeatures, GIFBS_HasNEON, 23797 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, 23798 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 23799 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 23800 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 23801 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23802 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23804 // (intrinsic_wo_chain:{ *:[v2i64] } 295:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) 23805 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv2i64, 23806 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23808 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23809 GIR_EraseFromParent, /*InsnID*/0, 23810 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23811 // GIR_Coverage, 1026, 23812 GIR_Done, 23813 // Label 1507: @58007 23814 GIM_Try, /*On fail goto*//*Label 1508*/ 58059, // Rule ID 1027 // 23815 GIM_CheckFeatures, GIFBS_HasNEON, 23816 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, 23817 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 23818 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 23819 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 23820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23822 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23823 // (intrinsic_wo_chain:{ *:[v8i8] } 298:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 23824 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv8i8, 23825 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23826 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23828 GIR_EraseFromParent, /*InsnID*/0, 23829 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23830 // GIR_Coverage, 1027, 23831 GIR_Done, 23832 // Label 1508: @58059 23833 GIM_Try, /*On fail goto*//*Label 1509*/ 58111, // Rule ID 1028 // 23834 GIM_CheckFeatures, GIFBS_HasNEON, 23835 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, 23836 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 23837 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 23838 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 23839 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23840 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23841 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23842 // (intrinsic_wo_chain:{ *:[v16i8] } 298:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 23843 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv16i8, 23844 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23845 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23846 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23847 GIR_EraseFromParent, /*InsnID*/0, 23848 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23849 // GIR_Coverage, 1028, 23850 GIR_Done, 23851 // Label 1509: @58111 23852 GIM_Try, /*On fail goto*//*Label 1510*/ 58163, // Rule ID 1029 // 23853 GIM_CheckFeatures, GIFBS_HasNEON, 23854 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, 23855 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 23856 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 23857 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 23858 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23861 // (intrinsic_wo_chain:{ *:[v4i16] } 298:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 23862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv4i16, 23863 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23866 GIR_EraseFromParent, /*InsnID*/0, 23867 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23868 // GIR_Coverage, 1029, 23869 GIR_Done, 23870 // Label 1510: @58163 23871 GIM_Try, /*On fail goto*//*Label 1511*/ 58215, // Rule ID 1030 // 23872 GIM_CheckFeatures, GIFBS_HasNEON, 23873 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, 23874 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 23875 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 23876 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 23877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23879 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23880 // (intrinsic_wo_chain:{ *:[v8i16] } 298:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 23881 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv8i16, 23882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23883 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23884 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23885 GIR_EraseFromParent, /*InsnID*/0, 23886 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23887 // GIR_Coverage, 1030, 23888 GIR_Done, 23889 // Label 1511: @58215 23890 GIM_Try, /*On fail goto*//*Label 1512*/ 58267, // Rule ID 1031 // 23891 GIM_CheckFeatures, GIFBS_HasNEON, 23892 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, 23893 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 23894 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 23895 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 23896 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23897 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23899 // (intrinsic_wo_chain:{ *:[v2i32] } 298:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 23900 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv2i32, 23901 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23902 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23904 GIR_EraseFromParent, /*InsnID*/0, 23905 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23906 // GIR_Coverage, 1031, 23907 GIR_Done, 23908 // Label 1512: @58267 23909 GIM_Try, /*On fail goto*//*Label 1513*/ 58319, // Rule ID 1032 // 23910 GIM_CheckFeatures, GIFBS_HasNEON, 23911 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, 23912 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 23913 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 23914 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 23915 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23918 // (intrinsic_wo_chain:{ *:[v4i32] } 298:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 23919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv4i32, 23920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23922 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23923 GIR_EraseFromParent, /*InsnID*/0, 23924 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23925 // GIR_Coverage, 1032, 23926 GIR_Done, 23927 // Label 1513: @58319 23928 GIM_Try, /*On fail goto*//*Label 1514*/ 58371, // Rule ID 1033 // 23929 GIM_CheckFeatures, GIFBS_HasNEON, 23930 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, 23931 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 23932 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 23933 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 23934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23936 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23937 // (intrinsic_wo_chain:{ *:[v2i64] } 298:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) 23938 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv2i64, 23939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23940 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23941 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23942 GIR_EraseFromParent, /*InsnID*/0, 23943 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23944 // GIR_Coverage, 1033, 23945 GIR_Done, 23946 // Label 1514: @58371 23947 GIM_Try, /*On fail goto*//*Label 1515*/ 58423, // Rule ID 1034 // 23948 GIM_CheckFeatures, GIFBS_HasNEON, 23949 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, 23950 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 23951 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 23952 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 23953 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23956 // (intrinsic_wo_chain:{ *:[v8i8] } 302:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 23957 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv8i8, 23958 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23959 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23960 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23961 GIR_EraseFromParent, /*InsnID*/0, 23962 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23963 // GIR_Coverage, 1034, 23964 GIR_Done, 23965 // Label 1515: @58423 23966 GIM_Try, /*On fail goto*//*Label 1516*/ 58475, // Rule ID 1035 // 23967 GIM_CheckFeatures, GIFBS_HasNEON, 23968 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, 23969 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 23970 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 23971 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 23972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 23973 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 23974 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 23975 // (intrinsic_wo_chain:{ *:[v16i8] } 302:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 23976 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv16i8, 23977 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23978 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23979 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23980 GIR_EraseFromParent, /*InsnID*/0, 23981 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23982 // GIR_Coverage, 1035, 23983 GIR_Done, 23984 // Label 1516: @58475 23985 GIM_Try, /*On fail goto*//*Label 1517*/ 58527, // Rule ID 1036 // 23986 GIM_CheckFeatures, GIFBS_HasNEON, 23987 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, 23988 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 23989 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 23990 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 23991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 23992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 23993 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 23994 // (intrinsic_wo_chain:{ *:[v4i16] } 302:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 23995 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv4i16, 23996 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 23997 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 23998 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 23999 GIR_EraseFromParent, /*InsnID*/0, 24000 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24001 // GIR_Coverage, 1036, 24002 GIR_Done, 24003 // Label 1517: @58527 24004 GIM_Try, /*On fail goto*//*Label 1518*/ 58579, // Rule ID 1037 // 24005 GIM_CheckFeatures, GIFBS_HasNEON, 24006 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, 24007 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 24008 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 24009 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 24010 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24011 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24012 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24013 // (intrinsic_wo_chain:{ *:[v8i16] } 302:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 24014 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv8i16, 24015 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24016 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24017 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24018 GIR_EraseFromParent, /*InsnID*/0, 24019 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24020 // GIR_Coverage, 1037, 24021 GIR_Done, 24022 // Label 1518: @58579 24023 GIM_Try, /*On fail goto*//*Label 1519*/ 58631, // Rule ID 1038 // 24024 GIM_CheckFeatures, GIFBS_HasNEON, 24025 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, 24026 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 24027 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 24028 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 24029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24030 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24031 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24032 // (intrinsic_wo_chain:{ *:[v2i32] } 302:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 24033 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv2i32, 24034 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24035 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24036 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24037 GIR_EraseFromParent, /*InsnID*/0, 24038 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24039 // GIR_Coverage, 1038, 24040 GIR_Done, 24041 // Label 1519: @58631 24042 GIM_Try, /*On fail goto*//*Label 1520*/ 58683, // Rule ID 1039 // 24043 GIM_CheckFeatures, GIFBS_HasNEON, 24044 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, 24045 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 24046 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 24047 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 24048 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24050 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24051 // (intrinsic_wo_chain:{ *:[v4i32] } 302:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 24052 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv4i32, 24053 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24056 GIR_EraseFromParent, /*InsnID*/0, 24057 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24058 // GIR_Coverage, 1039, 24059 GIR_Done, 24060 // Label 1520: @58683 24061 GIM_Try, /*On fail goto*//*Label 1521*/ 58735, // Rule ID 1040 // 24062 GIM_CheckFeatures, GIFBS_HasNEON, 24063 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, 24064 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 24065 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 24066 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 24067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24070 // (intrinsic_wo_chain:{ *:[v2i64] } 302:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) 24071 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv2i64, 24072 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24075 GIR_EraseFromParent, /*InsnID*/0, 24076 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24077 // GIR_Coverage, 1040, 24078 GIR_Done, 24079 // Label 1521: @58735 24080 GIM_Try, /*On fail goto*//*Label 1522*/ 58787, // Rule ID 1041 // 24081 GIM_CheckFeatures, GIFBS_HasNEON, 24082 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srhadd, 24083 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 24084 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 24085 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 24086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24089 // (intrinsic_wo_chain:{ *:[v8i8] } 305:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SRHADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 24090 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRHADDv8i8, 24091 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24094 GIR_EraseFromParent, /*InsnID*/0, 24095 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24096 // GIR_Coverage, 1041, 24097 GIR_Done, 24098 // Label 1522: @58787 24099 GIM_Try, /*On fail goto*//*Label 1523*/ 58839, // Rule ID 1042 // 24100 GIM_CheckFeatures, GIFBS_HasNEON, 24101 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srhadd, 24102 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 24103 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 24104 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 24105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24108 // (intrinsic_wo_chain:{ *:[v16i8] } 305:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SRHADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 24109 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRHADDv16i8, 24110 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24112 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24113 GIR_EraseFromParent, /*InsnID*/0, 24114 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24115 // GIR_Coverage, 1042, 24116 GIR_Done, 24117 // Label 1523: @58839 24118 GIM_Try, /*On fail goto*//*Label 1524*/ 58891, // Rule ID 1043 // 24119 GIM_CheckFeatures, GIFBS_HasNEON, 24120 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srhadd, 24121 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 24122 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 24123 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 24124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24127 // (intrinsic_wo_chain:{ *:[v4i16] } 305:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SRHADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 24128 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRHADDv4i16, 24129 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24130 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24131 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24132 GIR_EraseFromParent, /*InsnID*/0, 24133 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24134 // GIR_Coverage, 1043, 24135 GIR_Done, 24136 // Label 1524: @58891 24137 GIM_Try, /*On fail goto*//*Label 1525*/ 58943, // Rule ID 1044 // 24138 GIM_CheckFeatures, GIFBS_HasNEON, 24139 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srhadd, 24140 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 24141 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 24142 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 24143 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24146 // (intrinsic_wo_chain:{ *:[v8i16] } 305:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SRHADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 24147 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRHADDv8i16, 24148 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24149 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24150 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24151 GIR_EraseFromParent, /*InsnID*/0, 24152 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24153 // GIR_Coverage, 1044, 24154 GIR_Done, 24155 // Label 1525: @58943 24156 GIM_Try, /*On fail goto*//*Label 1526*/ 58995, // Rule ID 1045 // 24157 GIM_CheckFeatures, GIFBS_HasNEON, 24158 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srhadd, 24159 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 24160 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 24161 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 24162 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24163 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24164 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24165 // (intrinsic_wo_chain:{ *:[v2i32] } 305:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SRHADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 24166 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRHADDv2i32, 24167 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24168 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24169 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24170 GIR_EraseFromParent, /*InsnID*/0, 24171 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24172 // GIR_Coverage, 1045, 24173 GIR_Done, 24174 // Label 1526: @58995 24175 GIM_Try, /*On fail goto*//*Label 1527*/ 59047, // Rule ID 1046 // 24176 GIM_CheckFeatures, GIFBS_HasNEON, 24177 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srhadd, 24178 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 24179 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 24180 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 24181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24183 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24184 // (intrinsic_wo_chain:{ *:[v4i32] } 305:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SRHADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 24185 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRHADDv4i32, 24186 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24189 GIR_EraseFromParent, /*InsnID*/0, 24190 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24191 // GIR_Coverage, 1046, 24192 GIR_Done, 24193 // Label 1527: @59047 24194 GIM_Try, /*On fail goto*//*Label 1528*/ 59099, // Rule ID 1047 // 24195 GIM_CheckFeatures, GIFBS_HasNEON, 24196 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, 24197 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 24198 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 24199 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 24200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24202 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24203 // (intrinsic_wo_chain:{ *:[v8i8] } 306:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 24204 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv8i8, 24205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24206 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24207 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24208 GIR_EraseFromParent, /*InsnID*/0, 24209 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24210 // GIR_Coverage, 1047, 24211 GIR_Done, 24212 // Label 1528: @59099 24213 GIM_Try, /*On fail goto*//*Label 1529*/ 59151, // Rule ID 1048 // 24214 GIM_CheckFeatures, GIFBS_HasNEON, 24215 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, 24216 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 24217 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 24218 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 24219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24221 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24222 // (intrinsic_wo_chain:{ *:[v16i8] } 306:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 24223 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv16i8, 24224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24226 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24227 GIR_EraseFromParent, /*InsnID*/0, 24228 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24229 // GIR_Coverage, 1048, 24230 GIR_Done, 24231 // Label 1529: @59151 24232 GIM_Try, /*On fail goto*//*Label 1530*/ 59203, // Rule ID 1049 // 24233 GIM_CheckFeatures, GIFBS_HasNEON, 24234 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, 24235 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 24236 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 24237 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 24238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24241 // (intrinsic_wo_chain:{ *:[v4i16] } 306:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 24242 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv4i16, 24243 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24245 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24246 GIR_EraseFromParent, /*InsnID*/0, 24247 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24248 // GIR_Coverage, 1049, 24249 GIR_Done, 24250 // Label 1530: @59203 24251 GIM_Try, /*On fail goto*//*Label 1531*/ 59255, // Rule ID 1050 // 24252 GIM_CheckFeatures, GIFBS_HasNEON, 24253 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, 24254 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 24255 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 24256 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 24257 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24258 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24260 // (intrinsic_wo_chain:{ *:[v8i16] } 306:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 24261 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv8i16, 24262 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24263 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24264 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24265 GIR_EraseFromParent, /*InsnID*/0, 24266 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24267 // GIR_Coverage, 1050, 24268 GIR_Done, 24269 // Label 1531: @59255 24270 GIM_Try, /*On fail goto*//*Label 1532*/ 59307, // Rule ID 1051 // 24271 GIM_CheckFeatures, GIFBS_HasNEON, 24272 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, 24273 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 24274 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 24275 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 24276 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24279 // (intrinsic_wo_chain:{ *:[v2i32] } 306:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 24280 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv2i32, 24281 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24282 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24283 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24284 GIR_EraseFromParent, /*InsnID*/0, 24285 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24286 // GIR_Coverage, 1051, 24287 GIR_Done, 24288 // Label 1532: @59307 24289 GIM_Try, /*On fail goto*//*Label 1533*/ 59359, // Rule ID 1052 // 24290 GIM_CheckFeatures, GIFBS_HasNEON, 24291 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, 24292 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 24293 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 24294 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 24295 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24296 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24297 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24298 // (intrinsic_wo_chain:{ *:[v4i32] } 306:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 24299 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv4i32, 24300 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24301 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24302 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24303 GIR_EraseFromParent, /*InsnID*/0, 24304 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24305 // GIR_Coverage, 1052, 24306 GIR_Done, 24307 // Label 1533: @59359 24308 GIM_Try, /*On fail goto*//*Label 1534*/ 59411, // Rule ID 1053 // 24309 GIM_CheckFeatures, GIFBS_HasNEON, 24310 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, 24311 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 24312 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 24313 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 24314 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24315 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24317 // (intrinsic_wo_chain:{ *:[v2i64] } 306:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) 24318 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv2i64, 24319 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24322 GIR_EraseFromParent, /*InsnID*/0, 24323 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24324 // GIR_Coverage, 1053, 24325 GIR_Done, 24326 // Label 1534: @59411 24327 GIM_Try, /*On fail goto*//*Label 1535*/ 59463, // Rule ID 1054 // 24328 GIM_CheckFeatures, GIFBS_HasNEON, 24329 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, 24330 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 24331 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 24332 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 24333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24335 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24336 // (intrinsic_wo_chain:{ *:[v8i8] } 307:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 24337 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv8i8, 24338 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24339 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24340 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24341 GIR_EraseFromParent, /*InsnID*/0, 24342 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24343 // GIR_Coverage, 1054, 24344 GIR_Done, 24345 // Label 1535: @59463 24346 GIM_Try, /*On fail goto*//*Label 1536*/ 59515, // Rule ID 1055 // 24347 GIM_CheckFeatures, GIFBS_HasNEON, 24348 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, 24349 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 24350 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 24351 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 24352 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24353 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24355 // (intrinsic_wo_chain:{ *:[v16i8] } 307:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 24356 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv16i8, 24357 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24358 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24359 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24360 GIR_EraseFromParent, /*InsnID*/0, 24361 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24362 // GIR_Coverage, 1055, 24363 GIR_Done, 24364 // Label 1536: @59515 24365 GIM_Try, /*On fail goto*//*Label 1537*/ 59567, // Rule ID 1056 // 24366 GIM_CheckFeatures, GIFBS_HasNEON, 24367 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, 24368 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 24369 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 24370 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 24371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24372 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24374 // (intrinsic_wo_chain:{ *:[v4i16] } 307:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 24375 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv4i16, 24376 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24377 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24378 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24379 GIR_EraseFromParent, /*InsnID*/0, 24380 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24381 // GIR_Coverage, 1056, 24382 GIR_Done, 24383 // Label 1537: @59567 24384 GIM_Try, /*On fail goto*//*Label 1538*/ 59619, // Rule ID 1057 // 24385 GIM_CheckFeatures, GIFBS_HasNEON, 24386 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, 24387 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 24388 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 24389 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 24390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24391 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24392 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24393 // (intrinsic_wo_chain:{ *:[v8i16] } 307:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 24394 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv8i16, 24395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24396 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24397 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24398 GIR_EraseFromParent, /*InsnID*/0, 24399 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24400 // GIR_Coverage, 1057, 24401 GIR_Done, 24402 // Label 1538: @59619 24403 GIM_Try, /*On fail goto*//*Label 1539*/ 59671, // Rule ID 1058 // 24404 GIM_CheckFeatures, GIFBS_HasNEON, 24405 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, 24406 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 24407 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 24408 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 24409 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24410 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24412 // (intrinsic_wo_chain:{ *:[v2i32] } 307:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 24413 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv2i32, 24414 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24415 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24416 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24417 GIR_EraseFromParent, /*InsnID*/0, 24418 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24419 // GIR_Coverage, 1058, 24420 GIR_Done, 24421 // Label 1539: @59671 24422 GIM_Try, /*On fail goto*//*Label 1540*/ 59723, // Rule ID 1059 // 24423 GIM_CheckFeatures, GIFBS_HasNEON, 24424 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, 24425 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 24426 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 24427 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 24428 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24431 // (intrinsic_wo_chain:{ *:[v4i32] } 307:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 24432 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv4i32, 24433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24435 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24436 GIR_EraseFromParent, /*InsnID*/0, 24437 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24438 // GIR_Coverage, 1059, 24439 GIR_Done, 24440 // Label 1540: @59723 24441 GIM_Try, /*On fail goto*//*Label 1541*/ 59775, // Rule ID 1060 // 24442 GIM_CheckFeatures, GIFBS_HasNEON, 24443 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, 24444 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 24445 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 24446 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 24447 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24450 // (intrinsic_wo_chain:{ *:[v2i64] } 307:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) 24451 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv2i64, 24452 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24453 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24454 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24455 GIR_EraseFromParent, /*InsnID*/0, 24456 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24457 // GIR_Coverage, 1060, 24458 GIR_Done, 24459 // Label 1541: @59775 24460 GIM_Try, /*On fail goto*//*Label 1542*/ 59827, // Rule ID 1074 // 24461 GIM_CheckFeatures, GIFBS_HasNEON, 24462 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, 24463 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 24464 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 24465 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 24466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24469 // (intrinsic_wo_chain:{ *:[v8i8] } 328:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UABDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 24470 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv8i8, 24471 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24472 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24474 GIR_EraseFromParent, /*InsnID*/0, 24475 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24476 // GIR_Coverage, 1074, 24477 GIR_Done, 24478 // Label 1542: @59827 24479 GIM_Try, /*On fail goto*//*Label 1543*/ 59879, // Rule ID 1075 // 24480 GIM_CheckFeatures, GIFBS_HasNEON, 24481 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, 24482 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 24483 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 24484 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 24485 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24486 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24487 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24488 // (intrinsic_wo_chain:{ *:[v16i8] } 328:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UABDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 24489 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv16i8, 24490 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24491 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24492 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24493 GIR_EraseFromParent, /*InsnID*/0, 24494 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24495 // GIR_Coverage, 1075, 24496 GIR_Done, 24497 // Label 1543: @59879 24498 GIM_Try, /*On fail goto*//*Label 1544*/ 59931, // Rule ID 1076 // 24499 GIM_CheckFeatures, GIFBS_HasNEON, 24500 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, 24501 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 24502 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 24503 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 24504 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24505 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24506 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24507 // (intrinsic_wo_chain:{ *:[v4i16] } 328:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UABDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 24508 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv4i16, 24509 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24510 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24511 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24512 GIR_EraseFromParent, /*InsnID*/0, 24513 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24514 // GIR_Coverage, 1076, 24515 GIR_Done, 24516 // Label 1544: @59931 24517 GIM_Try, /*On fail goto*//*Label 1545*/ 59983, // Rule ID 1077 // 24518 GIM_CheckFeatures, GIFBS_HasNEON, 24519 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, 24520 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 24521 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 24522 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 24523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24526 // (intrinsic_wo_chain:{ *:[v8i16] } 328:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UABDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 24527 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv8i16, 24528 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24529 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24530 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24531 GIR_EraseFromParent, /*InsnID*/0, 24532 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24533 // GIR_Coverage, 1077, 24534 GIR_Done, 24535 // Label 1545: @59983 24536 GIM_Try, /*On fail goto*//*Label 1546*/ 60035, // Rule ID 1078 // 24537 GIM_CheckFeatures, GIFBS_HasNEON, 24538 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, 24539 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 24540 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 24541 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 24542 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24543 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24544 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24545 // (intrinsic_wo_chain:{ *:[v2i32] } 328:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UABDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 24546 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv2i32, 24547 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24548 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24549 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24550 GIR_EraseFromParent, /*InsnID*/0, 24551 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24552 // GIR_Coverage, 1078, 24553 GIR_Done, 24554 // Label 1546: @60035 24555 GIM_Try, /*On fail goto*//*Label 1547*/ 60087, // Rule ID 1079 // 24556 GIM_CheckFeatures, GIFBS_HasNEON, 24557 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, 24558 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 24559 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 24560 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 24561 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24562 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24564 // (intrinsic_wo_chain:{ *:[v4i32] } 328:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UABDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 24565 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv4i32, 24566 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24569 GIR_EraseFromParent, /*InsnID*/0, 24570 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24571 // GIR_Coverage, 1079, 24572 GIR_Done, 24573 // Label 1547: @60087 24574 GIM_Try, /*On fail goto*//*Label 1548*/ 60139, // Rule ID 1080 // 24575 GIM_CheckFeatures, GIFBS_HasNEON, 24576 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhadd, 24577 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 24578 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 24579 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 24580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24581 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24582 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24583 // (intrinsic_wo_chain:{ *:[v8i8] } 333:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UHADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 24584 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHADDv8i8, 24585 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24586 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24587 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24588 GIR_EraseFromParent, /*InsnID*/0, 24589 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24590 // GIR_Coverage, 1080, 24591 GIR_Done, 24592 // Label 1548: @60139 24593 GIM_Try, /*On fail goto*//*Label 1549*/ 60191, // Rule ID 1081 // 24594 GIM_CheckFeatures, GIFBS_HasNEON, 24595 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhadd, 24596 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 24597 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 24598 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 24599 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24600 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24602 // (intrinsic_wo_chain:{ *:[v16i8] } 333:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UHADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 24603 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHADDv16i8, 24604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24606 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24607 GIR_EraseFromParent, /*InsnID*/0, 24608 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24609 // GIR_Coverage, 1081, 24610 GIR_Done, 24611 // Label 1549: @60191 24612 GIM_Try, /*On fail goto*//*Label 1550*/ 60243, // Rule ID 1082 // 24613 GIM_CheckFeatures, GIFBS_HasNEON, 24614 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhadd, 24615 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 24616 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 24617 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 24618 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24621 // (intrinsic_wo_chain:{ *:[v4i16] } 333:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UHADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 24622 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHADDv4i16, 24623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24626 GIR_EraseFromParent, /*InsnID*/0, 24627 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24628 // GIR_Coverage, 1082, 24629 GIR_Done, 24630 // Label 1550: @60243 24631 GIM_Try, /*On fail goto*//*Label 1551*/ 60295, // Rule ID 1083 // 24632 GIM_CheckFeatures, GIFBS_HasNEON, 24633 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhadd, 24634 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 24635 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 24636 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 24637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24640 // (intrinsic_wo_chain:{ *:[v8i16] } 333:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UHADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 24641 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHADDv8i16, 24642 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24643 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24645 GIR_EraseFromParent, /*InsnID*/0, 24646 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24647 // GIR_Coverage, 1083, 24648 GIR_Done, 24649 // Label 1551: @60295 24650 GIM_Try, /*On fail goto*//*Label 1552*/ 60347, // Rule ID 1084 // 24651 GIM_CheckFeatures, GIFBS_HasNEON, 24652 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhadd, 24653 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 24654 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 24655 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 24656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24659 // (intrinsic_wo_chain:{ *:[v2i32] } 333:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UHADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 24660 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHADDv2i32, 24661 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24662 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24663 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24664 GIR_EraseFromParent, /*InsnID*/0, 24665 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24666 // GIR_Coverage, 1084, 24667 GIR_Done, 24668 // Label 1552: @60347 24669 GIM_Try, /*On fail goto*//*Label 1553*/ 60399, // Rule ID 1085 // 24670 GIM_CheckFeatures, GIFBS_HasNEON, 24671 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhadd, 24672 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 24673 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 24674 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 24675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24676 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24677 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24678 // (intrinsic_wo_chain:{ *:[v4i32] } 333:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UHADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 24679 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHADDv4i32, 24680 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24681 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24682 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24683 GIR_EraseFromParent, /*InsnID*/0, 24684 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24685 // GIR_Coverage, 1085, 24686 GIR_Done, 24687 // Label 1553: @60399 24688 GIM_Try, /*On fail goto*//*Label 1554*/ 60451, // Rule ID 1086 // 24689 GIM_CheckFeatures, GIFBS_HasNEON, 24690 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, 24691 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 24692 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 24693 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 24694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24697 // (intrinsic_wo_chain:{ *:[v8i8] } 334:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UHSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 24698 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv8i8, 24699 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24700 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24701 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24702 GIR_EraseFromParent, /*InsnID*/0, 24703 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24704 // GIR_Coverage, 1086, 24705 GIR_Done, 24706 // Label 1554: @60451 24707 GIM_Try, /*On fail goto*//*Label 1555*/ 60503, // Rule ID 1087 // 24708 GIM_CheckFeatures, GIFBS_HasNEON, 24709 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, 24710 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 24711 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 24712 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 24713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24716 // (intrinsic_wo_chain:{ *:[v16i8] } 334:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UHSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 24717 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv16i8, 24718 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24719 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24720 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24721 GIR_EraseFromParent, /*InsnID*/0, 24722 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24723 // GIR_Coverage, 1087, 24724 GIR_Done, 24725 // Label 1555: @60503 24726 GIM_Try, /*On fail goto*//*Label 1556*/ 60555, // Rule ID 1088 // 24727 GIM_CheckFeatures, GIFBS_HasNEON, 24728 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, 24729 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 24730 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 24731 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 24732 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24735 // (intrinsic_wo_chain:{ *:[v4i16] } 334:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UHSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 24736 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv4i16, 24737 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24738 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24739 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24740 GIR_EraseFromParent, /*InsnID*/0, 24741 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24742 // GIR_Coverage, 1088, 24743 GIR_Done, 24744 // Label 1556: @60555 24745 GIM_Try, /*On fail goto*//*Label 1557*/ 60607, // Rule ID 1089 // 24746 GIM_CheckFeatures, GIFBS_HasNEON, 24747 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, 24748 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 24749 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 24750 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 24751 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24754 // (intrinsic_wo_chain:{ *:[v8i16] } 334:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UHSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 24755 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv8i16, 24756 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24757 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24758 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24759 GIR_EraseFromParent, /*InsnID*/0, 24760 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24761 // GIR_Coverage, 1089, 24762 GIR_Done, 24763 // Label 1557: @60607 24764 GIM_Try, /*On fail goto*//*Label 1558*/ 60659, // Rule ID 1090 // 24765 GIM_CheckFeatures, GIFBS_HasNEON, 24766 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, 24767 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 24768 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 24769 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 24770 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24772 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24773 // (intrinsic_wo_chain:{ *:[v2i32] } 334:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UHSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 24774 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv2i32, 24775 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24776 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24778 GIR_EraseFromParent, /*InsnID*/0, 24779 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24780 // GIR_Coverage, 1090, 24781 GIR_Done, 24782 // Label 1558: @60659 24783 GIM_Try, /*On fail goto*//*Label 1559*/ 60711, // Rule ID 1091 // 24784 GIM_CheckFeatures, GIFBS_HasNEON, 24785 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, 24786 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 24787 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 24788 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 24789 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24790 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24791 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24792 // (intrinsic_wo_chain:{ *:[v4i32] } 334:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UHSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 24793 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv4i32, 24794 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24795 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24796 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24797 GIR_EraseFromParent, /*InsnID*/0, 24798 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24799 // GIR_Coverage, 1091, 24800 GIR_Done, 24801 // Label 1559: @60711 24802 GIM_Try, /*On fail goto*//*Label 1560*/ 60763, // Rule ID 1092 // 24803 GIM_CheckFeatures, GIFBS_HasNEON, 24804 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, 24805 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 24806 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 24807 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 24808 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24809 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24811 // (intrinsic_wo_chain:{ *:[v8i8] } 336:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMAXPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 24812 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv8i8, 24813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24814 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24815 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24816 GIR_EraseFromParent, /*InsnID*/0, 24817 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24818 // GIR_Coverage, 1092, 24819 GIR_Done, 24820 // Label 1560: @60763 24821 GIM_Try, /*On fail goto*//*Label 1561*/ 60815, // Rule ID 1093 // 24822 GIM_CheckFeatures, GIFBS_HasNEON, 24823 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, 24824 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 24825 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 24826 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 24827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24830 // (intrinsic_wo_chain:{ *:[v16i8] } 336:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMAXPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 24831 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv16i8, 24832 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24833 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24834 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24835 GIR_EraseFromParent, /*InsnID*/0, 24836 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24837 // GIR_Coverage, 1093, 24838 GIR_Done, 24839 // Label 1561: @60815 24840 GIM_Try, /*On fail goto*//*Label 1562*/ 60867, // Rule ID 1094 // 24841 GIM_CheckFeatures, GIFBS_HasNEON, 24842 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, 24843 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 24844 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 24845 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 24846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24849 // (intrinsic_wo_chain:{ *:[v4i16] } 336:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMAXPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 24850 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv4i16, 24851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24852 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24853 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24854 GIR_EraseFromParent, /*InsnID*/0, 24855 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24856 // GIR_Coverage, 1094, 24857 GIR_Done, 24858 // Label 1562: @60867 24859 GIM_Try, /*On fail goto*//*Label 1563*/ 60919, // Rule ID 1095 // 24860 GIM_CheckFeatures, GIFBS_HasNEON, 24861 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, 24862 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 24863 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 24864 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 24865 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24866 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24867 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24868 // (intrinsic_wo_chain:{ *:[v8i16] } 336:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UMAXPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 24869 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv8i16, 24870 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24871 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24872 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24873 GIR_EraseFromParent, /*InsnID*/0, 24874 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24875 // GIR_Coverage, 1095, 24876 GIR_Done, 24877 // Label 1563: @60919 24878 GIM_Try, /*On fail goto*//*Label 1564*/ 60971, // Rule ID 1096 // 24879 GIM_CheckFeatures, GIFBS_HasNEON, 24880 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, 24881 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 24882 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 24883 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 24884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24885 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24887 // (intrinsic_wo_chain:{ *:[v2i32] } 336:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMAXPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 24888 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv2i32, 24889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24891 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24892 GIR_EraseFromParent, /*InsnID*/0, 24893 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24894 // GIR_Coverage, 1096, 24895 GIR_Done, 24896 // Label 1564: @60971 24897 GIM_Try, /*On fail goto*//*Label 1565*/ 61023, // Rule ID 1097 // 24898 GIM_CheckFeatures, GIFBS_HasNEON, 24899 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, 24900 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 24901 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 24902 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 24903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24905 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24906 // (intrinsic_wo_chain:{ *:[v4i32] } 336:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UMAXPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 24907 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv4i32, 24908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24909 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24910 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24911 GIR_EraseFromParent, /*InsnID*/0, 24912 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24913 // GIR_Coverage, 1097, 24914 GIR_Done, 24915 // Label 1565: @61023 24916 GIM_Try, /*On fail goto*//*Label 1566*/ 61075, // Rule ID 1104 // 24917 GIM_CheckFeatures, GIFBS_HasNEON, 24918 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, 24919 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 24920 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 24921 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 24922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24925 // (intrinsic_wo_chain:{ *:[v8i8] } 339:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMINPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 24926 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv8i8, 24927 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24928 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24929 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24930 GIR_EraseFromParent, /*InsnID*/0, 24931 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24932 // GIR_Coverage, 1104, 24933 GIR_Done, 24934 // Label 1566: @61075 24935 GIM_Try, /*On fail goto*//*Label 1567*/ 61127, // Rule ID 1105 // 24936 GIM_CheckFeatures, GIFBS_HasNEON, 24937 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, 24938 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 24939 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 24940 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 24941 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24944 // (intrinsic_wo_chain:{ *:[v16i8] } 339:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMINPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 24945 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv16i8, 24946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24947 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24948 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24949 GIR_EraseFromParent, /*InsnID*/0, 24950 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24951 // GIR_Coverage, 1105, 24952 GIR_Done, 24953 // Label 1567: @61127 24954 GIM_Try, /*On fail goto*//*Label 1568*/ 61179, // Rule ID 1106 // 24955 GIM_CheckFeatures, GIFBS_HasNEON, 24956 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, 24957 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 24958 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 24959 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 24960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24961 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 24962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 24963 // (intrinsic_wo_chain:{ *:[v4i16] } 339:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMINPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 24964 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv4i16, 24965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24968 GIR_EraseFromParent, /*InsnID*/0, 24969 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24970 // GIR_Coverage, 1106, 24971 GIR_Done, 24972 // Label 1568: @61179 24973 GIM_Try, /*On fail goto*//*Label 1569*/ 61231, // Rule ID 1107 // 24974 GIM_CheckFeatures, GIFBS_HasNEON, 24975 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, 24976 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 24977 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 24978 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 24979 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 24980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 24981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 24982 // (intrinsic_wo_chain:{ *:[v8i16] } 339:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UMINPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 24983 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv8i16, 24984 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 24985 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 24986 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 24987 GIR_EraseFromParent, /*InsnID*/0, 24988 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24989 // GIR_Coverage, 1107, 24990 GIR_Done, 24991 // Label 1569: @61231 24992 GIM_Try, /*On fail goto*//*Label 1570*/ 61283, // Rule ID 1108 // 24993 GIM_CheckFeatures, GIFBS_HasNEON, 24994 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, 24995 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 24996 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 24997 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 24998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 24999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25001 // (intrinsic_wo_chain:{ *:[v2i32] } 339:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMINPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 25002 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv2i32, 25003 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25004 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25005 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25006 GIR_EraseFromParent, /*InsnID*/0, 25007 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25008 // GIR_Coverage, 1108, 25009 GIR_Done, 25010 // Label 1570: @61283 25011 GIM_Try, /*On fail goto*//*Label 1571*/ 61335, // Rule ID 1109 // 25012 GIM_CheckFeatures, GIFBS_HasNEON, 25013 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, 25014 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 25015 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 25016 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 25017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25018 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25020 // (intrinsic_wo_chain:{ *:[v4i32] } 339:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UMINPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 25021 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv4i32, 25022 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25025 GIR_EraseFromParent, /*InsnID*/0, 25026 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25027 // GIR_Coverage, 1109, 25028 GIR_Done, 25029 // Label 1571: @61335 25030 GIM_Try, /*On fail goto*//*Label 1572*/ 61387, // Rule ID 1116 // 25031 GIM_CheckFeatures, GIFBS_HasNEON, 25032 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, 25033 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 25034 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 25035 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 25036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25038 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25039 // (intrinsic_wo_chain:{ *:[v8i8] } 342:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 25040 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv8i8, 25041 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25042 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25044 GIR_EraseFromParent, /*InsnID*/0, 25045 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25046 // GIR_Coverage, 1116, 25047 GIR_Done, 25048 // Label 1572: @61387 25049 GIM_Try, /*On fail goto*//*Label 1573*/ 61439, // Rule ID 1117 // 25050 GIM_CheckFeatures, GIFBS_HasNEON, 25051 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, 25052 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 25053 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 25054 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 25055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25057 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25058 // (intrinsic_wo_chain:{ *:[v16i8] } 342:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 25059 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv16i8, 25060 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25061 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25062 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25063 GIR_EraseFromParent, /*InsnID*/0, 25064 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25065 // GIR_Coverage, 1117, 25066 GIR_Done, 25067 // Label 1573: @61439 25068 GIM_Try, /*On fail goto*//*Label 1574*/ 61491, // Rule ID 1118 // 25069 GIM_CheckFeatures, GIFBS_HasNEON, 25070 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, 25071 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 25072 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 25073 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 25074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25076 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25077 // (intrinsic_wo_chain:{ *:[v4i16] } 342:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 25078 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv4i16, 25079 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25080 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25081 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25082 GIR_EraseFromParent, /*InsnID*/0, 25083 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25084 // GIR_Coverage, 1118, 25085 GIR_Done, 25086 // Label 1574: @61491 25087 GIM_Try, /*On fail goto*//*Label 1575*/ 61543, // Rule ID 1119 // 25088 GIM_CheckFeatures, GIFBS_HasNEON, 25089 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, 25090 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 25091 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 25092 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 25093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25095 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25096 // (intrinsic_wo_chain:{ *:[v8i16] } 342:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 25097 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv8i16, 25098 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25099 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25101 GIR_EraseFromParent, /*InsnID*/0, 25102 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25103 // GIR_Coverage, 1119, 25104 GIR_Done, 25105 // Label 1575: @61543 25106 GIM_Try, /*On fail goto*//*Label 1576*/ 61595, // Rule ID 1120 // 25107 GIM_CheckFeatures, GIFBS_HasNEON, 25108 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, 25109 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 25110 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 25111 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 25112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25114 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25115 // (intrinsic_wo_chain:{ *:[v2i32] } 342:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 25116 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv2i32, 25117 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25118 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25119 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25120 GIR_EraseFromParent, /*InsnID*/0, 25121 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25122 // GIR_Coverage, 1120, 25123 GIR_Done, 25124 // Label 1576: @61595 25125 GIM_Try, /*On fail goto*//*Label 1577*/ 61647, // Rule ID 1121 // 25126 GIM_CheckFeatures, GIFBS_HasNEON, 25127 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, 25128 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 25129 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 25130 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 25131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25134 // (intrinsic_wo_chain:{ *:[v4i32] } 342:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 25135 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv4i32, 25136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25138 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25139 GIR_EraseFromParent, /*InsnID*/0, 25140 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25141 // GIR_Coverage, 1121, 25142 GIR_Done, 25143 // Label 1577: @61647 25144 GIM_Try, /*On fail goto*//*Label 1578*/ 61699, // Rule ID 1122 // 25145 GIM_CheckFeatures, GIFBS_HasNEON, 25146 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, 25147 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 25148 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 25149 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 25150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25151 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25152 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25153 // (intrinsic_wo_chain:{ *:[v2i64] } 342:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) 25154 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv2i64, 25155 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25156 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25157 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25158 GIR_EraseFromParent, /*InsnID*/0, 25159 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25160 // GIR_Coverage, 1122, 25161 GIR_Done, 25162 // Label 1578: @61699 25163 GIM_Try, /*On fail goto*//*Label 1579*/ 61751, // Rule ID 1123 // 25164 GIM_CheckFeatures, GIFBS_HasNEON, 25165 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, 25166 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 25167 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 25168 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 25169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25171 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25172 // (intrinsic_wo_chain:{ *:[v8i8] } 343:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 25173 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv8i8, 25174 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25175 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25176 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25177 GIR_EraseFromParent, /*InsnID*/0, 25178 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25179 // GIR_Coverage, 1123, 25180 GIR_Done, 25181 // Label 1579: @61751 25182 GIM_Try, /*On fail goto*//*Label 1580*/ 61803, // Rule ID 1124 // 25183 GIM_CheckFeatures, GIFBS_HasNEON, 25184 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, 25185 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 25186 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 25187 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 25188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25190 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25191 // (intrinsic_wo_chain:{ *:[v16i8] } 343:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 25192 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv16i8, 25193 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25194 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25195 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25196 GIR_EraseFromParent, /*InsnID*/0, 25197 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25198 // GIR_Coverage, 1124, 25199 GIR_Done, 25200 // Label 1580: @61803 25201 GIM_Try, /*On fail goto*//*Label 1581*/ 61855, // Rule ID 1125 // 25202 GIM_CheckFeatures, GIFBS_HasNEON, 25203 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, 25204 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 25205 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 25206 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 25207 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25209 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25210 // (intrinsic_wo_chain:{ *:[v4i16] } 343:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 25211 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv4i16, 25212 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25213 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25214 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25215 GIR_EraseFromParent, /*InsnID*/0, 25216 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25217 // GIR_Coverage, 1125, 25218 GIR_Done, 25219 // Label 1581: @61855 25220 GIM_Try, /*On fail goto*//*Label 1582*/ 61907, // Rule ID 1126 // 25221 GIM_CheckFeatures, GIFBS_HasNEON, 25222 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, 25223 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 25224 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 25225 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 25226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25227 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25228 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25229 // (intrinsic_wo_chain:{ *:[v8i16] } 343:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 25230 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv8i16, 25231 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25232 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25233 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25234 GIR_EraseFromParent, /*InsnID*/0, 25235 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25236 // GIR_Coverage, 1126, 25237 GIR_Done, 25238 // Label 1582: @61907 25239 GIM_Try, /*On fail goto*//*Label 1583*/ 61959, // Rule ID 1127 // 25240 GIM_CheckFeatures, GIFBS_HasNEON, 25241 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, 25242 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 25243 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 25244 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 25245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25247 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25248 // (intrinsic_wo_chain:{ *:[v2i32] } 343:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 25249 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv2i32, 25250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25251 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25252 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25253 GIR_EraseFromParent, /*InsnID*/0, 25254 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25255 // GIR_Coverage, 1127, 25256 GIR_Done, 25257 // Label 1583: @61959 25258 GIM_Try, /*On fail goto*//*Label 1584*/ 62011, // Rule ID 1128 // 25259 GIM_CheckFeatures, GIFBS_HasNEON, 25260 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, 25261 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 25262 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 25263 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 25264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25266 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25267 // (intrinsic_wo_chain:{ *:[v4i32] } 343:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 25268 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv4i32, 25269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25271 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25272 GIR_EraseFromParent, /*InsnID*/0, 25273 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25274 // GIR_Coverage, 1128, 25275 GIR_Done, 25276 // Label 1584: @62011 25277 GIM_Try, /*On fail goto*//*Label 1585*/ 62063, // Rule ID 1129 // 25278 GIM_CheckFeatures, GIFBS_HasNEON, 25279 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, 25280 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 25281 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 25282 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 25283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25286 // (intrinsic_wo_chain:{ *:[v2i64] } 343:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) 25287 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv2i64, 25288 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25289 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25290 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25291 GIR_EraseFromParent, /*InsnID*/0, 25292 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25293 // GIR_Coverage, 1129, 25294 GIR_Done, 25295 // Label 1585: @62063 25296 GIM_Try, /*On fail goto*//*Label 1586*/ 62115, // Rule ID 1130 // 25297 GIM_CheckFeatures, GIFBS_HasNEON, 25298 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, 25299 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 25300 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 25301 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 25302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25303 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25304 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25305 // (intrinsic_wo_chain:{ *:[v8i8] } 345:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 25306 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv8i8, 25307 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25308 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25309 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25310 GIR_EraseFromParent, /*InsnID*/0, 25311 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25312 // GIR_Coverage, 1130, 25313 GIR_Done, 25314 // Label 1586: @62115 25315 GIM_Try, /*On fail goto*//*Label 1587*/ 62167, // Rule ID 1131 // 25316 GIM_CheckFeatures, GIFBS_HasNEON, 25317 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, 25318 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 25319 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 25320 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 25321 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25322 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25324 // (intrinsic_wo_chain:{ *:[v16i8] } 345:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 25325 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv16i8, 25326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25327 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25328 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25329 GIR_EraseFromParent, /*InsnID*/0, 25330 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25331 // GIR_Coverage, 1131, 25332 GIR_Done, 25333 // Label 1587: @62167 25334 GIM_Try, /*On fail goto*//*Label 1588*/ 62219, // Rule ID 1132 // 25335 GIM_CheckFeatures, GIFBS_HasNEON, 25336 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, 25337 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 25338 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 25339 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 25340 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25343 // (intrinsic_wo_chain:{ *:[v4i16] } 345:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 25344 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv4i16, 25345 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25346 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25347 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25348 GIR_EraseFromParent, /*InsnID*/0, 25349 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25350 // GIR_Coverage, 1132, 25351 GIR_Done, 25352 // Label 1588: @62219 25353 GIM_Try, /*On fail goto*//*Label 1589*/ 62271, // Rule ID 1133 // 25354 GIM_CheckFeatures, GIFBS_HasNEON, 25355 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, 25356 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 25357 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 25358 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 25359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25361 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25362 // (intrinsic_wo_chain:{ *:[v8i16] } 345:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 25363 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv8i16, 25364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25367 GIR_EraseFromParent, /*InsnID*/0, 25368 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25369 // GIR_Coverage, 1133, 25370 GIR_Done, 25371 // Label 1589: @62271 25372 GIM_Try, /*On fail goto*//*Label 1590*/ 62323, // Rule ID 1134 // 25373 GIM_CheckFeatures, GIFBS_HasNEON, 25374 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, 25375 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 25376 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 25377 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 25378 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25379 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25381 // (intrinsic_wo_chain:{ *:[v2i32] } 345:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 25382 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv2i32, 25383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25386 GIR_EraseFromParent, /*InsnID*/0, 25387 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25388 // GIR_Coverage, 1134, 25389 GIR_Done, 25390 // Label 1590: @62323 25391 GIM_Try, /*On fail goto*//*Label 1591*/ 62375, // Rule ID 1135 // 25392 GIM_CheckFeatures, GIFBS_HasNEON, 25393 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, 25394 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 25395 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 25396 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 25397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25400 // (intrinsic_wo_chain:{ *:[v4i32] } 345:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 25401 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv4i32, 25402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25405 GIR_EraseFromParent, /*InsnID*/0, 25406 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25407 // GIR_Coverage, 1135, 25408 GIR_Done, 25409 // Label 1591: @62375 25410 GIM_Try, /*On fail goto*//*Label 1592*/ 62427, // Rule ID 1136 // 25411 GIM_CheckFeatures, GIFBS_HasNEON, 25412 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, 25413 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 25414 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 25415 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 25416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25419 // (intrinsic_wo_chain:{ *:[v2i64] } 345:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) 25420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv2i64, 25421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25422 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25423 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25424 GIR_EraseFromParent, /*InsnID*/0, 25425 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25426 // GIR_Coverage, 1136, 25427 GIR_Done, 25428 // Label 1592: @62427 25429 GIM_Try, /*On fail goto*//*Label 1593*/ 62479, // Rule ID 1137 // 25430 GIM_CheckFeatures, GIFBS_HasNEON, 25431 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, 25432 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 25433 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 25434 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 25435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25438 // (intrinsic_wo_chain:{ *:[v8i8] } 347:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 25439 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv8i8, 25440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25441 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25442 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25443 GIR_EraseFromParent, /*InsnID*/0, 25444 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25445 // GIR_Coverage, 1137, 25446 GIR_Done, 25447 // Label 1593: @62479 25448 GIM_Try, /*On fail goto*//*Label 1594*/ 62531, // Rule ID 1138 // 25449 GIM_CheckFeatures, GIFBS_HasNEON, 25450 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, 25451 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 25452 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 25453 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 25454 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25455 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25457 // (intrinsic_wo_chain:{ *:[v16i8] } 347:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 25458 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv16i8, 25459 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25460 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25461 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25462 GIR_EraseFromParent, /*InsnID*/0, 25463 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25464 // GIR_Coverage, 1138, 25465 GIR_Done, 25466 // Label 1594: @62531 25467 GIM_Try, /*On fail goto*//*Label 1595*/ 62583, // Rule ID 1139 // 25468 GIM_CheckFeatures, GIFBS_HasNEON, 25469 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, 25470 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 25471 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 25472 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 25473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25476 // (intrinsic_wo_chain:{ *:[v4i16] } 347:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 25477 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv4i16, 25478 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25479 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25480 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25481 GIR_EraseFromParent, /*InsnID*/0, 25482 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25483 // GIR_Coverage, 1139, 25484 GIR_Done, 25485 // Label 1595: @62583 25486 GIM_Try, /*On fail goto*//*Label 1596*/ 62635, // Rule ID 1140 // 25487 GIM_CheckFeatures, GIFBS_HasNEON, 25488 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, 25489 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 25490 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 25491 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 25492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25495 // (intrinsic_wo_chain:{ *:[v8i16] } 347:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 25496 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv8i16, 25497 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25498 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25500 GIR_EraseFromParent, /*InsnID*/0, 25501 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25502 // GIR_Coverage, 1140, 25503 GIR_Done, 25504 // Label 1596: @62635 25505 GIM_Try, /*On fail goto*//*Label 1597*/ 62687, // Rule ID 1141 // 25506 GIM_CheckFeatures, GIFBS_HasNEON, 25507 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, 25508 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 25509 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 25510 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 25511 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25512 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25513 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25514 // (intrinsic_wo_chain:{ *:[v2i32] } 347:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 25515 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv2i32, 25516 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25517 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25518 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25519 GIR_EraseFromParent, /*InsnID*/0, 25520 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25521 // GIR_Coverage, 1141, 25522 GIR_Done, 25523 // Label 1597: @62687 25524 GIM_Try, /*On fail goto*//*Label 1598*/ 62739, // Rule ID 1142 // 25525 GIM_CheckFeatures, GIFBS_HasNEON, 25526 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, 25527 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 25528 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 25529 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 25530 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25531 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25532 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25533 // (intrinsic_wo_chain:{ *:[v4i32] } 347:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 25534 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv4i32, 25535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25536 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25537 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25538 GIR_EraseFromParent, /*InsnID*/0, 25539 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25540 // GIR_Coverage, 1142, 25541 GIR_Done, 25542 // Label 1598: @62739 25543 GIM_Try, /*On fail goto*//*Label 1599*/ 62791, // Rule ID 1143 // 25544 GIM_CheckFeatures, GIFBS_HasNEON, 25545 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, 25546 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 25547 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 25548 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 25549 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25550 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25551 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25552 // (intrinsic_wo_chain:{ *:[v2i64] } 347:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) 25553 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv2i64, 25554 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25555 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25556 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25557 GIR_EraseFromParent, /*InsnID*/0, 25558 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25559 // GIR_Coverage, 1143, 25560 GIR_Done, 25561 // Label 1599: @62791 25562 GIM_Try, /*On fail goto*//*Label 1600*/ 62843, // Rule ID 1144 // 25563 GIM_CheckFeatures, GIFBS_HasNEON, 25564 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urhadd, 25565 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 25566 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 25567 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 25568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25569 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25570 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25571 // (intrinsic_wo_chain:{ *:[v8i8] } 350:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (URHADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 25572 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URHADDv8i8, 25573 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25574 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25575 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25576 GIR_EraseFromParent, /*InsnID*/0, 25577 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25578 // GIR_Coverage, 1144, 25579 GIR_Done, 25580 // Label 1600: @62843 25581 GIM_Try, /*On fail goto*//*Label 1601*/ 62895, // Rule ID 1145 // 25582 GIM_CheckFeatures, GIFBS_HasNEON, 25583 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urhadd, 25584 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 25585 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 25586 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 25587 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25588 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25589 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25590 // (intrinsic_wo_chain:{ *:[v16i8] } 350:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (URHADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 25591 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URHADDv16i8, 25592 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25593 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25594 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25595 GIR_EraseFromParent, /*InsnID*/0, 25596 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25597 // GIR_Coverage, 1145, 25598 GIR_Done, 25599 // Label 1601: @62895 25600 GIM_Try, /*On fail goto*//*Label 1602*/ 62947, // Rule ID 1146 // 25601 GIM_CheckFeatures, GIFBS_HasNEON, 25602 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urhadd, 25603 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 25604 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 25605 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 25606 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25607 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25609 // (intrinsic_wo_chain:{ *:[v4i16] } 350:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (URHADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 25610 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URHADDv4i16, 25611 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25612 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25613 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25614 GIR_EraseFromParent, /*InsnID*/0, 25615 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25616 // GIR_Coverage, 1146, 25617 GIR_Done, 25618 // Label 1602: @62947 25619 GIM_Try, /*On fail goto*//*Label 1603*/ 62999, // Rule ID 1147 // 25620 GIM_CheckFeatures, GIFBS_HasNEON, 25621 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urhadd, 25622 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 25623 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 25624 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 25625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25628 // (intrinsic_wo_chain:{ *:[v8i16] } 350:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (URHADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 25629 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URHADDv8i16, 25630 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25631 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25632 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25633 GIR_EraseFromParent, /*InsnID*/0, 25634 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25635 // GIR_Coverage, 1147, 25636 GIR_Done, 25637 // Label 1603: @62999 25638 GIM_Try, /*On fail goto*//*Label 1604*/ 63051, // Rule ID 1148 // 25639 GIM_CheckFeatures, GIFBS_HasNEON, 25640 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urhadd, 25641 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 25642 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 25643 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 25644 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25645 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25646 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25647 // (intrinsic_wo_chain:{ *:[v2i32] } 350:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (URHADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 25648 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URHADDv2i32, 25649 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25650 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25651 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25652 GIR_EraseFromParent, /*InsnID*/0, 25653 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25654 // GIR_Coverage, 1148, 25655 GIR_Done, 25656 // Label 1604: @63051 25657 GIM_Try, /*On fail goto*//*Label 1605*/ 63103, // Rule ID 1149 // 25658 GIM_CheckFeatures, GIFBS_HasNEON, 25659 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urhadd, 25660 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 25661 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 25662 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 25663 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25664 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25665 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25666 // (intrinsic_wo_chain:{ *:[v4i32] } 350:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (URHADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 25667 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URHADDv4i32, 25668 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25669 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25670 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25671 GIR_EraseFromParent, /*InsnID*/0, 25672 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25673 // GIR_Coverage, 1149, 25674 GIR_Done, 25675 // Label 1605: @63103 25676 GIM_Try, /*On fail goto*//*Label 1606*/ 63155, // Rule ID 1150 // 25677 GIM_CheckFeatures, GIFBS_HasNEON, 25678 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, 25679 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 25680 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 25681 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 25682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25684 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25685 // (intrinsic_wo_chain:{ *:[v8i8] } 351:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (URSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 25686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv8i8, 25687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25690 GIR_EraseFromParent, /*InsnID*/0, 25691 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25692 // GIR_Coverage, 1150, 25693 GIR_Done, 25694 // Label 1606: @63155 25695 GIM_Try, /*On fail goto*//*Label 1607*/ 63207, // Rule ID 1151 // 25696 GIM_CheckFeatures, GIFBS_HasNEON, 25697 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, 25698 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 25699 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 25700 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 25701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25703 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25704 // (intrinsic_wo_chain:{ *:[v16i8] } 351:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (URSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 25705 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv16i8, 25706 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25707 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25708 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25709 GIR_EraseFromParent, /*InsnID*/0, 25710 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25711 // GIR_Coverage, 1151, 25712 GIR_Done, 25713 // Label 1607: @63207 25714 GIM_Try, /*On fail goto*//*Label 1608*/ 63259, // Rule ID 1152 // 25715 GIM_CheckFeatures, GIFBS_HasNEON, 25716 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, 25717 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 25718 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 25719 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 25720 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25722 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25723 // (intrinsic_wo_chain:{ *:[v4i16] } 351:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (URSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 25724 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv4i16, 25725 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25726 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25728 GIR_EraseFromParent, /*InsnID*/0, 25729 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25730 // GIR_Coverage, 1152, 25731 GIR_Done, 25732 // Label 1608: @63259 25733 GIM_Try, /*On fail goto*//*Label 1609*/ 63311, // Rule ID 1153 // 25734 GIM_CheckFeatures, GIFBS_HasNEON, 25735 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, 25736 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 25737 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 25738 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 25739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25740 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25742 // (intrinsic_wo_chain:{ *:[v8i16] } 351:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (URSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 25743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv8i16, 25744 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25745 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25747 GIR_EraseFromParent, /*InsnID*/0, 25748 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25749 // GIR_Coverage, 1153, 25750 GIR_Done, 25751 // Label 1609: @63311 25752 GIM_Try, /*On fail goto*//*Label 1610*/ 63363, // Rule ID 1154 // 25753 GIM_CheckFeatures, GIFBS_HasNEON, 25754 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, 25755 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 25756 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 25757 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 25758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25759 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25761 // (intrinsic_wo_chain:{ *:[v2i32] } 351:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (URSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 25762 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv2i32, 25763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25766 GIR_EraseFromParent, /*InsnID*/0, 25767 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25768 // GIR_Coverage, 1154, 25769 GIR_Done, 25770 // Label 1610: @63363 25771 GIM_Try, /*On fail goto*//*Label 1611*/ 63415, // Rule ID 1155 // 25772 GIM_CheckFeatures, GIFBS_HasNEON, 25773 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, 25774 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 25775 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 25776 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 25777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25780 // (intrinsic_wo_chain:{ *:[v4i32] } 351:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (URSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 25781 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv4i32, 25782 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25783 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25785 GIR_EraseFromParent, /*InsnID*/0, 25786 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25787 // GIR_Coverage, 1155, 25788 GIR_Done, 25789 // Label 1611: @63415 25790 GIM_Try, /*On fail goto*//*Label 1612*/ 63467, // Rule ID 1156 // 25791 GIM_CheckFeatures, GIFBS_HasNEON, 25792 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, 25793 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 25794 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 25795 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 25796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25799 // (intrinsic_wo_chain:{ *:[v2i64] } 351:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (URSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) 25800 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv2i64, 25801 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25802 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25803 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25804 GIR_EraseFromParent, /*InsnID*/0, 25805 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25806 // GIR_Coverage, 1156, 25807 GIR_Done, 25808 // Label 1612: @63467 25809 GIM_Try, /*On fail goto*//*Label 1613*/ 63519, // Rule ID 1157 // 25810 GIM_CheckFeatures, GIFBS_HasNEON, 25811 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, 25812 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 25813 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 25814 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 25815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25818 // (intrinsic_wo_chain:{ *:[v8i8] } 353:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (USHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 25819 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv8i8, 25820 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25821 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25822 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25823 GIR_EraseFromParent, /*InsnID*/0, 25824 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25825 // GIR_Coverage, 1157, 25826 GIR_Done, 25827 // Label 1613: @63519 25828 GIM_Try, /*On fail goto*//*Label 1614*/ 63571, // Rule ID 1158 // 25829 GIM_CheckFeatures, GIFBS_HasNEON, 25830 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, 25831 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 25832 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 25833 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 25834 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25835 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25836 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25837 // (intrinsic_wo_chain:{ *:[v16i8] } 353:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (USHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 25838 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv16i8, 25839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25840 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25841 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25842 GIR_EraseFromParent, /*InsnID*/0, 25843 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25844 // GIR_Coverage, 1158, 25845 GIR_Done, 25846 // Label 1614: @63571 25847 GIM_Try, /*On fail goto*//*Label 1615*/ 63623, // Rule ID 1159 // 25848 GIM_CheckFeatures, GIFBS_HasNEON, 25849 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, 25850 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 25851 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 25852 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 25853 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25854 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25855 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25856 // (intrinsic_wo_chain:{ *:[v4i16] } 353:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (USHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 25857 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv4i16, 25858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25861 GIR_EraseFromParent, /*InsnID*/0, 25862 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25863 // GIR_Coverage, 1159, 25864 GIR_Done, 25865 // Label 1615: @63623 25866 GIM_Try, /*On fail goto*//*Label 1616*/ 63675, // Rule ID 1160 // 25867 GIM_CheckFeatures, GIFBS_HasNEON, 25868 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, 25869 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 25870 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 25871 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 25872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25875 // (intrinsic_wo_chain:{ *:[v8i16] } 353:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (USHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 25876 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv8i16, 25877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25880 GIR_EraseFromParent, /*InsnID*/0, 25881 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25882 // GIR_Coverage, 1160, 25883 GIR_Done, 25884 // Label 1616: @63675 25885 GIM_Try, /*On fail goto*//*Label 1617*/ 63727, // Rule ID 1161 // 25886 GIM_CheckFeatures, GIFBS_HasNEON, 25887 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, 25888 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 25889 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 25890 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 25891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25894 // (intrinsic_wo_chain:{ *:[v2i32] } 353:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (USHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 25895 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv2i32, 25896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25898 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25899 GIR_EraseFromParent, /*InsnID*/0, 25900 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25901 // GIR_Coverage, 1161, 25902 GIR_Done, 25903 // Label 1617: @63727 25904 GIM_Try, /*On fail goto*//*Label 1618*/ 63779, // Rule ID 1162 // 25905 GIM_CheckFeatures, GIFBS_HasNEON, 25906 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, 25907 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 25908 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 25909 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 25910 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25913 // (intrinsic_wo_chain:{ *:[v4i32] } 353:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (USHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 25914 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv4i32, 25915 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25916 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25917 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25918 GIR_EraseFromParent, /*InsnID*/0, 25919 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25920 // GIR_Coverage, 1162, 25921 GIR_Done, 25922 // Label 1618: @63779 25923 GIM_Try, /*On fail goto*//*Label 1619*/ 63831, // Rule ID 1163 // 25924 GIM_CheckFeatures, GIFBS_HasNEON, 25925 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, 25926 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 25927 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 25928 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 25929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 25930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 25931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 25932 // (intrinsic_wo_chain:{ *:[v2i64] } 353:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (USHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) 25933 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv2i64, 25934 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25935 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25937 GIR_EraseFromParent, /*InsnID*/0, 25938 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25939 // GIR_Coverage, 1163, 25940 GIR_Done, 25941 // Label 1619: @63831 25942 GIM_Try, /*On fail goto*//*Label 1620*/ 63883, // Rule ID 1193 // 25943 GIM_CheckFeatures, GIFBS_HasNEON, 25944 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fabd, 25945 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 25946 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 25947 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 25948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 25949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 25950 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 25951 // (intrinsic_wo_chain:{ *:[f64] } 366:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FABD64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) 25952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD64, 25953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25954 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25956 GIR_EraseFromParent, /*InsnID*/0, 25957 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25958 // GIR_Coverage, 1193, 25959 GIR_Done, 25960 // Label 1620: @63883 25961 GIM_Try, /*On fail goto*//*Label 1621*/ 63935, // Rule ID 1194 // 25962 GIM_CheckFeatures, GIFBS_HasNEON, 25963 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fabd, 25964 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 25965 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 25966 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 25967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 25968 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 25969 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 25970 // (intrinsic_wo_chain:{ *:[f32] } 366:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FABD32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) 25971 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD32, 25972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25973 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25975 GIR_EraseFromParent, /*InsnID*/0, 25976 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25977 // GIR_Coverage, 1194, 25978 GIR_Done, 25979 // Label 1621: @63935 25980 GIM_Try, /*On fail goto*//*Label 1622*/ 63987, // Rule ID 1195 // 25981 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 25982 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fabd, 25983 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 25984 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 25985 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, 25986 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 25987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 25988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, 25989 // (intrinsic_wo_chain:{ *:[f16] } 366:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FABD16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) 25990 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD16, 25991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 25992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 25993 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 25994 GIR_EraseFromParent, /*InsnID*/0, 25995 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25996 // GIR_Coverage, 1195, 25997 GIR_Done, 25998 // Label 1622: @63987 25999 GIM_Try, /*On fail goto*//*Label 1623*/ 64039, // Rule ID 1196 // 26000 GIM_CheckFeatures, GIFBS_HasNEON, 26001 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, 26002 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26003 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26004 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 26005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26006 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26008 // (intrinsic_wo_chain:{ *:[i64] } 218:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FACGE64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) 26009 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGE64, 26010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26011 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26012 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26013 GIR_EraseFromParent, /*InsnID*/0, 26014 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26015 // GIR_Coverage, 1196, 26016 GIR_Done, 26017 // Label 1623: @64039 26018 GIM_Try, /*On fail goto*//*Label 1624*/ 64091, // Rule ID 1197 // 26019 GIM_CheckFeatures, GIFBS_HasNEON, 26020 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, 26021 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 26022 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 26023 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 26024 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 26025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 26026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 26027 // (intrinsic_wo_chain:{ *:[i32] } 218:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FACGE32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) 26028 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGE32, 26029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26032 GIR_EraseFromParent, /*InsnID*/0, 26033 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26034 // GIR_Coverage, 1197, 26035 GIR_Done, 26036 // Label 1624: @64091 26037 GIM_Try, /*On fail goto*//*Label 1625*/ 64143, // Rule ID 1198 // 26038 GIM_CheckFeatures, GIFBS_HasNEON, 26039 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, 26040 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26041 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26042 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 26043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26046 // (intrinsic_wo_chain:{ *:[i64] } 219:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FACGT64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) 26047 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGT64, 26048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26051 GIR_EraseFromParent, /*InsnID*/0, 26052 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26053 // GIR_Coverage, 1198, 26054 GIR_Done, 26055 // Label 1625: @64143 26056 GIM_Try, /*On fail goto*//*Label 1626*/ 64195, // Rule ID 1199 // 26057 GIM_CheckFeatures, GIFBS_HasNEON, 26058 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, 26059 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 26060 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 26061 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 26062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 26063 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 26064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 26065 // (intrinsic_wo_chain:{ *:[i32] } 219:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FACGT32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) 26066 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGT32, 26067 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26070 GIR_EraseFromParent, /*InsnID*/0, 26071 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26072 // GIR_Coverage, 1199, 26073 GIR_Done, 26074 // Label 1626: @64195 26075 GIM_Try, /*On fail goto*//*Label 1627*/ 64247, // Rule ID 1206 // 26076 GIM_CheckFeatures, GIFBS_HasNEON, 26077 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, 26078 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26079 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26080 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 26081 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26082 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26084 // (intrinsic_wo_chain:{ *:[f64] } 244:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMULX64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) 26085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX64, 26086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26087 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26088 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26089 GIR_EraseFromParent, /*InsnID*/0, 26090 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26091 // GIR_Coverage, 1206, 26092 GIR_Done, 26093 // Label 1627: @64247 26094 GIM_Try, /*On fail goto*//*Label 1628*/ 64299, // Rule ID 1207 // 26095 GIM_CheckFeatures, GIFBS_HasNEON, 26096 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, 26097 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 26098 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 26099 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 26100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 26101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 26102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 26103 // (intrinsic_wo_chain:{ *:[f32] } 244:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMULX32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) 26104 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX32, 26105 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26106 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26107 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26108 GIR_EraseFromParent, /*InsnID*/0, 26109 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26110 // GIR_Coverage, 1207, 26111 GIR_Done, 26112 // Label 1628: @64299 26113 GIM_Try, /*On fail goto*//*Label 1629*/ 64351, // Rule ID 1208 // 26114 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 26115 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, 26116 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 26117 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 26118 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, 26119 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 26120 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 26121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, 26122 // (intrinsic_wo_chain:{ *:[f16] } 244:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMULX16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) 26123 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX16, 26124 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26126 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26127 GIR_EraseFromParent, /*InsnID*/0, 26128 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26129 // GIR_Coverage, 1208, 26130 GIR_Done, 26131 // Label 1629: @64351 26132 GIM_Try, /*On fail goto*//*Label 1630*/ 64403, // Rule ID 1209 // 26133 GIM_CheckFeatures, GIFBS_HasNEON, 26134 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, 26135 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26136 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26137 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 26138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26141 // (intrinsic_wo_chain:{ *:[f64] } 246:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FRECPS64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) 26142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS64, 26143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26144 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26145 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26146 GIR_EraseFromParent, /*InsnID*/0, 26147 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26148 // GIR_Coverage, 1209, 26149 GIR_Done, 26150 // Label 1630: @64403 26151 GIM_Try, /*On fail goto*//*Label 1631*/ 64455, // Rule ID 1210 // 26152 GIM_CheckFeatures, GIFBS_HasNEON, 26153 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, 26154 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 26155 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 26156 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 26157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 26158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 26159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 26160 // (intrinsic_wo_chain:{ *:[f32] } 246:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FRECPS32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) 26161 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS32, 26162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26165 GIR_EraseFromParent, /*InsnID*/0, 26166 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26167 // GIR_Coverage, 1210, 26168 GIR_Done, 26169 // Label 1631: @64455 26170 GIM_Try, /*On fail goto*//*Label 1632*/ 64507, // Rule ID 1211 // 26171 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 26172 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, 26173 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 26174 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 26175 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, 26176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 26177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 26178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, 26179 // (intrinsic_wo_chain:{ *:[f16] } 246:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FRECPS16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) 26180 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS16, 26181 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26182 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26183 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26184 GIR_EraseFromParent, /*InsnID*/0, 26185 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26186 // GIR_Coverage, 1211, 26187 GIR_Done, 26188 // Label 1632: @64507 26189 GIM_Try, /*On fail goto*//*Label 1633*/ 64559, // Rule ID 1212 // 26190 GIM_CheckFeatures, GIFBS_HasNEON, 26191 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, 26192 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26193 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26194 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 26195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26198 // (intrinsic_wo_chain:{ *:[f64] } 250:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FRSQRTS64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) 26199 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS64, 26200 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26201 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26202 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26203 GIR_EraseFromParent, /*InsnID*/0, 26204 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26205 // GIR_Coverage, 1212, 26206 GIR_Done, 26207 // Label 1633: @64559 26208 GIM_Try, /*On fail goto*//*Label 1634*/ 64611, // Rule ID 1213 // 26209 GIM_CheckFeatures, GIFBS_HasNEON, 26210 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, 26211 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 26212 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 26213 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 26214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 26215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 26216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 26217 // (intrinsic_wo_chain:{ *:[f32] } 250:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FRSQRTS32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) 26218 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS32, 26219 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26220 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26221 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26222 GIR_EraseFromParent, /*InsnID*/0, 26223 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26224 // GIR_Coverage, 1213, 26225 GIR_Done, 26226 // Label 1634: @64611 26227 GIM_Try, /*On fail goto*//*Label 1635*/ 64663, // Rule ID 1214 // 26228 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 26229 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, 26230 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 26231 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 26232 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, 26233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 26234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 26235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, 26236 // (intrinsic_wo_chain:{ *:[f16] } 250:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FRSQRTS16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) 26237 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS16, 26238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26239 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26240 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26241 GIR_EraseFromParent, /*InsnID*/0, 26242 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26243 // GIR_Coverage, 1214, 26244 GIR_Done, 26245 // Label 1635: @64663 26246 GIM_Try, /*On fail goto*//*Label 1636*/ 64715, // Rule ID 1215 // 26247 GIM_CheckFeatures, GIFBS_HasNEON, 26248 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, 26249 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26250 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26251 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 26252 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26255 // (intrinsic_wo_chain:{ *:[v1i64] } 289:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) 26256 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv1i64, 26257 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26258 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26259 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26260 GIR_EraseFromParent, /*InsnID*/0, 26261 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26262 // GIR_Coverage, 1215, 26263 GIR_Done, 26264 // Label 1636: @64715 26265 GIM_Try, /*On fail goto*//*Label 1637*/ 64767, // Rule ID 1216 // 26266 GIM_CheckFeatures, GIFBS_HasNEON, 26267 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, 26268 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 26269 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 26270 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 26271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 26272 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 26273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 26274 // (intrinsic_wo_chain:{ *:[i32] } 290:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQDMULHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) 26275 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv1i32, 26276 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26278 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26279 GIR_EraseFromParent, /*InsnID*/0, 26280 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26281 // GIR_Coverage, 1216, 26282 GIR_Done, 26283 // Label 1637: @64767 26284 GIM_Try, /*On fail goto*//*Label 1638*/ 64819, // Rule ID 1217 // 26285 GIM_CheckFeatures, GIFBS_HasNEON, 26286 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, 26287 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 26288 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 26289 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 26290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 26291 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 26292 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 26293 // (intrinsic_wo_chain:{ *:[i32] } 294:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQRDMULHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) 26294 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv1i32, 26295 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26296 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26297 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26298 GIR_EraseFromParent, /*InsnID*/0, 26299 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26300 // GIR_Coverage, 1217, 26301 GIR_Done, 26302 // Label 1638: @64819 26303 GIM_Try, /*On fail goto*//*Label 1639*/ 64871, // Rule ID 1218 // 26304 GIM_CheckFeatures, GIFBS_HasNEON, 26305 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, 26306 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26307 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26308 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 26309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26311 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26312 // (intrinsic_wo_chain:{ *:[v1i64] } 295:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) 26313 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv1i64, 26314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26315 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26316 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26317 GIR_EraseFromParent, /*InsnID*/0, 26318 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26319 // GIR_Coverage, 1218, 26320 GIR_Done, 26321 // Label 1639: @64871 26322 GIM_Try, /*On fail goto*//*Label 1640*/ 64923, // Rule ID 1219 // 26323 GIM_CheckFeatures, GIFBS_HasNEON, 26324 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, 26325 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26326 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26327 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 26328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26331 // (intrinsic_wo_chain:{ *:[v1i64] } 298:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) 26332 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv1i64, 26333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26334 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26335 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26336 GIR_EraseFromParent, /*InsnID*/0, 26337 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26338 // GIR_Coverage, 1219, 26339 GIR_Done, 26340 // Label 1640: @64923 26341 GIM_Try, /*On fail goto*//*Label 1641*/ 64975, // Rule ID 1220 // 26342 GIM_CheckFeatures, GIFBS_HasNEON, 26343 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, 26344 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26345 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26346 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 26347 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26350 // (intrinsic_wo_chain:{ *:[v1i64] } 302:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQSUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) 26351 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv1i64, 26352 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26355 GIR_EraseFromParent, /*InsnID*/0, 26356 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26357 // GIR_Coverage, 1220, 26358 GIR_Done, 26359 // Label 1641: @64975 26360 GIM_Try, /*On fail goto*//*Label 1642*/ 65027, // Rule ID 1221 // 26361 GIM_CheckFeatures, GIFBS_HasNEON, 26362 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, 26363 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26364 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26365 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 26366 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26369 // (intrinsic_wo_chain:{ *:[v1i64] } 306:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) 26370 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv1i64, 26371 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26372 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26373 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26374 GIR_EraseFromParent, /*InsnID*/0, 26375 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26376 // GIR_Coverage, 1221, 26377 GIR_Done, 26378 // Label 1642: @65027 26379 GIM_Try, /*On fail goto*//*Label 1643*/ 65079, // Rule ID 1222 // 26380 GIM_CheckFeatures, GIFBS_HasNEON, 26381 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, 26382 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26383 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26384 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 26385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26386 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26387 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26388 // (intrinsic_wo_chain:{ *:[v1i64] } 307:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) 26389 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv1i64, 26390 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26391 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26392 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26393 GIR_EraseFromParent, /*InsnID*/0, 26394 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26395 // GIR_Coverage, 1222, 26396 GIR_Done, 26397 // Label 1643: @65079 26398 GIM_Try, /*On fail goto*//*Label 1644*/ 65131, // Rule ID 1224 // 26399 GIM_CheckFeatures, GIFBS_HasNEON, 26400 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, 26401 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26402 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26403 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 26404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26407 // (intrinsic_wo_chain:{ *:[v1i64] } 342:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) 26408 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv1i64, 26409 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26410 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26411 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26412 GIR_EraseFromParent, /*InsnID*/0, 26413 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26414 // GIR_Coverage, 1224, 26415 GIR_Done, 26416 // Label 1644: @65131 26417 GIM_Try, /*On fail goto*//*Label 1645*/ 65183, // Rule ID 1225 // 26418 GIM_CheckFeatures, GIFBS_HasNEON, 26419 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, 26420 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26421 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26422 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 26423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26426 // (intrinsic_wo_chain:{ *:[v1i64] } 343:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) 26427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv1i64, 26428 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26429 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26430 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26431 GIR_EraseFromParent, /*InsnID*/0, 26432 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26433 // GIR_Coverage, 1225, 26434 GIR_Done, 26435 // Label 1645: @65183 26436 GIM_Try, /*On fail goto*//*Label 1646*/ 65235, // Rule ID 1226 // 26437 GIM_CheckFeatures, GIFBS_HasNEON, 26438 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, 26439 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26440 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26441 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 26442 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26443 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26444 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26445 // (intrinsic_wo_chain:{ *:[v1i64] } 345:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) 26446 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv1i64, 26447 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26448 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26449 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26450 GIR_EraseFromParent, /*InsnID*/0, 26451 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26452 // GIR_Coverage, 1226, 26453 GIR_Done, 26454 // Label 1646: @65235 26455 GIM_Try, /*On fail goto*//*Label 1647*/ 65287, // Rule ID 1227 // 26456 GIM_CheckFeatures, GIFBS_HasNEON, 26457 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, 26458 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26459 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26460 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 26461 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26462 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26463 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26464 // (intrinsic_wo_chain:{ *:[v1i64] } 347:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQSUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) 26465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv1i64, 26466 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26467 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26468 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26469 GIR_EraseFromParent, /*InsnID*/0, 26470 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26471 // GIR_Coverage, 1227, 26472 GIR_Done, 26473 // Label 1647: @65287 26474 GIM_Try, /*On fail goto*//*Label 1648*/ 65339, // Rule ID 1228 // 26475 GIM_CheckFeatures, GIFBS_HasNEON, 26476 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, 26477 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26478 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26479 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 26480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26481 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26482 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26483 // (intrinsic_wo_chain:{ *:[v1i64] } 351:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (URSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) 26484 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv1i64, 26485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26486 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26487 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26488 GIR_EraseFromParent, /*InsnID*/0, 26489 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26490 // GIR_Coverage, 1228, 26491 GIR_Done, 26492 // Label 1648: @65339 26493 GIM_Try, /*On fail goto*//*Label 1649*/ 65391, // Rule ID 1229 // 26494 GIM_CheckFeatures, GIFBS_HasNEON, 26495 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, 26496 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26497 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26498 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 26499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26501 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26502 // (intrinsic_wo_chain:{ *:[v1i64] } 353:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (USHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) 26503 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv1i64, 26504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26507 GIR_EraseFromParent, /*InsnID*/0, 26508 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26509 // GIR_Coverage, 1229, 26510 GIR_Done, 26511 // Label 1649: @65391 26512 GIM_Try, /*On fail goto*//*Label 1650*/ 65443, // Rule ID 1230 // 26513 GIM_CheckFeatures, GIFBS_HasNEON, 26514 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, 26515 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26516 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 26517 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 26518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 26520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 26521 // (intrinsic_wo_chain:{ *:[i64] } 292:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQDMULLi32:{ *:[i64] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) 26522 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLi32, 26523 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26524 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26526 GIR_EraseFromParent, /*InsnID*/0, 26527 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26528 // GIR_Coverage, 1230, 26529 GIR_Done, 26530 // Label 1650: @65443 26531 GIM_Try, /*On fail goto*//*Label 1651*/ 65495, // Rule ID 1243 // 26532 GIM_CheckFeatures, GIFBS_HasNEON, 26533 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, 26534 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26535 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26536 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 26537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26539 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26540 // (intrinsic_wo_chain:{ *:[i64] } 319:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn) => (SUQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn) 26541 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv1i64, 26542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 26543 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 26544 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 26545 GIR_EraseFromParent, /*InsnID*/0, 26546 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26547 // GIR_Coverage, 1243, 26548 GIR_Done, 26549 // Label 1651: @65495 26550 GIM_Try, /*On fail goto*//*Label 1652*/ 65547, // Rule ID 1244 // 26551 GIM_CheckFeatures, GIFBS_HasNEON, 26552 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, 26553 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 26554 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 26555 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 26556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 26557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 26558 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 26559 // (intrinsic_wo_chain:{ *:[i32] } 319:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn) => (SUQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn) 26560 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv1i32, 26561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 26562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 26563 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 26564 GIR_EraseFromParent, /*InsnID*/0, 26565 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26566 // GIR_Coverage, 1244, 26567 GIR_Done, 26568 // Label 1652: @65547 26569 GIM_Try, /*On fail goto*//*Label 1653*/ 65599, // Rule ID 1249 // 26570 GIM_CheckFeatures, GIFBS_HasNEON, 26571 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, 26572 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 26573 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26574 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 26575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26577 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26578 // (intrinsic_wo_chain:{ *:[i64] } 355:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn) => (USQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn) 26579 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv1i64, 26580 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 26581 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 26582 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 26583 GIR_EraseFromParent, /*InsnID*/0, 26584 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26585 // GIR_Coverage, 1249, 26586 GIR_Done, 26587 // Label 1653: @65599 26588 GIM_Try, /*On fail goto*//*Label 1654*/ 65651, // Rule ID 1250 // 26589 GIM_CheckFeatures, GIFBS_HasNEON, 26590 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, 26591 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 26592 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 26593 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 26594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 26595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 26596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 26597 // (intrinsic_wo_chain:{ *:[i32] } 355:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn) => (USQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn) 26598 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv1i32, 26599 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 26600 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 26601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 26602 GIR_EraseFromParent, /*InsnID*/0, 26603 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26604 // GIR_Coverage, 1250, 26605 GIR_Done, 26606 // Label 1654: @65651 26607 GIM_Try, /*On fail goto*//*Label 1655*/ 65703, // Rule ID 1251 // 26608 GIM_CheckFeatures, GIFBS_HasNEON, 26609 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addhn, 26610 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 26611 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 26612 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 26613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 26615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 26616 // (intrinsic_wo_chain:{ *:[v8i8] } 214:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 26617 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv8i16_v8i8, 26618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26620 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26621 GIR_EraseFromParent, /*InsnID*/0, 26622 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26623 // GIR_Coverage, 1251, 26624 GIR_Done, 26625 // Label 1655: @65703 26626 GIM_Try, /*On fail goto*//*Label 1656*/ 65755, // Rule ID 1252 // 26627 GIM_CheckFeatures, GIFBS_HasNEON, 26628 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addhn, 26629 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 26630 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 26631 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 26632 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26633 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 26634 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 26635 // (intrinsic_wo_chain:{ *:[v4i16] } 214:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 26636 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv4i32_v4i16, 26637 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26638 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26639 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26640 GIR_EraseFromParent, /*InsnID*/0, 26641 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26642 // GIR_Coverage, 1252, 26643 GIR_Done, 26644 // Label 1656: @65755 26645 GIM_Try, /*On fail goto*//*Label 1657*/ 65807, // Rule ID 1253 // 26646 GIM_CheckFeatures, GIFBS_HasNEON, 26647 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addhn, 26648 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 26649 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 26650 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 26651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 26653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 26654 // (intrinsic_wo_chain:{ *:[v2i32] } 214:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) 26655 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv2i64_v2i32, 26656 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26659 GIR_EraseFromParent, /*InsnID*/0, 26660 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26661 // GIR_Coverage, 1253, 26662 GIR_Done, 26663 // Label 1657: @65807 26664 GIM_Try, /*On fail goto*//*Label 1658*/ 65859, // Rule ID 1254 // 26665 GIM_CheckFeatures, GIFBS_HasNEON, 26666 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_subhn, 26667 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 26668 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 26669 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 26670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 26672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 26673 // (intrinsic_wo_chain:{ *:[v8i8] } 318:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 26674 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv8i16_v8i8, 26675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26678 GIR_EraseFromParent, /*InsnID*/0, 26679 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26680 // GIR_Coverage, 1254, 26681 GIR_Done, 26682 // Label 1658: @65859 26683 GIM_Try, /*On fail goto*//*Label 1659*/ 65911, // Rule ID 1255 // 26684 GIM_CheckFeatures, GIFBS_HasNEON, 26685 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_subhn, 26686 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 26687 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 26688 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 26689 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26690 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 26691 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 26692 // (intrinsic_wo_chain:{ *:[v4i16] } 318:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 26693 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv4i32_v4i16, 26694 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26696 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26697 GIR_EraseFromParent, /*InsnID*/0, 26698 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26699 // GIR_Coverage, 1255, 26700 GIR_Done, 26701 // Label 1659: @65911 26702 GIM_Try, /*On fail goto*//*Label 1660*/ 65963, // Rule ID 1256 // 26703 GIM_CheckFeatures, GIFBS_HasNEON, 26704 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_subhn, 26705 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 26706 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 26707 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 26708 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 26710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 26711 // (intrinsic_wo_chain:{ *:[v2i32] } 318:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) 26712 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv2i64_v2i32, 26713 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26716 GIR_EraseFromParent, /*InsnID*/0, 26717 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26718 // GIR_Coverage, 1256, 26719 GIR_Done, 26720 // Label 1660: @65963 26721 GIM_Try, /*On fail goto*//*Label 1661*/ 66015, // Rule ID 1257 // 26722 GIM_CheckFeatures, GIFBS_HasNEON, 26723 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_raddhn, 26724 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 26725 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 26726 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 26727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26728 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 26729 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 26730 // (intrinsic_wo_chain:{ *:[v8i8] } 266:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (RADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 26731 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv8i16_v8i8, 26732 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26733 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26735 GIR_EraseFromParent, /*InsnID*/0, 26736 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26737 // GIR_Coverage, 1257, 26738 GIR_Done, 26739 // Label 1661: @66015 26740 GIM_Try, /*On fail goto*//*Label 1662*/ 66067, // Rule ID 1258 // 26741 GIM_CheckFeatures, GIFBS_HasNEON, 26742 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_raddhn, 26743 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 26744 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 26745 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 26746 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26747 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 26748 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 26749 // (intrinsic_wo_chain:{ *:[v4i16] } 266:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (RADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 26750 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv4i32_v4i16, 26751 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26754 GIR_EraseFromParent, /*InsnID*/0, 26755 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26756 // GIR_Coverage, 1258, 26757 GIR_Done, 26758 // Label 1662: @66067 26759 GIM_Try, /*On fail goto*//*Label 1663*/ 66119, // Rule ID 1259 // 26760 GIM_CheckFeatures, GIFBS_HasNEON, 26761 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_raddhn, 26762 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 26763 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 26764 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 26765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 26767 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 26768 // (intrinsic_wo_chain:{ *:[v2i32] } 266:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (RADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) 26769 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv2i64_v2i32, 26770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26771 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26772 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26773 GIR_EraseFromParent, /*InsnID*/0, 26774 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26775 // GIR_Coverage, 1259, 26776 GIR_Done, 26777 // Label 1663: @66119 26778 GIM_Try, /*On fail goto*//*Label 1664*/ 66171, // Rule ID 1260 // 26779 GIM_CheckFeatures, GIFBS_HasNEON, 26780 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, 26781 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 26782 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 26783 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 26784 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26785 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 26786 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 26787 // (intrinsic_wo_chain:{ *:[v8i8] } 269:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (RSUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) 26788 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv8i16_v8i8, 26789 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26790 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26791 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26792 GIR_EraseFromParent, /*InsnID*/0, 26793 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26794 // GIR_Coverage, 1260, 26795 GIR_Done, 26796 // Label 1664: @66171 26797 GIM_Try, /*On fail goto*//*Label 1665*/ 66223, // Rule ID 1261 // 26798 GIM_CheckFeatures, GIFBS_HasNEON, 26799 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, 26800 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 26801 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 26802 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 26803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26804 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 26805 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 26806 // (intrinsic_wo_chain:{ *:[v4i16] } 269:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (RSUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 26807 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv4i32_v4i16, 26808 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26809 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26810 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26811 GIR_EraseFromParent, /*InsnID*/0, 26812 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26813 // GIR_Coverage, 1261, 26814 GIR_Done, 26815 // Label 1665: @66223 26816 GIM_Try, /*On fail goto*//*Label 1666*/ 66275, // Rule ID 1262 // 26817 GIM_CheckFeatures, GIFBS_HasNEON, 26818 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, 26819 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 26820 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 26821 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 26822 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 26823 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 26824 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 26825 // (intrinsic_wo_chain:{ *:[v2i32] } 269:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (RSUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) 26826 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv2i64_v2i32, 26827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26829 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26830 GIR_EraseFromParent, /*InsnID*/0, 26831 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26832 // GIR_Coverage, 1262, 26833 GIR_Done, 26834 // Label 1666: @66275 26835 GIM_Try, /*On fail goto*//*Label 1667*/ 66327, // Rule ID 1263 // 26836 GIM_CheckFeatures, GIFBS_HasNEON, 26837 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_pmull, 26838 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 26839 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 26840 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 26841 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 26842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26844 // (intrinsic_wo_chain:{ *:[v8i16] } 264:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (PMULLv8i8:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 26845 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PMULLv8i8, 26846 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26847 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26848 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26849 GIR_EraseFromParent, /*InsnID*/0, 26850 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26851 // GIR_Coverage, 1263, 26852 GIR_Done, 26853 // Label 1667: @66327 26854 GIM_Try, /*On fail goto*//*Label 1668*/ 66379, // Rule ID 1300 // 26855 GIM_CheckFeatures, GIFBS_HasNEON, 26856 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smull, 26857 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 26858 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 26859 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 26860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 26861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26863 // (intrinsic_wo_chain:{ *:[v8i16] } 287:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMULLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 26864 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMULLv8i8_v8i16, 26865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26866 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26867 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26868 GIR_EraseFromParent, /*InsnID*/0, 26869 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26870 // GIR_Coverage, 1300, 26871 GIR_Done, 26872 // Label 1668: @66379 26873 GIM_Try, /*On fail goto*//*Label 1669*/ 66431, // Rule ID 1302 // 26874 GIM_CheckFeatures, GIFBS_HasNEON, 26875 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smull, 26876 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 26877 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 26878 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 26879 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 26880 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26881 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26882 // (intrinsic_wo_chain:{ *:[v4i32] } 287:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMULLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 26883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMULLv4i16_v4i32, 26884 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26885 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26886 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26887 GIR_EraseFromParent, /*InsnID*/0, 26888 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26889 // GIR_Coverage, 1302, 26890 GIR_Done, 26891 // Label 1669: @66431 26892 GIM_Try, /*On fail goto*//*Label 1670*/ 66483, // Rule ID 1304 // 26893 GIM_CheckFeatures, GIFBS_HasNEON, 26894 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smull, 26895 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 26896 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 26897 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 26898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 26899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26901 // (intrinsic_wo_chain:{ *:[v2i64] } 287:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMULLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 26902 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMULLv2i32_v2i64, 26903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26904 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26905 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26906 GIR_EraseFromParent, /*InsnID*/0, 26907 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26908 // GIR_Coverage, 1304, 26909 GIR_Done, 26910 // Label 1670: @66483 26911 GIM_Try, /*On fail goto*//*Label 1671*/ 66535, // Rule ID 1314 // 26912 GIM_CheckFeatures, GIFBS_HasNEON, 26913 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, 26914 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 26915 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 26916 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 26917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 26918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26920 // (intrinsic_wo_chain:{ *:[v4i32] } 291:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQDMULLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 26921 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLv4i16_v4i32, 26922 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26923 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26924 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26925 GIR_EraseFromParent, /*InsnID*/0, 26926 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26927 // GIR_Coverage, 1314, 26928 GIR_Done, 26929 // Label 1671: @66535 26930 GIM_Try, /*On fail goto*//*Label 1672*/ 66587, // Rule ID 1316 // 26931 GIM_CheckFeatures, GIFBS_HasNEON, 26932 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, 26933 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 26934 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 26935 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 26936 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 26937 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26938 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26939 // (intrinsic_wo_chain:{ *:[v2i64] } 291:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQDMULLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 26940 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLv2i32_v2i64, 26941 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26942 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26943 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26944 GIR_EraseFromParent, /*InsnID*/0, 26945 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26946 // GIR_Coverage, 1316, 26947 GIR_Done, 26948 // Label 1672: @66587 26949 GIM_Try, /*On fail goto*//*Label 1673*/ 66639, // Rule ID 1360 // 26950 GIM_CheckFeatures, GIFBS_HasNEON, 26951 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umull, 26952 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 26953 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 26954 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 26955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 26956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26958 // (intrinsic_wo_chain:{ *:[v8i16] } 341:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMULLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 26959 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMULLv8i8_v8i16, 26960 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26961 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26962 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26963 GIR_EraseFromParent, /*InsnID*/0, 26964 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26965 // GIR_Coverage, 1360, 26966 GIR_Done, 26967 // Label 1673: @66639 26968 GIM_Try, /*On fail goto*//*Label 1674*/ 66691, // Rule ID 1362 // 26969 GIM_CheckFeatures, GIFBS_HasNEON, 26970 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umull, 26971 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 26972 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 26973 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 26974 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 26975 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26976 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26977 // (intrinsic_wo_chain:{ *:[v4i32] } 341:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMULLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 26978 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMULLv4i16_v4i32, 26979 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26980 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 26981 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 26982 GIR_EraseFromParent, /*InsnID*/0, 26983 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26984 // GIR_Coverage, 1362, 26985 GIR_Done, 26986 // Label 1674: @66691 26987 GIM_Try, /*On fail goto*//*Label 1675*/ 66743, // Rule ID 1364 // 26988 GIM_CheckFeatures, GIFBS_HasNEON, 26989 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umull, 26990 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 26991 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 26992 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 26993 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 26994 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 26995 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 26996 // (intrinsic_wo_chain:{ *:[v2i64] } 341:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMULLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 26997 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMULLv2i32_v2i64, 26998 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 26999 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27000 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27001 GIR_EraseFromParent, /*InsnID*/0, 27002 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27003 // GIR_Coverage, 1364, 27004 GIR_Done, 27005 // Label 1675: @66743 27006 GIM_Try, /*On fail goto*//*Label 1676*/ 66795, // Rule ID 1742 // 27007 GIM_CheckFeatures, GIFBS_HasAES, 27008 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aese, 27009 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 27010 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 27011 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 27012 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 27013 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 27014 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 27015 // (intrinsic_wo_chain:{ *:[v16i8] } 191:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (AESErr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) 27016 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESErr, 27017 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27018 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 27019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 27020 GIR_EraseFromParent, /*InsnID*/0, 27021 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27022 // GIR_Coverage, 1742, 27023 GIR_Done, 27024 // Label 1676: @66795 27025 GIM_Try, /*On fail goto*//*Label 1677*/ 66847, // Rule ID 1743 // 27026 GIM_CheckFeatures, GIFBS_HasAES, 27027 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesd, 27028 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 27029 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 27030 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 27031 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 27032 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 27033 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 27034 // (intrinsic_wo_chain:{ *:[v16i8] } 190:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (AESDrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) 27035 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESDrr, 27036 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27037 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 27038 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 27039 GIR_EraseFromParent, /*InsnID*/0, 27040 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27041 // GIR_Coverage, 1743, 27042 GIR_Done, 27043 // Label 1677: @66847 27044 GIM_Try, /*On fail goto*//*Label 1678*/ 66899, // Rule ID 1754 // 27045 GIM_CheckFeatures, GIFBS_HasSHA2, 27046 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1su1, 27047 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 27048 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 27049 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 27050 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 27051 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 27052 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 27053 // (intrinsic_wo_chain:{ *:[v4i32] } 199:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (SHA1SU1rr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) 27054 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1SU1rr, 27055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27056 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 27057 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 27058 GIR_EraseFromParent, /*InsnID*/0, 27059 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27060 // GIR_Coverage, 1754, 27061 GIR_Done, 27062 // Label 1678: @66899 27063 GIM_Try, /*On fail goto*//*Label 1679*/ 66951, // Rule ID 1755 // 27064 GIM_CheckFeatures, GIFBS_HasSHA2, 27065 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha256su0, 27066 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 27067 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 27068 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 27069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 27070 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 27071 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 27072 // (intrinsic_wo_chain:{ *:[v4i32] } 202:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (SHA256SU0rr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) 27073 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256SU0rr, 27074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27075 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 27076 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 27077 GIR_EraseFromParent, /*InsnID*/0, 27078 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27079 // GIR_Coverage, 1755, 27080 GIR_Done, 27081 // Label 1679: @66951 27082 GIM_Try, /*On fail goto*//*Label 1680*/ 67003, // Rule ID 1789 // 27083 GIM_CheckFeatures, GIFBS_HasNEON, 27084 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, 27085 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27086 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27087 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27091 // (intrinsic_wo_chain:{ *:[i64] } 289:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) 27092 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv1i64, 27093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27095 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27096 GIR_EraseFromParent, /*InsnID*/0, 27097 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27098 // GIR_Coverage, 1789, 27099 GIR_Done, 27100 // Label 1680: @67003 27101 GIM_Try, /*On fail goto*//*Label 1681*/ 67055, // Rule ID 1790 // 27102 GIM_CheckFeatures, GIFBS_HasNEON, 27103 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, 27104 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 27105 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 27106 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 27107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 27108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 27109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 27110 // (intrinsic_wo_chain:{ *:[i32] } 289:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) 27111 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv1i32, 27112 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27114 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27115 GIR_EraseFromParent, /*InsnID*/0, 27116 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27117 // GIR_Coverage, 1790, 27118 GIR_Done, 27119 // Label 1681: @67055 27120 GIM_Try, /*On fail goto*//*Label 1682*/ 67107, // Rule ID 1791 // 27121 GIM_CheckFeatures, GIFBS_HasNEON, 27122 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fabd, 27123 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27124 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27125 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27128 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27129 // (intrinsic_wo_chain:{ *:[v1f64] } 366:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FABD64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) 27130 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD64, 27131 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27134 GIR_EraseFromParent, /*InsnID*/0, 27135 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27136 // GIR_Coverage, 1791, 27137 GIR_Done, 27138 // Label 1682: @67107 27139 GIM_Try, /*On fail goto*//*Label 1683*/ 67159, // Rule ID 1792 // 27140 GIM_CheckFeatures, GIFBS_HasNEON, 27141 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, 27142 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27143 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27144 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27146 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27147 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27148 // (intrinsic_wo_chain:{ *:[v1i64] } 218:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FACGE64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) 27149 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGE64, 27150 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27151 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27152 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27153 GIR_EraseFromParent, /*InsnID*/0, 27154 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27155 // GIR_Coverage, 1792, 27156 GIR_Done, 27157 // Label 1683: @67159 27158 GIM_Try, /*On fail goto*//*Label 1684*/ 67211, // Rule ID 1797 // 27159 GIM_CheckFeatures, GIFBS_HasNEON, 27160 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, 27161 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27162 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27163 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27164 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27167 // (intrinsic_wo_chain:{ *:[v1i64] } 319:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn) => (SUQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn) 27168 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv1i64, 27169 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27170 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 27171 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 27172 GIR_EraseFromParent, /*InsnID*/0, 27173 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27174 // GIR_Coverage, 1797, 27175 GIR_Done, 27176 // Label 1684: @67211 27177 GIM_Try, /*On fail goto*//*Label 1685*/ 67261, // Rule ID 1854 // 27178 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_udiv, 27179 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 27180 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 27181 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 27182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 27183 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 27184 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 27185 // (intrinsic_wo_chain:{ *:[i32] } 372:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (UDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 27186 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDIVWr, 27187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27190 GIR_EraseFromParent, /*InsnID*/0, 27191 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27192 // GIR_Coverage, 1854, 27193 GIR_Done, 27194 // Label 1685: @67261 27195 GIM_Try, /*On fail goto*//*Label 1686*/ 67311, // Rule ID 1855 // 27196 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_udiv, 27197 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27198 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27199 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 27201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 27202 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, 27203 // (intrinsic_wo_chain:{ *:[i64] } 372:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (UDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) 27204 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDIVXr, 27205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27206 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27207 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27208 GIR_EraseFromParent, /*InsnID*/0, 27209 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27210 // GIR_Coverage, 1855, 27211 GIR_Done, 27212 // Label 1686: @67311 27213 GIM_Try, /*On fail goto*//*Label 1687*/ 67361, // Rule ID 1856 // 27214 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sdiv, 27215 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 27216 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 27217 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 27218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 27219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, 27220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, 27221 // (intrinsic_wo_chain:{ *:[i32] } 365:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (SDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 27222 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDIVWr, 27223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27226 GIR_EraseFromParent, /*InsnID*/0, 27227 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27228 // GIR_Coverage, 1856, 27229 GIR_Done, 27230 // Label 1687: @67361 27231 GIM_Try, /*On fail goto*//*Label 1688*/ 67411, // Rule ID 1857 // 27232 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sdiv, 27233 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27234 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27235 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 27237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 27238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, 27239 // (intrinsic_wo_chain:{ *:[i64] } 365:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) 27240 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDIVXr, 27241 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27242 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27243 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27244 GIR_EraseFromParent, /*InsnID*/0, 27245 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27246 // GIR_Coverage, 1857, 27247 GIR_Done, 27248 // Label 1688: @67411 27249 GIM_Try, /*On fail goto*//*Label 1689*/ 67461, // Rule ID 2405 // 27250 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, 27251 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27252 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27253 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27255 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27256 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27257 // (intrinsic_wo_chain:{ *:[v1f64] } 217:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FABD64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) 27258 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD64, 27259 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27262 GIR_EraseFromParent, /*InsnID*/0, 27263 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27264 // GIR_Coverage, 2405, 27265 GIR_Done, 27266 // Label 1689: @67461 27267 GIM_Try, /*On fail goto*//*Label 1690*/ 67513, // Rule ID 2409 // 27268 GIM_CheckFeatures, GIFBS_HasNEON, 27269 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, 27270 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27271 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27272 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27274 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27275 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27276 // (intrinsic_wo_chain:{ *:[v1i64] } 219:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FACGT64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) 27277 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGT64, 27278 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27279 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27280 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27281 GIR_EraseFromParent, /*InsnID*/0, 27282 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27283 // GIR_Coverage, 2409, 27284 GIR_Done, 27285 // Label 1690: @67513 27286 GIM_Try, /*On fail goto*//*Label 1691*/ 67565, // Rule ID 2413 // 27287 GIM_CheckFeatures, GIFBS_HasNEON, 27288 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, 27289 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27290 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27291 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27292 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27295 // (intrinsic_wo_chain:{ *:[v1f64] } 244:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FMULX64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) 27296 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX64, 27297 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27298 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27299 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27300 GIR_EraseFromParent, /*InsnID*/0, 27301 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27302 // GIR_Coverage, 2413, 27303 GIR_Done, 27304 // Label 1691: @67565 27305 GIM_Try, /*On fail goto*//*Label 1692*/ 67617, // Rule ID 2414 // 27306 GIM_CheckFeatures, GIFBS_HasNEON, 27307 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, 27308 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27309 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27310 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27311 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27314 // (intrinsic_wo_chain:{ *:[v1f64] } 246:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FRECPS64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) 27315 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS64, 27316 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27317 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27318 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27319 GIR_EraseFromParent, /*InsnID*/0, 27320 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27321 // GIR_Coverage, 2414, 27322 GIR_Done, 27323 // Label 1692: @67617 27324 GIM_Try, /*On fail goto*//*Label 1693*/ 67669, // Rule ID 2415 // 27325 GIM_CheckFeatures, GIFBS_HasNEON, 27326 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, 27327 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27328 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27329 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27333 // (intrinsic_wo_chain:{ *:[v1f64] } 250:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FRSQRTS64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) 27334 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS64, 27335 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27336 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27337 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27338 GIR_EraseFromParent, /*InsnID*/0, 27339 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27340 // GIR_Coverage, 2415, 27341 GIR_Done, 27342 // Label 1693: @67669 27343 GIM_Try, /*On fail goto*//*Label 1694*/ 67721, // Rule ID 2416 // 27344 GIM_CheckFeatures, GIFBS_HasNEON, 27345 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, 27346 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27347 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27348 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27351 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27352 // (intrinsic_wo_chain:{ *:[i64] } 295:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) 27353 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv1i64, 27354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27356 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27357 GIR_EraseFromParent, /*InsnID*/0, 27358 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27359 // GIR_Coverage, 2416, 27360 GIR_Done, 27361 // Label 1694: @67721 27362 GIM_Try, /*On fail goto*//*Label 1695*/ 67773, // Rule ID 2417 // 27363 GIM_CheckFeatures, GIFBS_HasNEON, 27364 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, 27365 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 27366 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 27367 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 27368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 27369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 27370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 27371 // (intrinsic_wo_chain:{ *:[i32] } 295:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQRSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) 27372 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv1i32, 27373 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27374 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27375 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27376 GIR_EraseFromParent, /*InsnID*/0, 27377 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27378 // GIR_Coverage, 2417, 27379 GIR_Done, 27380 // Label 1695: @67773 27381 GIM_Try, /*On fail goto*//*Label 1696*/ 67825, // Rule ID 2418 // 27382 GIM_CheckFeatures, GIFBS_HasNEON, 27383 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, 27384 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27385 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27386 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27387 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27388 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27390 // (intrinsic_wo_chain:{ *:[i64] } 298:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) 27391 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv1i64, 27392 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27393 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27394 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27395 GIR_EraseFromParent, /*InsnID*/0, 27396 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27397 // GIR_Coverage, 2418, 27398 GIR_Done, 27399 // Label 1696: @67825 27400 GIM_Try, /*On fail goto*//*Label 1697*/ 67877, // Rule ID 2419 // 27401 GIM_CheckFeatures, GIFBS_HasNEON, 27402 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, 27403 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 27404 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 27405 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 27406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 27407 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 27408 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 27409 // (intrinsic_wo_chain:{ *:[i32] } 298:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) 27410 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv1i32, 27411 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27412 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27413 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27414 GIR_EraseFromParent, /*InsnID*/0, 27415 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27416 // GIR_Coverage, 2419, 27417 GIR_Done, 27418 // Label 1697: @67877 27419 GIM_Try, /*On fail goto*//*Label 1698*/ 67929, // Rule ID 2420 // 27420 GIM_CheckFeatures, GIFBS_HasNEON, 27421 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, 27422 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27423 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27424 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27427 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27428 // (intrinsic_wo_chain:{ *:[i64] } 302:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQSUBv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) 27429 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv1i64, 27430 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27431 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27432 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27433 GIR_EraseFromParent, /*InsnID*/0, 27434 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27435 // GIR_Coverage, 2420, 27436 GIR_Done, 27437 // Label 1698: @67929 27438 GIM_Try, /*On fail goto*//*Label 1699*/ 67981, // Rule ID 2421 // 27439 GIM_CheckFeatures, GIFBS_HasNEON, 27440 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, 27441 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 27442 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 27443 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 27444 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 27445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 27446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 27447 // (intrinsic_wo_chain:{ *:[i32] } 302:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQSUBv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) 27448 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv1i32, 27449 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27450 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27451 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27452 GIR_EraseFromParent, /*InsnID*/0, 27453 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27454 // GIR_Coverage, 2421, 27455 GIR_Done, 27456 // Label 1699: @67981 27457 GIM_Try, /*On fail goto*//*Label 1700*/ 68033, // Rule ID 2422 // 27458 GIM_CheckFeatures, GIFBS_HasNEON, 27459 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, 27460 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27461 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27462 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27463 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27464 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27466 // (intrinsic_wo_chain:{ *:[i64] } 342:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) 27467 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv1i64, 27468 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27469 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27470 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27471 GIR_EraseFromParent, /*InsnID*/0, 27472 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27473 // GIR_Coverage, 2422, 27474 GIR_Done, 27475 // Label 1700: @68033 27476 GIM_Try, /*On fail goto*//*Label 1701*/ 68085, // Rule ID 2423 // 27477 GIM_CheckFeatures, GIFBS_HasNEON, 27478 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, 27479 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 27480 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 27481 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 27482 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 27483 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 27484 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 27485 // (intrinsic_wo_chain:{ *:[i32] } 342:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) 27486 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv1i32, 27487 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27488 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27489 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27490 GIR_EraseFromParent, /*InsnID*/0, 27491 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27492 // GIR_Coverage, 2423, 27493 GIR_Done, 27494 // Label 1701: @68085 27495 GIM_Try, /*On fail goto*//*Label 1702*/ 68137, // Rule ID 2424 // 27496 GIM_CheckFeatures, GIFBS_HasNEON, 27497 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, 27498 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27499 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27500 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27501 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27502 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27504 // (intrinsic_wo_chain:{ *:[i64] } 343:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) 27505 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv1i64, 27506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27507 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27508 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27509 GIR_EraseFromParent, /*InsnID*/0, 27510 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27511 // GIR_Coverage, 2424, 27512 GIR_Done, 27513 // Label 1702: @68137 27514 GIM_Try, /*On fail goto*//*Label 1703*/ 68189, // Rule ID 2425 // 27515 GIM_CheckFeatures, GIFBS_HasNEON, 27516 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, 27517 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 27518 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 27519 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 27520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 27521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 27522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 27523 // (intrinsic_wo_chain:{ *:[i32] } 343:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQRSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) 27524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv1i32, 27525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27528 GIR_EraseFromParent, /*InsnID*/0, 27529 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27530 // GIR_Coverage, 2425, 27531 GIR_Done, 27532 // Label 1703: @68189 27533 GIM_Try, /*On fail goto*//*Label 1704*/ 68241, // Rule ID 2426 // 27534 GIM_CheckFeatures, GIFBS_HasNEON, 27535 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, 27536 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27537 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27538 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27539 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27540 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27542 // (intrinsic_wo_chain:{ *:[i64] } 345:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) 27543 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv1i64, 27544 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27545 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27546 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27547 GIR_EraseFromParent, /*InsnID*/0, 27548 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27549 // GIR_Coverage, 2426, 27550 GIR_Done, 27551 // Label 1704: @68241 27552 GIM_Try, /*On fail goto*//*Label 1705*/ 68293, // Rule ID 2427 // 27553 GIM_CheckFeatures, GIFBS_HasNEON, 27554 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, 27555 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 27556 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 27557 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 27558 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 27559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 27560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 27561 // (intrinsic_wo_chain:{ *:[i32] } 345:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) 27562 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv1i32, 27563 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27564 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27565 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27566 GIR_EraseFromParent, /*InsnID*/0, 27567 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27568 // GIR_Coverage, 2427, 27569 GIR_Done, 27570 // Label 1705: @68293 27571 GIM_Try, /*On fail goto*//*Label 1706*/ 68345, // Rule ID 2428 // 27572 GIM_CheckFeatures, GIFBS_HasNEON, 27573 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, 27574 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27575 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27576 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27577 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27578 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27580 // (intrinsic_wo_chain:{ *:[i64] } 347:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQSUBv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) 27581 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv1i64, 27582 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27583 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27584 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27585 GIR_EraseFromParent, /*InsnID*/0, 27586 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27587 // GIR_Coverage, 2428, 27588 GIR_Done, 27589 // Label 1706: @68345 27590 GIM_Try, /*On fail goto*//*Label 1707*/ 68397, // Rule ID 2429 // 27591 GIM_CheckFeatures, GIFBS_HasNEON, 27592 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, 27593 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 27594 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 27595 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 27596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 27597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 27598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 27599 // (intrinsic_wo_chain:{ *:[i32] } 347:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQSUBv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) 27600 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv1i32, 27601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27604 GIR_EraseFromParent, /*InsnID*/0, 27605 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27606 // GIR_Coverage, 2429, 27607 GIR_Done, 27608 // Label 1707: @68397 27609 GIM_Try, /*On fail goto*//*Label 1708*/ 68449, // Rule ID 2444 // 27610 GIM_CheckFeatures, GIFBS_HasNEON, 27611 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, 27612 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27613 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27614 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27617 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27618 // (intrinsic_wo_chain:{ *:[v1i64] } 355:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn) => (USQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn) 27619 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv1i64, 27620 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27621 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 27622 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 27623 GIR_EraseFromParent, /*InsnID*/0, 27624 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27625 // GIR_Coverage, 2444, 27626 GIR_Done, 27627 // Label 1708: @68449 27628 GIM_Try, /*On fail goto*//*Label 1709*/ 68499, // Rule ID 2540 // 27629 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_pmull64, 27630 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 27631 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27632 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27633 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 27634 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27635 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27636 // (intrinsic_wo_chain:{ *:[v16i8] } 265:{ *:[iPTR] }, V64:{ *:[i64] }:$Rn, V64:{ *:[i64] }:$Rm) => (PMULLv1i64:{ *:[v16i8] } V64:{ *:[i64] }:$Rn, V64:{ *:[i64] }:$Rm) 27637 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PMULLv1i64, 27638 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27639 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27640 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27641 GIR_EraseFromParent, /*InsnID*/0, 27642 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27643 // GIR_Coverage, 2540, 27644 GIR_Done, 27645 // Label 1709: @68499 27646 GIM_Try, /*On fail goto*//*Label 1710*/ 68549, // Rule ID 2596 // 27647 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_tbl1, 27648 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 27649 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 27650 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 27651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 27653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27654 // (intrinsic_wo_chain:{ *:[v8i8] } 320:{ *:[iPTR] }, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri) => (TBLv8i8One:{ *:[v8i8] } VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri) 27655 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBLv8i8One, 27656 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd 27657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ri 27659 GIR_EraseFromParent, /*InsnID*/0, 27660 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27661 // GIR_Coverage, 2596, 27662 GIR_Done, 27663 // Label 1710: @68549 27664 GIM_Try, /*On fail goto*//*Label 1711*/ 68599, // Rule ID 2597 // 27665 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_tbl1, 27666 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 27667 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 27668 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 27669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 27670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 27671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 27672 // (intrinsic_wo_chain:{ *:[v16i8] } 320:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn) => (TBLv16i8One:{ *:[v16i8] } V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn) 27673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBLv16i8One, 27674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd 27675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ri 27676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 27677 GIR_EraseFromParent, /*InsnID*/0, 27678 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27679 // GIR_Coverage, 2597, 27680 GIR_Done, 27681 // Label 1711: @68599 27682 GIM_Try, /*On fail goto*//*Label 1712*/ 68649, // Rule ID 3451 // 27683 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, 27684 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27685 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27686 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27689 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27690 // (intrinsic_wo_chain:{ *:[i64] } 307:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) 27691 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv1i64, 27692 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27693 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27694 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27695 GIR_EraseFromParent, /*InsnID*/0, 27696 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27697 // GIR_Coverage, 3451, 27698 GIR_Done, 27699 // Label 1712: @68649 27700 GIM_Try, /*On fail goto*//*Label 1713*/ 68699, // Rule ID 3452 // 27701 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, 27702 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27703 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27704 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27705 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27706 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27707 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27708 // (intrinsic_wo_chain:{ *:[i64] } 353:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (USHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) 27709 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv1i64, 27710 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27711 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27712 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27713 GIR_EraseFromParent, /*InsnID*/0, 27714 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27715 // GIR_Coverage, 3452, 27716 GIR_Done, 27717 // Label 1713: @68699 27718 GIM_Try, /*On fail goto*//*Label 1714*/ 68749, // Rule ID 3453 // 27719 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, 27720 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27721 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27722 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27726 // (intrinsic_wo_chain:{ *:[i64] } 306:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) 27727 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv1i64, 27728 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27729 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27730 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27731 GIR_EraseFromParent, /*InsnID*/0, 27732 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27733 // GIR_Coverage, 3453, 27734 GIR_Done, 27735 // Label 1714: @68749 27736 GIM_Try, /*On fail goto*//*Label 1715*/ 68799, // Rule ID 3454 // 27737 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, 27738 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 27739 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27740 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27742 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27743 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27744 // (intrinsic_wo_chain:{ *:[i64] } 351:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (URSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) 27745 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv1i64, 27746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 27747 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 27748 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm 27749 GIR_EraseFromParent, /*InsnID*/0, 27750 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27751 // GIR_Coverage, 3454, 27752 GIR_Done, 27753 // Label 1715: @68799 27754 GIM_Reject, 27755 // Label 1290: @68800 27756 GIM_Try, /*On fail goto*//*Label 1716*/ 70766, 27757 GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, 27758 GIM_Try, /*On fail goto*//*Label 1717*/ 68876, // Rule ID 1616 // 27759 GIM_CheckFeatures, GIFBS_HasNEON, 27760 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli, 27761 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 27762 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 27763 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 27764 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 27765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27767 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27768 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 27769 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 27770 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL8, 27771 // MIs[1] Operand 1 27772 // No operand predicates 27773 GIM_CheckIsSafeToFold, /*InsnID*/1, 27774 // (intrinsic_wo_chain:{ *:[v8i8] } 363:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$imm) => (SLIv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) 27775 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv8i8_shift, 27776 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 27778 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 27779 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 27780 GIR_EraseFromParent, /*InsnID*/0, 27781 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27782 // GIR_Coverage, 1616, 27783 GIR_Done, 27784 // Label 1717: @68876 27785 GIM_Try, /*On fail goto*//*Label 1718*/ 68947, // Rule ID 1617 // 27786 GIM_CheckFeatures, GIFBS_HasNEON, 27787 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli, 27788 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 27789 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 27790 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 27791 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 27792 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 27793 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 27794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 27795 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 27796 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 27797 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL8, 27798 // MIs[1] Operand 1 27799 // No operand predicates 27800 GIM_CheckIsSafeToFold, /*InsnID*/1, 27801 // (intrinsic_wo_chain:{ *:[v16i8] } 363:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$imm) => (SLIv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) 27802 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv16i8_shift, 27803 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27804 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 27805 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 27806 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 27807 GIR_EraseFromParent, /*InsnID*/0, 27808 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27809 // GIR_Coverage, 1617, 27810 GIR_Done, 27811 // Label 1718: @68947 27812 GIM_Try, /*On fail goto*//*Label 1719*/ 69018, // Rule ID 1618 // 27813 GIM_CheckFeatures, GIFBS_HasNEON, 27814 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli, 27815 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 27816 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 27817 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 27818 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 27819 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27822 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 27823 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 27824 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL16, 27825 // MIs[1] Operand 1 27826 // No operand predicates 27827 GIM_CheckIsSafeToFold, /*InsnID*/1, 27828 // (intrinsic_wo_chain:{ *:[v4i16] } 363:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$imm) => (SLIv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) 27829 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv4i16_shift, 27830 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 27832 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 27833 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 27834 GIR_EraseFromParent, /*InsnID*/0, 27835 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27836 // GIR_Coverage, 1618, 27837 GIR_Done, 27838 // Label 1719: @69018 27839 GIM_Try, /*On fail goto*//*Label 1720*/ 69089, // Rule ID 1619 // 27840 GIM_CheckFeatures, GIFBS_HasNEON, 27841 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli, 27842 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 27843 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 27844 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 27845 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 27846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 27847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 27848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 27849 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 27850 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 27851 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL16, 27852 // MIs[1] Operand 1 27853 // No operand predicates 27854 GIM_CheckIsSafeToFold, /*InsnID*/1, 27855 // (intrinsic_wo_chain:{ *:[v8i16] } 363:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$imm) => (SLIv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) 27856 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv8i16_shift, 27857 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 27859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 27860 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 27861 GIR_EraseFromParent, /*InsnID*/0, 27862 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27863 // GIR_Coverage, 1619, 27864 GIR_Done, 27865 // Label 1720: @69089 27866 GIM_Try, /*On fail goto*//*Label 1721*/ 69160, // Rule ID 1620 // 27867 GIM_CheckFeatures, GIFBS_HasNEON, 27868 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli, 27869 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 27870 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 27871 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 27872 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 27873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27876 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 27877 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 27878 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL32, 27879 // MIs[1] Operand 1 27880 // No operand predicates 27881 GIM_CheckIsSafeToFold, /*InsnID*/1, 27882 // (intrinsic_wo_chain:{ *:[v2i32] } 363:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$imm) => (SLIv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) 27883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv2i32_shift, 27884 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27885 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 27886 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 27887 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 27888 GIR_EraseFromParent, /*InsnID*/0, 27889 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27890 // GIR_Coverage, 1620, 27891 GIR_Done, 27892 // Label 1721: @69160 27893 GIM_Try, /*On fail goto*//*Label 1722*/ 69231, // Rule ID 1621 // 27894 GIM_CheckFeatures, GIFBS_HasNEON, 27895 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli, 27896 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 27897 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 27898 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 27899 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 27900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 27901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 27902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 27903 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 27904 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 27905 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL32, 27906 // MIs[1] Operand 1 27907 // No operand predicates 27908 GIM_CheckIsSafeToFold, /*InsnID*/1, 27909 // (intrinsic_wo_chain:{ *:[v4i32] } 363:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$imm) => (SLIv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) 27910 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv4i32_shift, 27911 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27912 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 27913 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 27914 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 27915 GIR_EraseFromParent, /*InsnID*/0, 27916 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27917 // GIR_Coverage, 1621, 27918 GIR_Done, 27919 // Label 1722: @69231 27920 GIM_Try, /*On fail goto*//*Label 1723*/ 69302, // Rule ID 1622 // 27921 GIM_CheckFeatures, GIFBS_HasNEON, 27922 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli, 27923 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 27924 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 27925 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 27926 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 27927 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 27928 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 27929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 27930 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 27931 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 27932 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL64, 27933 // MIs[1] Operand 1 27934 // No operand predicates 27935 GIM_CheckIsSafeToFold, /*InsnID*/1, 27936 // (intrinsic_wo_chain:{ *:[v2i64] } 363:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL64>>:$imm) => (SLIv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) 27937 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv2i64_shift, 27938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 27940 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 27941 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 27942 GIR_EraseFromParent, /*InsnID*/0, 27943 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27944 // GIR_Coverage, 1622, 27945 GIR_Done, 27946 // Label 1723: @69302 27947 GIM_Try, /*On fail goto*//*Label 1724*/ 69373, // Rule ID 1649 // 27948 GIM_CheckFeatures, GIFBS_HasNEON, 27949 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri, 27950 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 27951 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 27952 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 27953 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 27954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 27955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 27956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 27957 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 27958 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 27959 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, 27960 // MIs[1] Operand 1 27961 // No operand predicates 27962 GIM_CheckIsSafeToFold, /*InsnID*/1, 27963 // (intrinsic_wo_chain:{ *:[v8i8] } 364:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm) => (SRIv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) 27964 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv8i8_shift, 27965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 27967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 27968 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 27969 GIR_EraseFromParent, /*InsnID*/0, 27970 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27971 // GIR_Coverage, 1649, 27972 GIR_Done, 27973 // Label 1724: @69373 27974 GIM_Try, /*On fail goto*//*Label 1725*/ 69444, // Rule ID 1650 // 27975 GIM_CheckFeatures, GIFBS_HasNEON, 27976 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri, 27977 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 27978 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 27979 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 27980 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 27981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 27982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 27983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 27984 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 27985 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 27986 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, 27987 // MIs[1] Operand 1 27988 // No operand predicates 27989 GIM_CheckIsSafeToFold, /*InsnID*/1, 27990 // (intrinsic_wo_chain:{ *:[v16i8] } 364:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm) => (SRIv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) 27991 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv16i8_shift, 27992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27993 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 27994 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 27995 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 27996 GIR_EraseFromParent, /*InsnID*/0, 27997 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27998 // GIR_Coverage, 1650, 27999 GIR_Done, 28000 // Label 1725: @69444 28001 GIM_Try, /*On fail goto*//*Label 1726*/ 69515, // Rule ID 1651 // 28002 GIM_CheckFeatures, GIFBS_HasNEON, 28003 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri, 28004 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, 28005 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 28006 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 28007 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 28008 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 28009 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 28010 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 28011 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 28012 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 28013 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, 28014 // MIs[1] Operand 1 28015 // No operand predicates 28016 GIM_CheckIsSafeToFold, /*InsnID*/1, 28017 // (intrinsic_wo_chain:{ *:[v4i16] } 364:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (SRIv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) 28018 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv4i16_shift, 28019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28020 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28021 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 28022 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 28023 GIR_EraseFromParent, /*InsnID*/0, 28024 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28025 // GIR_Coverage, 1651, 28026 GIR_Done, 28027 // Label 1726: @69515 28028 GIM_Try, /*On fail goto*//*Label 1727*/ 69586, // Rule ID 1652 // 28029 GIM_CheckFeatures, GIFBS_HasNEON, 28030 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri, 28031 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 28032 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 28033 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 28034 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 28035 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 28037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 28038 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 28039 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 28040 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, 28041 // MIs[1] Operand 1 28042 // No operand predicates 28043 GIM_CheckIsSafeToFold, /*InsnID*/1, 28044 // (intrinsic_wo_chain:{ *:[v8i16] } 364:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (SRIv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) 28045 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv8i16_shift, 28046 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 28049 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 28050 GIR_EraseFromParent, /*InsnID*/0, 28051 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28052 // GIR_Coverage, 1652, 28053 GIR_Done, 28054 // Label 1727: @69586 28055 GIM_Try, /*On fail goto*//*Label 1728*/ 69657, // Rule ID 1653 // 28056 GIM_CheckFeatures, GIFBS_HasNEON, 28057 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri, 28058 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 28059 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 28060 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 28061 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 28062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 28063 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 28064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 28065 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 28066 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 28067 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, 28068 // MIs[1] Operand 1 28069 // No operand predicates 28070 GIM_CheckIsSafeToFold, /*InsnID*/1, 28071 // (intrinsic_wo_chain:{ *:[v2i32] } 364:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SRIv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) 28072 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv2i32_shift, 28073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28075 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 28076 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 28077 GIR_EraseFromParent, /*InsnID*/0, 28078 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28079 // GIR_Coverage, 1653, 28080 GIR_Done, 28081 // Label 1728: @69657 28082 GIM_Try, /*On fail goto*//*Label 1729*/ 69728, // Rule ID 1654 // 28083 GIM_CheckFeatures, GIFBS_HasNEON, 28084 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri, 28085 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 28086 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 28087 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 28088 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 28089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 28091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 28092 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 28093 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 28094 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, 28095 // MIs[1] Operand 1 28096 // No operand predicates 28097 GIM_CheckIsSafeToFold, /*InsnID*/1, 28098 // (intrinsic_wo_chain:{ *:[v4i32] } 364:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SRIv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) 28099 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv4i32_shift, 28100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28101 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28102 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 28103 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 28104 GIR_EraseFromParent, /*InsnID*/0, 28105 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28106 // GIR_Coverage, 1654, 28107 GIR_Done, 28108 // Label 1729: @69728 28109 GIM_Try, /*On fail goto*//*Label 1730*/ 69799, // Rule ID 1655 // 28110 GIM_CheckFeatures, GIFBS_HasNEON, 28111 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri, 28112 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 28113 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 28114 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 28115 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 28116 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28117 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 28118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 28119 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 28120 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 28121 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, 28122 // MIs[1] Operand 1 28123 // No operand predicates 28124 GIM_CheckIsSafeToFold, /*InsnID*/1, 28125 // (intrinsic_wo_chain:{ *:[v2i64] } 364:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (SRIv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) 28126 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv2i64_shift, 28127 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28128 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28129 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 28130 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 28131 GIR_EraseFromParent, /*InsnID*/0, 28132 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28133 // GIR_Coverage, 1655, 28134 GIR_Done, 28135 // Label 1730: @69799 28136 GIM_Try, /*On fail goto*//*Label 1731*/ 69868, // Rule ID 2945 // 28137 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli, 28138 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 28139 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 28140 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 28141 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 28142 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 28143 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 28144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 28145 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 28146 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 28147 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL64, 28148 // MIs[1] Operand 1 28149 // No operand predicates 28150 GIM_CheckIsSafeToFold, /*InsnID*/1, 28151 // (intrinsic_wo_chain:{ *:[v1i64] } 363:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL64>>:$imm) => (SLId:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftL64>>:$imm) 28152 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLId, 28153 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28155 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 28156 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 28157 GIR_EraseFromParent, /*InsnID*/0, 28158 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28159 // GIR_Coverage, 2945, 28160 GIR_Done, 28161 // Label 1731: @69868 28162 GIM_Try, /*On fail goto*//*Label 1732*/ 69937, // Rule ID 2958 // 28163 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri, 28164 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 28165 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 28166 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 28167 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 28168 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 28169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 28170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 28171 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] 28172 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 28173 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, 28174 // MIs[1] Operand 1 28175 // No operand predicates 28176 GIM_CheckIsSafeToFold, /*InsnID*/1, 28177 // (intrinsic_wo_chain:{ *:[v1i64] } 364:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (SRId:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) 28178 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRId, 28179 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28180 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28181 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 28182 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 28183 GIR_EraseFromParent, /*InsnID*/0, 28184 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28185 // GIR_Coverage, 2958, 28186 GIR_Done, 28187 // Label 1732: @69937 28188 GIM_Try, /*On fail goto*//*Label 1733*/ 70001, // Rule ID 14 // 28189 GIM_CheckFeatures, GIFBS_HasDotProd, 28190 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sdot, 28191 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 28192 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 28193 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 28194 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, 28195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 28196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 28197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 28198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, 28199 // (intrinsic_wo_chain:{ *:[v2i32] } 277:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SDOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 28200 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDOTv8i8, 28201 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28202 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28203 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 28204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm 28205 GIR_EraseFromParent, /*InsnID*/0, 28206 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28207 // GIR_Coverage, 14, 28208 GIR_Done, 28209 // Label 1733: @70001 28210 GIM_Try, /*On fail goto*//*Label 1734*/ 70065, // Rule ID 15 // 28211 GIM_CheckFeatures, GIFBS_HasDotProd, 28212 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sdot, 28213 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 28214 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 28215 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 28216 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, 28217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 28219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 28220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, 28221 // (intrinsic_wo_chain:{ *:[v4i32] } 277:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SDOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 28222 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDOTv16i8, 28223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 28226 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm 28227 GIR_EraseFromParent, /*InsnID*/0, 28228 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28229 // GIR_Coverage, 15, 28230 GIR_Done, 28231 // Label 1734: @70065 28232 GIM_Try, /*On fail goto*//*Label 1735*/ 70129, // Rule ID 16 // 28233 GIM_CheckFeatures, GIFBS_HasDotProd, 28234 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_udot, 28235 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, 28236 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 28237 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, 28238 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, 28239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 28240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 28241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 28242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, 28243 // (intrinsic_wo_chain:{ *:[v2i32] } 332:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UDOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 28244 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDOTv8i8, 28245 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28246 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28247 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 28248 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm 28249 GIR_EraseFromParent, /*InsnID*/0, 28250 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28251 // GIR_Coverage, 16, 28252 GIR_Done, 28253 // Label 1735: @70129 28254 GIM_Try, /*On fail goto*//*Label 1736*/ 70193, // Rule ID 17 // 28255 GIM_CheckFeatures, GIFBS_HasDotProd, 28256 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_udot, 28257 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 28258 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 28259 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 28260 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, 28261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 28263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 28264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, 28265 // (intrinsic_wo_chain:{ *:[v4i32] } 332:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UDOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) 28266 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDOTv16i8, 28267 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28268 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 28270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm 28271 GIR_EraseFromParent, /*InsnID*/0, 28272 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28273 // GIR_Coverage, 17, 28274 GIR_Done, 28275 // Label 1736: @70193 28276 GIM_Try, /*On fail goto*//*Label 1737*/ 70257, // Rule ID 1746 // 28277 GIM_CheckFeatures, GIFBS_HasSHA2, 28278 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1c, 28279 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 28280 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 28281 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 28282 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 28283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 28285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 28286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, 28287 // (intrinsic_wo_chain:{ *:[v4i32] } 194:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1Crrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 28288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Crrr, 28289 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28290 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 28292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm 28293 GIR_EraseFromParent, /*InsnID*/0, 28294 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28295 // GIR_Coverage, 1746, 28296 GIR_Done, 28297 // Label 1737: @70257 28298 GIM_Try, /*On fail goto*//*Label 1738*/ 70321, // Rule ID 1747 // 28299 GIM_CheckFeatures, GIFBS_HasSHA2, 28300 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1p, 28301 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 28302 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 28303 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 28304 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 28305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 28307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 28308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, 28309 // (intrinsic_wo_chain:{ *:[v4i32] } 197:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1Prrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 28310 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Prrr, 28311 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28312 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28313 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 28314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm 28315 GIR_EraseFromParent, /*InsnID*/0, 28316 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28317 // GIR_Coverage, 1747, 28318 GIR_Done, 28319 // Label 1738: @70321 28320 GIM_Try, /*On fail goto*//*Label 1739*/ 70385, // Rule ID 1748 // 28321 GIM_CheckFeatures, GIFBS_HasSHA2, 28322 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1m, 28323 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 28324 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 28325 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 28326 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 28327 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 28329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 28330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, 28331 // (intrinsic_wo_chain:{ *:[v4i32] } 196:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1Mrrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 28332 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Mrrr, 28333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28334 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28335 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 28336 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm 28337 GIR_EraseFromParent, /*InsnID*/0, 28338 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28339 // GIR_Coverage, 1748, 28340 GIR_Done, 28341 // Label 1739: @70385 28342 GIM_Try, /*On fail goto*//*Label 1740*/ 70449, // Rule ID 1749 // 28343 GIM_CheckFeatures, GIFBS_HasSHA2, 28344 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1su0, 28345 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 28346 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 28347 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 28348 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 28349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 28351 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 28352 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, 28353 // (intrinsic_wo_chain:{ *:[v4i32] } 198:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1SU0rrr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 28354 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1SU0rrr, 28355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28356 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28357 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 28358 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm 28359 GIR_EraseFromParent, /*InsnID*/0, 28360 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28361 // GIR_Coverage, 1749, 28362 GIR_Done, 28363 // Label 1740: @70449 28364 GIM_Try, /*On fail goto*//*Label 1741*/ 70513, // Rule ID 1750 // 28365 GIM_CheckFeatures, GIFBS_HasSHA2, 28366 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha256h, 28367 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 28368 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 28369 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 28370 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 28371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28372 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 28373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 28374 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, 28375 // (intrinsic_wo_chain:{ *:[v4i32] } 200:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA256Hrrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 28376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256Hrrr, 28377 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28378 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 28380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm 28381 GIR_EraseFromParent, /*InsnID*/0, 28382 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28383 // GIR_Coverage, 1750, 28384 GIR_Done, 28385 // Label 1741: @70513 28386 GIM_Try, /*On fail goto*//*Label 1742*/ 70577, // Rule ID 1751 // 28387 GIM_CheckFeatures, GIFBS_HasSHA2, 28388 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha256h2, 28389 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 28390 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 28391 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 28392 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 28393 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28394 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 28395 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 28396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, 28397 // (intrinsic_wo_chain:{ *:[v4i32] } 201:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA256H2rrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 28398 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256H2rrr, 28399 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28400 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 28402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm 28403 GIR_EraseFromParent, /*InsnID*/0, 28404 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28405 // GIR_Coverage, 1751, 28406 GIR_Done, 28407 // Label 1742: @70577 28408 GIM_Try, /*On fail goto*//*Label 1743*/ 70641, // Rule ID 1752 // 28409 GIM_CheckFeatures, GIFBS_HasSHA2, 28410 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha256su1, 28411 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 28412 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 28413 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 28414 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 28415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 28417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 28418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, 28419 // (intrinsic_wo_chain:{ *:[v4i32] } 203:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA256SU1rrr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) 28420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256SU1rrr, 28421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28422 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28423 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 28424 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm 28425 GIR_EraseFromParent, /*InsnID*/0, 28426 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28427 // GIR_Coverage, 1752, 28428 GIR_Done, 28429 // Label 1743: @70641 28430 GIM_Try, /*On fail goto*//*Label 1744*/ 70703, // Rule ID 2598 // 28431 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_tbx1, 28432 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, 28433 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, 28434 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 28435 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, 28436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 28437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 28438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 28439 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, 28440 // (intrinsic_wo_chain:{ *:[v8i8] } 324:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri) => (TBXv8i8One:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri) 28441 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBXv8i8One, 28442 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28443 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28444 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn 28445 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ri 28446 GIR_EraseFromParent, /*InsnID*/0, 28447 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28448 // GIR_Coverage, 2598, 28449 GIR_Done, 28450 // Label 1744: @70703 28451 GIM_Try, /*On fail goto*//*Label 1745*/ 70765, // Rule ID 2599 // 28452 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_tbx1, 28453 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 28454 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 28455 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 28456 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, 28457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28458 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 28459 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 28460 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, 28461 // (intrinsic_wo_chain:{ *:[v16i8] } 324:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn) => (TBXv16i8One:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn) 28462 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBXv16i8One, 28463 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28464 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd 28465 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ri 28466 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rn 28467 GIR_EraseFromParent, /*InsnID*/0, 28468 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28469 // GIR_Coverage, 2599, 28470 GIR_Done, 28471 // Label 1745: @70765 28472 GIM_Reject, 28473 // Label 1716: @70766 28474 GIM_Try, /*On fail goto*//*Label 1746*/ 71112, 28475 GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, 28476 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcopy_lane, 28477 GIM_Try, /*On fail goto*//*Label 1747*/ 70859, // Rule ID 2676 // 28478 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 28479 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 28480 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 28481 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, 28482 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64, 28483 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28484 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 28485 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 28486 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 28487 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, 28488 // MIs[1] Operand 1 28489 // No operand predicates 28490 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, 28491 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] 28492 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 28493 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, 28494 // MIs[2] Operand 1 28495 // No operand predicates 28496 GIM_CheckIsSafeToFold, /*InsnID*/1, 28497 GIM_CheckIsSafeToFold, /*InsnID*/2, 28498 // (intrinsic_wo_chain:{ *:[v16i8] } 356:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, V128:{ *:[v16i8] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx2) => (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, V128:{ *:[v16i8] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx2) 28499 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi8lane, 28500 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28501 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd 28502 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx 28503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs 28504 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2 28505 GIR_EraseFromParent, /*InsnID*/0, 28506 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28507 // GIR_Coverage, 2676, 28508 GIR_Done, 28509 // Label 1747: @70859 28510 GIM_Try, /*On fail goto*//*Label 1748*/ 70943, // Rule ID 2677 // 28511 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 28512 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 28513 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 28514 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 28515 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64, 28516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 28518 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 28519 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 28520 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, 28521 // MIs[1] Operand 1 28522 // No operand predicates 28523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, 28524 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] 28525 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 28526 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, 28527 // MIs[2] Operand 1 28528 // No operand predicates 28529 GIM_CheckIsSafeToFold, /*InsnID*/1, 28530 GIM_CheckIsSafeToFold, /*InsnID*/2, 28531 // (intrinsic_wo_chain:{ *:[v8i16] } 356:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, V128:{ *:[v8i16] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx2) => (INSvi16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, V128:{ *:[v8i16] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx2) 28532 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi16lane, 28533 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28534 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd 28535 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx 28536 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs 28537 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2 28538 GIR_EraseFromParent, /*InsnID*/0, 28539 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28540 // GIR_Coverage, 2677, 28541 GIR_Done, 28542 // Label 1748: @70943 28543 GIM_Try, /*On fail goto*//*Label 1749*/ 71027, // Rule ID 2678 // 28544 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 28545 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 28546 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 28547 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 28548 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64, 28549 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28550 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 28551 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 28552 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 28553 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, 28554 // MIs[1] Operand 1 28555 // No operand predicates 28556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, 28557 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] 28558 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 28559 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, 28560 // MIs[2] Operand 1 28561 // No operand predicates 28562 GIM_CheckIsSafeToFold, /*InsnID*/1, 28563 GIM_CheckIsSafeToFold, /*InsnID*/2, 28564 // (intrinsic_wo_chain:{ *:[v4i32] } 356:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, V128:{ *:[v4i32] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx2) => (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, V128:{ *:[v4i32] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx2) 28565 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi32lane, 28566 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd 28568 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx 28569 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs 28570 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2 28571 GIR_EraseFromParent, /*InsnID*/0, 28572 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28573 // GIR_Coverage, 2678, 28574 GIR_Done, 28575 // Label 1749: @71027 28576 GIM_Try, /*On fail goto*//*Label 1750*/ 71111, // Rule ID 2679 // 28577 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 28578 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 28579 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 28580 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, 28581 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64, 28582 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 28584 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 28585 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 28586 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, 28587 // MIs[1] Operand 1 28588 // No operand predicates 28589 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, 28590 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] 28591 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 28592 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, 28593 // MIs[2] Operand 1 28594 // No operand predicates 28595 GIM_CheckIsSafeToFold, /*InsnID*/1, 28596 GIM_CheckIsSafeToFold, /*InsnID*/2, 28597 // (intrinsic_wo_chain:{ *:[v2i64] } 356:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, V128:{ *:[v2i64] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx2) => (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, V128:{ *:[v2i64] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx2) 28598 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, 28599 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28600 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd 28601 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx 28602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs 28603 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2 28604 GIR_EraseFromParent, /*InsnID*/0, 28605 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28606 // GIR_Coverage, 2679, 28607 GIR_Done, 28608 // Label 1750: @71111 28609 GIM_Reject, 28610 // Label 1746: @71112 28611 GIM_Reject, 28612 // Label 25: @71113 28613 GIM_Try, /*On fail goto*//*Label 1751*/ 71134, // Rule ID 3544 // 28614 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_clrex, 28615 // (intrinsic_void 181:{ *:[iPTR] }) => (CLREX 15:{ *:[i64] }) 28616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLREX, 28617 GIR_AddImm, /*InsnID*/0, /*Imm*/15, 28618 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 28619 GIR_EraseFromParent, /*InsnID*/0, 28620 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28621 // GIR_Coverage, 3544, 28622 GIR_Done, 28623 // Label 1751: @71134 28624 GIM_Try, /*On fail goto*//*Label 1752*/ 71292, 28625 GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, 28626 GIM_Try, /*On fail goto*//*Label 1753*/ 71177, // Rule ID 10 // 28627 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_hint, 28628 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 28629 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 28630 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 28631 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_127, 28632 // MIs[1] Operand 1 28633 // No operand predicates 28634 GIM_CheckIsSafeToFold, /*InsnID*/1, 28635 // (intrinsic_void 207:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_127>>:$imm) => (HINT (imm:{ *:[i32] }):$imm) 28636 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::HINT, 28637 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 28638 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 28639 GIR_EraseFromParent, /*InsnID*/0, 28640 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28641 // GIR_Coverage, 10, 28642 GIR_Done, 28643 // Label 1753: @71177 28644 GIM_Try, /*On fail goto*//*Label 1754*/ 71215, // Rule ID 11 // 28645 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_dmb, 28646 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 28647 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 28648 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 28649 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_15, 28650 // MIs[1] Operand 1 28651 // No operand predicates 28652 GIM_CheckIsSafeToFold, /*InsnID*/1, 28653 // (intrinsic_void 204:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm) => (DMB (imm:{ *:[i32] }):$CRm) 28654 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DMB, 28655 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm 28656 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 28657 GIR_EraseFromParent, /*InsnID*/0, 28658 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28659 // GIR_Coverage, 11, 28660 GIR_Done, 28661 // Label 1754: @71215 28662 GIM_Try, /*On fail goto*//*Label 1755*/ 71253, // Rule ID 12 // 28663 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_dsb, 28664 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 28665 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 28666 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 28667 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_15, 28668 // MIs[1] Operand 1 28669 // No operand predicates 28670 GIM_CheckIsSafeToFold, /*InsnID*/1, 28671 // (intrinsic_void 205:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm) => (DSB (imm:{ *:[i32] }):$CRm) 28672 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DSB, 28673 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm 28674 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 28675 GIR_EraseFromParent, /*InsnID*/0, 28676 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28677 // GIR_Coverage, 12, 28678 GIR_Done, 28679 // Label 1755: @71253 28680 GIM_Try, /*On fail goto*//*Label 1756*/ 71291, // Rule ID 13 // 28681 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_isb, 28682 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 28683 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 28684 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 28685 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_15, 28686 // MIs[1] Operand 1 28687 // No operand predicates 28688 GIM_CheckIsSafeToFold, /*InsnID*/1, 28689 // (intrinsic_void 208:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm) => (ISB (imm:{ *:[i32] }):$CRm) 28690 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ISB, 28691 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm 28692 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, 28693 GIR_EraseFromParent, /*InsnID*/0, 28694 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28695 // GIR_Coverage, 13, 28696 GIR_Done, 28697 // Label 1756: @71291 28698 GIM_Reject, 28699 // Label 1752: @71292 28700 GIM_Reject, 28701 // Label 26: @71293 28702 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 10, /*)*//*default:*//*Label 1760*/ 71406, 28703 /*GILLT_v2s64*//*Label 1757*/ 71304, 0, 28704 /*GILLT_v4s32*//*Label 1758*/ 71338, 0, 28705 /*GILLT_v8s16*//*Label 1759*/ 71372, 28706 // Label 1757: @71304 28707 GIM_Try, /*On fail goto*//*Label 1761*/ 71337, // Rule ID 2979 // 28708 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 28709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 28711 // (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn) => (USHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] }) 28712 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv2i32_shift, 28713 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 28714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 28715 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 28716 GIR_EraseFromParent, /*InsnID*/0, 28717 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28718 // GIR_Coverage, 2979, 28719 GIR_Done, 28720 // Label 1761: @71337 28721 GIM_Reject, 28722 // Label 1758: @71338 28723 GIM_Try, /*On fail goto*//*Label 1762*/ 71371, // Rule ID 2976 // 28724 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 28725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28726 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 28727 // (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn) => (USHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] }) 28728 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv4i16_shift, 28729 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 28730 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 28731 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 28732 GIR_EraseFromParent, /*InsnID*/0, 28733 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28734 // GIR_Coverage, 2976, 28735 GIR_Done, 28736 // Label 1762: @71371 28737 GIM_Reject, 28738 // Label 1759: @71372 28739 GIM_Try, /*On fail goto*//*Label 1763*/ 71405, // Rule ID 2973 // 28740 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 28741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28742 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 28743 // (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn) => (USHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] }) 28744 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv8i8_shift, 28745 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 28746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 28747 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 28748 GIR_EraseFromParent, /*InsnID*/0, 28749 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28750 // GIR_Coverage, 2973, 28751 GIR_Done, 28752 // Label 1763: @71405 28753 GIM_Reject, 28754 // Label 1760: @71406 28755 GIM_Reject, 28756 // Label 27: @71407 28757 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 1768*/ 71531, 28758 /*GILLT_s32*//*Label 1764*/ 71421, 0, 0, 28759 /*GILLT_v2s32*//*Label 1765*/ 71459, 0, 28760 /*GILLT_v4s16*//*Label 1766*/ 71483, 0, 28761 /*GILLT_v8s8*//*Label 1767*/ 71507, 28762 // Label 1764: @71421 28763 GIM_Try, /*On fail goto*//*Label 1769*/ 71458, // Rule ID 3110 // 28764 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 28765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, 28766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, 28767 // (trunc:{ *:[i32] } GPR64sp:{ *:[i64] }:$src) => (EXTRACT_SUBREG:{ *:[i32] } GPR64sp:{ *:[i64] }:$src, sub_32:{ *:[i32] }) 28768 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 28769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28770 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/15, // src 28771 GIR_EraseFromParent, /*InsnID*/0, 28772 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32sp*/7, 28773 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GPR64sp*/18, 28774 // GIR_Coverage, 3110, 28775 GIR_Done, 28776 // Label 1769: @71458 28777 GIM_Reject, 28778 // Label 1765: @71459 28779 GIM_Try, /*On fail goto*//*Label 1770*/ 71482, // Rule ID 760 // 28780 GIM_CheckFeatures, GIFBS_HasNEON, 28781 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 28782 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 28783 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 28784 // (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) => (XTNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) 28785 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::XTNv2i32, 28786 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28787 // GIR_Coverage, 760, 28788 GIR_Done, 28789 // Label 1770: @71482 28790 GIM_Reject, 28791 // Label 1766: @71483 28792 GIM_Try, /*On fail goto*//*Label 1771*/ 71506, // Rule ID 759 // 28793 GIM_CheckFeatures, GIFBS_HasNEON, 28794 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 28795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 28796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 28797 // (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) => (XTNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) 28798 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::XTNv4i16, 28799 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28800 // GIR_Coverage, 759, 28801 GIR_Done, 28802 // Label 1771: @71506 28803 GIM_Reject, 28804 // Label 1767: @71507 28805 GIM_Try, /*On fail goto*//*Label 1772*/ 71530, // Rule ID 758 // 28806 GIM_CheckFeatures, GIFBS_HasNEON, 28807 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 28808 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 28809 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 28810 // (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) => (XTNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) 28811 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::XTNv8i8, 28812 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28813 // GIR_Coverage, 758, 28814 GIR_Done, 28815 // Label 1772: @71530 28816 GIM_Reject, 28817 // Label 1768: @71531 28818 GIM_Reject, 28819 // Label 28: @71532 28820 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1775*/ 71584, 28821 /*GILLT_s32*//*Label 1773*/ 71540, 28822 /*GILLT_s64*//*Label 1774*/ 71562, 28823 // Label 1773: @71540 28824 GIM_Try, /*On fail goto*//*Label 1776*/ 71561, // Rule ID 23 // 28825 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 28826 // MIs[0] Operand 1 28827 // No operand predicates 28828 // (imm:{ *:[i32] }):$src => (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src) 28829 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MOVi32imm, 28830 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28831 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src 28832 GIR_EraseFromParent, /*InsnID*/0, 28833 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28834 // GIR_Coverage, 23, 28835 GIR_Done, 28836 // Label 1776: @71561 28837 GIM_Reject, 28838 // Label 1774: @71562 28839 GIM_Try, /*On fail goto*//*Label 1777*/ 71583, // Rule ID 24 // 28840 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 28841 // MIs[0] Operand 1 28842 // No operand predicates 28843 // (imm:{ *:[i64] }):$src => (MOVi64imm:{ *:[i64] } (imm:{ *:[i64] }):$src) 28844 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MOVi64imm, 28845 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 28846 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src 28847 GIR_EraseFromParent, /*InsnID*/0, 28848 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28849 // GIR_Coverage, 24, 28850 GIR_Done, 28851 // Label 1777: @71583 28852 GIM_Reject, 28853 // Label 1775: @71584 28854 GIM_Reject, 28855 // Label 29: @71585 28856 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 1781*/ 71662, 28857 /*GILLT_s16*//*Label 1778*/ 71594, 28858 /*GILLT_s32*//*Label 1779*/ 71618, 28859 /*GILLT_s64*//*Label 1780*/ 71640, 28860 // Label 1778: @71594 28861 GIM_Try, /*On fail goto*//*Label 1782*/ 71617, // Rule ID 368 // 28862 GIM_CheckFeatures, GIFBS_HasFullFP16, 28863 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm0, 28864 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 28865 // MIs[0] Operand 1 28866 // No operand predicates 28867 // (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>> => (FMOVH0:{ *:[f16] }) 28868 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMOVH0, 28869 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 28870 GIR_EraseFromParent, /*InsnID*/0, 28871 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28872 // GIR_Coverage, 368, 28873 GIR_Done, 28874 // Label 1782: @71617 28875 GIM_Reject, 28876 // Label 1779: @71618 28877 GIM_Try, /*On fail goto*//*Label 1783*/ 71639, // Rule ID 369 // 28878 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm0, 28879 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 28880 // MIs[0] Operand 1 28881 // No operand predicates 28882 // (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>> => (FMOVS0:{ *:[f32] }) 28883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMOVS0, 28884 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 28885 GIR_EraseFromParent, /*InsnID*/0, 28886 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28887 // GIR_Coverage, 369, 28888 GIR_Done, 28889 // Label 1783: @71639 28890 GIM_Reject, 28891 // Label 1780: @71640 28892 GIM_Try, /*On fail goto*//*Label 1784*/ 71661, // Rule ID 370 // 28893 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm0, 28894 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 28895 // MIs[0] Operand 1 28896 // No operand predicates 28897 // (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>> => (FMOVD0:{ *:[f64] }) 28898 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMOVD0, 28899 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 28900 GIR_EraseFromParent, /*InsnID*/0, 28901 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28902 // GIR_Coverage, 370, 28903 GIR_Done, 28904 // Label 1784: @71661 28905 GIM_Reject, 28906 // Label 1781: @71662 28907 GIM_Reject, 28908 // Label 30: @71663 28909 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 10, /*)*//*default:*//*Label 1788*/ 71776, 28910 /*GILLT_v2s64*//*Label 1785*/ 71674, 0, 28911 /*GILLT_v4s32*//*Label 1786*/ 71708, 0, 28912 /*GILLT_v8s16*//*Label 1787*/ 71742, 28913 // Label 1785: @71674 28914 GIM_Try, /*On fail goto*//*Label 1789*/ 71707, // Rule ID 2977 // 28915 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 28916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 28918 // (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn) => (SSHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] }) 28919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLLv2i32_shift, 28920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 28921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 28922 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 28923 GIR_EraseFromParent, /*InsnID*/0, 28924 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28925 // GIR_Coverage, 2977, 28926 GIR_Done, 28927 // Label 1789: @71707 28928 GIM_Reject, 28929 // Label 1786: @71708 28930 GIM_Try, /*On fail goto*//*Label 1790*/ 71741, // Rule ID 2974 // 28931 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 28932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 28934 // (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn) => (SSHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] }) 28935 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLLv4i16_shift, 28936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 28937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 28938 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 28939 GIR_EraseFromParent, /*InsnID*/0, 28940 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28941 // GIR_Coverage, 2974, 28942 GIR_Done, 28943 // Label 1790: @71741 28944 GIM_Reject, 28945 // Label 1787: @71742 28946 GIM_Try, /*On fail goto*//*Label 1791*/ 71775, // Rule ID 2971 // 28947 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 28948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 28950 // (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn) => (SSHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] }) 28951 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLLv8i8_shift, 28952 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 28953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 28954 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 28955 GIR_EraseFromParent, /*InsnID*/0, 28956 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28957 // GIR_Coverage, 2971, 28958 GIR_Done, 28959 // Label 1791: @71775 28960 GIM_Reject, 28961 // Label 1788: @71776 28962 GIM_Reject, 28963 // Label 31: @71777 28964 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 10, /*)*//*default:*//*Label 1795*/ 72235, 28965 /*GILLT_v2s64*//*Label 1792*/ 71788, 0, 28966 /*GILLT_v4s32*//*Label 1793*/ 71937, 0, 28967 /*GILLT_v8s16*//*Label 1794*/ 72086, 28968 // Label 1792: @71788 28969 GIM_Try, /*On fail goto*//*Label 1796*/ 71936, 28970 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 28971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 28972 GIM_Try, /*On fail goto*//*Label 1797*/ 71854, // Rule ID 466 // 28973 GIM_CheckFeatures, GIFBS_HasNEON, 28974 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 28975 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 28976 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 28977 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, 28978 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 28979 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, 28980 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 28981 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 28982 GIM_CheckIsSafeToFold, /*InsnID*/1, 28983 // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 328:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (UABDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 28984 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv2i32_v2i64, 28985 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 28986 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 28987 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 28988 GIR_EraseFromParent, /*InsnID*/0, 28989 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 28990 // GIR_Coverage, 466, 28991 GIR_Done, 28992 // Label 1797: @71854 28993 GIM_Try, /*On fail goto*//*Label 1798*/ 71910, // Rule ID 1274 // 28994 GIM_CheckFeatures, GIFBS_HasNEON, 28995 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 28996 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 28997 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 28998 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, 28999 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, 29000 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, 29001 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 29002 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 29003 GIM_CheckIsSafeToFold, /*InsnID*/1, 29004 // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 270:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SABDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) 29005 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDLv2i32_v2i64, 29006 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29007 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 29008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 29009 GIR_EraseFromParent, /*InsnID*/0, 29010 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29011 // GIR_Coverage, 1274, 29012 GIR_Done, 29013 // Label 1798: @71910 29014 GIM_Try, /*On fail goto*//*Label 1799*/ 71935, // Rule ID 2978 // 29015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 29016 // (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn) => (USHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] }) 29017 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv2i32_shift, 29018 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 29020 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 29021 GIR_EraseFromParent, /*InsnID*/0, 29022 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29023 // GIR_Coverage, 2978, 29024 GIR_Done, 29025 // Label 1799: @71935 29026 GIM_Reject, 29027 // Label 1796: @71936 29028 GIM_Reject, 29029 // Label 1793: @71937 29030 GIM_Try, /*On fail goto*//*Label 1800*/ 72085, 29031 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 29032 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 29033 GIM_Try, /*On fail goto*//*Label 1801*/ 72003, // Rule ID 464 // 29034 GIM_CheckFeatures, GIFBS_HasNEON, 29035 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 29036 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 29037 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 29038 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, 29039 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 29040 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, 29041 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 29042 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 29043 GIM_CheckIsSafeToFold, /*InsnID*/1, 29044 // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 328:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (UABDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 29045 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv4i16_v4i32, 29046 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 29048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 29049 GIR_EraseFromParent, /*InsnID*/0, 29050 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29051 // GIR_Coverage, 464, 29052 GIR_Done, 29053 // Label 1801: @72003 29054 GIM_Try, /*On fail goto*//*Label 1802*/ 72059, // Rule ID 1272 // 29055 GIM_CheckFeatures, GIFBS_HasNEON, 29056 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 29057 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 29058 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 29059 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, 29060 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, 29061 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, 29062 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 29063 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 29064 GIM_CheckIsSafeToFold, /*InsnID*/1, 29065 // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 270:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SABDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) 29066 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDLv4i16_v4i32, 29067 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 29069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 29070 GIR_EraseFromParent, /*InsnID*/0, 29071 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29072 // GIR_Coverage, 1272, 29073 GIR_Done, 29074 // Label 1802: @72059 29075 GIM_Try, /*On fail goto*//*Label 1803*/ 72084, // Rule ID 2975 // 29076 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 29077 // (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn) => (USHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] }) 29078 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv4i16_shift, 29079 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29080 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 29081 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 29082 GIR_EraseFromParent, /*InsnID*/0, 29083 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29084 // GIR_Coverage, 2975, 29085 GIR_Done, 29086 // Label 1803: @72084 29087 GIM_Reject, 29088 // Label 1800: @72085 29089 GIM_Reject, 29090 // Label 1794: @72086 29091 GIM_Try, /*On fail goto*//*Label 1804*/ 72234, 29092 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, 29093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 29094 GIM_Try, /*On fail goto*//*Label 1805*/ 72152, // Rule ID 462 // 29095 GIM_CheckFeatures, GIFBS_HasNEON, 29096 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 29097 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 29098 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 29099 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, 29100 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, 29101 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, 29102 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 29103 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 29104 GIM_CheckIsSafeToFold, /*InsnID*/1, 29105 // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 328:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (UABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 29106 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv8i8_v8i16, 29107 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29108 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 29109 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 29110 GIR_EraseFromParent, /*InsnID*/0, 29111 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29112 // GIR_Coverage, 462, 29113 GIR_Done, 29114 // Label 1805: @72152 29115 GIM_Try, /*On fail goto*//*Label 1806*/ 72208, // Rule ID 1270 // 29116 GIM_CheckFeatures, GIFBS_HasNEON, 29117 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 29118 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, 29119 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, 29120 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, 29121 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, 29122 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, 29123 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 29124 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 29125 GIM_CheckIsSafeToFold, /*InsnID*/1, 29126 // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 270:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (SABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) 29127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDLv8i8_v8i16, 29128 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29129 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn 29130 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm 29131 GIR_EraseFromParent, /*InsnID*/0, 29132 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29133 // GIR_Coverage, 1270, 29134 GIR_Done, 29135 // Label 1806: @72208 29136 GIM_Try, /*On fail goto*//*Label 1807*/ 72233, // Rule ID 2972 // 29137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 29138 // (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn) => (USHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] }) 29139 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv8i8_shift, 29140 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29141 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 29142 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 29143 GIR_EraseFromParent, /*InsnID*/0, 29144 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29145 // GIR_Coverage, 2972, 29146 GIR_Done, 29147 // Label 1807: @72233 29148 GIM_Reject, 29149 // Label 1804: @72234 29150 GIM_Reject, 29151 // Label 1795: @72235 29152 GIM_Reject, 29153 // Label 32: @72236 29154 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1810*/ 72411, 29155 /*GILLT_s32*//*Label 1808*/ 72244, 29156 /*GILLT_s64*//*Label 1809*/ 72381, 29157 // Label 1808: @72244 29158 GIM_Try, /*On fail goto*//*Label 1811*/ 72380, 29159 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 29160 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 29161 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 29162 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 29163 GIM_Try, /*On fail goto*//*Label 1812*/ 72301, // Rule ID 1860 // 29164 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 29165 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, 29166 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 29167 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 29168 GIM_CheckIsSafeToFold, /*InsnID*/1, 29169 // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 29170 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVWr, 29171 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29172 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 29173 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 29174 GIR_EraseFromParent, /*InsnID*/0, 29175 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29176 // GIR_Coverage, 1860, 29177 GIR_Done, 29178 // Label 1812: @72301 29179 GIM_Try, /*On fail goto*//*Label 1813*/ 72340, // Rule ID 1861 // 29180 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 29181 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 29182 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 29183 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 29184 GIM_CheckIsSafeToFold, /*InsnID*/1, 29185 // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 29186 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVWr, 29187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 29189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 29190 GIR_EraseFromParent, /*InsnID*/0, 29191 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29192 // GIR_Coverage, 1861, 29193 GIR_Done, 29194 // Label 1813: @72340 29195 GIM_Try, /*On fail goto*//*Label 1814*/ 72379, // Rule ID 1859 // 29196 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 29197 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 29198 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 29199 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 29200 GIM_CheckIsSafeToFold, /*InsnID*/1, 29201 // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 29202 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVWr, 29203 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 29205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 29206 GIR_EraseFromParent, /*InsnID*/0, 29207 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29208 // GIR_Coverage, 1859, 29209 GIR_Done, 29210 // Label 1814: @72379 29211 GIM_Reject, 29212 // Label 1811: @72380 29213 GIM_Reject, 29214 // Label 1809: @72381 29215 GIM_Try, /*On fail goto*//*Label 1815*/ 72410, // Rule ID 62 // 29216 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 29217 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 29218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 29219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 29220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 29221 // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (LSLVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) 29222 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LSLVXr, 29223 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29224 // GIR_Coverage, 62, 29225 GIR_Done, 29226 // Label 1815: @72410 29227 GIM_Reject, 29228 // Label 1810: @72411 29229 GIM_Reject, 29230 // Label 33: @72412 29231 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1818*/ 72662, 29232 /*GILLT_s32*//*Label 1816*/ 72420, 29233 /*GILLT_s64*//*Label 1817*/ 72593, 29234 // Label 1816: @72420 29235 GIM_Try, /*On fail goto*//*Label 1819*/ 72592, 29236 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 29237 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 29238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 29239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 29240 GIM_Try, /*On fail goto*//*Label 1820*/ 72474, // Rule ID 1906 // 29241 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 29242 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 29243 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31, 29244 // MIs[1] Operand 1 29245 // No operand predicates 29246 GIM_CheckIsSafeToFold, /*InsnID*/1, 29247 // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm) => (UBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, 31:{ *:[i64] }) 29248 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UBFMWri, 29249 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 29251 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 29252 GIR_AddImm, /*InsnID*/0, /*Imm*/31, 29253 GIR_EraseFromParent, /*InsnID*/0, 29254 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29255 // GIR_Coverage, 1906, 29256 GIR_Done, 29257 // Label 1820: @72474 29258 GIM_Try, /*On fail goto*//*Label 1821*/ 72513, // Rule ID 1864 // 29259 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 29260 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, 29261 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 29262 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 29263 GIM_CheckIsSafeToFold, /*InsnID*/1, 29264 // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 29265 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVWr, 29266 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29267 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 29268 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 29269 GIR_EraseFromParent, /*InsnID*/0, 29270 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29271 // GIR_Coverage, 1864, 29272 GIR_Done, 29273 // Label 1821: @72513 29274 GIM_Try, /*On fail goto*//*Label 1822*/ 72552, // Rule ID 1865 // 29275 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 29276 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 29277 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 29278 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 29279 GIM_CheckIsSafeToFold, /*InsnID*/1, 29280 // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 29281 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVWr, 29282 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29283 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 29284 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 29285 GIR_EraseFromParent, /*InsnID*/0, 29286 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29287 // GIR_Coverage, 1865, 29288 GIR_Done, 29289 // Label 1822: @72552 29290 GIM_Try, /*On fail goto*//*Label 1823*/ 72591, // Rule ID 1863 // 29291 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 29292 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 29293 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 29294 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 29295 GIM_CheckIsSafeToFold, /*InsnID*/1, 29296 // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 29297 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVWr, 29298 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29299 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 29300 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 29301 GIR_EraseFromParent, /*InsnID*/0, 29302 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29303 // GIR_Coverage, 1863, 29304 GIR_Done, 29305 // Label 1823: @72591 29306 GIM_Reject, 29307 // Label 1819: @72592 29308 GIM_Reject, 29309 // Label 1817: @72593 29310 GIM_Try, /*On fail goto*//*Label 1824*/ 72661, 29311 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 29312 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 29313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 29314 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 29315 GIM_Try, /*On fail goto*//*Label 1825*/ 72647, // Rule ID 1907 // 29316 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 29317 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 29318 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_63, 29319 // MIs[1] Operand 1 29320 // No operand predicates 29321 GIM_CheckIsSafeToFold, /*InsnID*/1, 29322 // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm) => (UBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm, 63:{ *:[i64] }) 29323 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UBFMXri, 29324 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 29326 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 29327 GIR_AddImm, /*InsnID*/0, /*Imm*/63, 29328 GIR_EraseFromParent, /*InsnID*/0, 29329 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29330 // GIR_Coverage, 1907, 29331 GIR_Done, 29332 // Label 1825: @72647 29333 GIM_Try, /*On fail goto*//*Label 1826*/ 72660, // Rule ID 63 // 29334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 29335 // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (LSRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) 29336 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LSRVXr, 29337 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29338 // GIR_Coverage, 63, 29339 GIR_Done, 29340 // Label 1826: @72660 29341 GIM_Reject, 29342 // Label 1824: @72661 29343 GIM_Reject, 29344 // Label 1818: @72662 29345 GIM_Reject, 29346 // Label 34: @72663 29347 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1829*/ 72913, 29348 /*GILLT_s32*//*Label 1827*/ 72671, 29349 /*GILLT_s64*//*Label 1828*/ 72844, 29350 // Label 1827: @72671 29351 GIM_Try, /*On fail goto*//*Label 1830*/ 72843, 29352 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 29353 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 29354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 29355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 29356 GIM_Try, /*On fail goto*//*Label 1831*/ 72725, // Rule ID 1904 // 29357 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 29358 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 29359 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31, 29360 // MIs[1] Operand 1 29361 // No operand predicates 29362 GIM_CheckIsSafeToFold, /*InsnID*/1, 29363 // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm) => (SBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, 31:{ *:[i64] }) 29364 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMWri, 29365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 29367 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 29368 GIR_AddImm, /*InsnID*/0, /*Imm*/31, 29369 GIR_EraseFromParent, /*InsnID*/0, 29370 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29371 // GIR_Coverage, 1904, 29372 GIR_Done, 29373 // Label 1831: @72725 29374 GIM_Try, /*On fail goto*//*Label 1832*/ 72764, // Rule ID 1760 // 29375 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 29376 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, 29377 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 29378 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 29379 GIM_CheckIsSafeToFold, /*InsnID*/1, 29380 // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 29381 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVWr, 29382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 29384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 29385 GIR_EraseFromParent, /*InsnID*/0, 29386 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29387 // GIR_Coverage, 1760, 29388 GIR_Done, 29389 // Label 1832: @72764 29390 GIM_Try, /*On fail goto*//*Label 1833*/ 72803, // Rule ID 1761 // 29391 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 29392 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, 29393 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 29394 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 29395 GIM_CheckIsSafeToFold, /*InsnID*/1, 29396 // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 29397 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVWr, 29398 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29399 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 29400 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 29401 GIR_EraseFromParent, /*InsnID*/0, 29402 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29403 // GIR_Coverage, 1761, 29404 GIR_Done, 29405 // Label 1833: @72803 29406 GIM_Try, /*On fail goto*//*Label 1834*/ 72842, // Rule ID 1759 // 29407 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 29408 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, 29409 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 29410 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 29411 GIM_CheckIsSafeToFold, /*InsnID*/1, 29412 // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) 29413 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVWr, 29414 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29415 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 29416 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 29417 GIR_EraseFromParent, /*InsnID*/0, 29418 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29419 // GIR_Coverage, 1759, 29420 GIR_Done, 29421 // Label 1834: @72842 29422 GIM_Reject, 29423 // Label 1830: @72843 29424 GIM_Reject, 29425 // Label 1828: @72844 29426 GIM_Try, /*On fail goto*//*Label 1835*/ 72912, 29427 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 29428 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 29429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 29430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 29431 GIM_Try, /*On fail goto*//*Label 1836*/ 72898, // Rule ID 1905 // 29432 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 29433 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 29434 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_63, 29435 // MIs[1] Operand 1 29436 // No operand predicates 29437 GIM_CheckIsSafeToFold, /*InsnID*/1, 29438 // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm) => (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm, 63:{ *:[i64] }) 29439 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMXri, 29440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29441 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 29442 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm 29443 GIR_AddImm, /*InsnID*/0, /*Imm*/63, 29444 GIR_EraseFromParent, /*InsnID*/0, 29445 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29446 // GIR_Coverage, 1905, 29447 GIR_Done, 29448 // Label 1836: @72898 29449 GIM_Try, /*On fail goto*//*Label 1837*/ 72911, // Rule ID 61 // 29450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, 29451 // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ASRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) 29452 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ASRVXr, 29453 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29454 // GIR_Coverage, 61, 29455 GIR_Done, 29456 // Label 1837: @72911 29457 GIM_Reject, 29458 // Label 1835: @72912 29459 GIM_Reject, 29460 // Label 1829: @72913 29461 GIM_Reject, 29462 // Label 35: @72914 29463 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 1846*/ 73186, 29464 /*GILLT_s16*//*Label 1838*/ 72930, 29465 /*GILLT_s32*//*Label 1839*/ 72962, 29466 /*GILLT_s64*//*Label 1840*/ 72994, 0, 29467 /*GILLT_v2s32*//*Label 1841*/ 73026, 29468 /*GILLT_v2s64*//*Label 1842*/ 73058, 29469 /*GILLT_v4s16*//*Label 1843*/ 73090, 29470 /*GILLT_v4s32*//*Label 1844*/ 73122, 0, 29471 /*GILLT_v8s16*//*Label 1845*/ 73154, 29472 // Label 1838: @72930 29473 GIM_Try, /*On fail goto*//*Label 1847*/ 72961, // Rule ID 407 // 29474 GIM_CheckFeatures, GIFBS_HasFullFP16, 29475 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 29476 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 29477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 29478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, 29479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 29480 // (fadd:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FADDHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) 29481 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDHrr, 29482 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29483 // GIR_Coverage, 407, 29484 GIR_Done, 29485 // Label 1847: @72961 29486 GIM_Reject, 29487 // Label 1839: @72962 29488 GIM_Try, /*On fail goto*//*Label 1848*/ 72993, // Rule ID 408 // 29489 GIM_CheckFeatures, GIFBS_HasFPARMv8, 29490 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 29491 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 29492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 29493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 29494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 29495 // (fadd:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FADDSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) 29496 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDSrr, 29497 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29498 // GIR_Coverage, 408, 29499 GIR_Done, 29500 // Label 1848: @72993 29501 GIM_Reject, 29502 // Label 1840: @72994 29503 GIM_Try, /*On fail goto*//*Label 1849*/ 73025, // Rule ID 409 // 29504 GIM_CheckFeatures, GIFBS_HasFPARMv8, 29505 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 29506 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 29507 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 29508 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 29509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 29510 // (fadd:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FADDDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) 29511 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDDrr, 29512 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29513 // GIR_Coverage, 409, 29514 GIR_Done, 29515 // Label 1849: @73025 29516 GIM_Reject, 29517 // Label 1841: @73026 29518 GIM_Try, /*On fail goto*//*Label 1850*/ 73057, // Rule ID 839 // 29519 GIM_CheckFeatures, GIFBS_HasNEON, 29520 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 29521 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 29522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 29523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 29524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 29525 // (fadd:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) 29526 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv2f32, 29527 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29528 // GIR_Coverage, 839, 29529 GIR_Done, 29530 // Label 1850: @73057 29531 GIM_Reject, 29532 // Label 1842: @73058 29533 GIM_Try, /*On fail goto*//*Label 1851*/ 73089, // Rule ID 841 // 29534 GIM_CheckFeatures, GIFBS_HasNEON, 29535 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 29536 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 29537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 29538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 29539 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 29540 // (fadd:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) 29541 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv2f64, 29542 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29543 // GIR_Coverage, 841, 29544 GIR_Done, 29545 // Label 1851: @73089 29546 GIM_Reject, 29547 // Label 1843: @73090 29548 GIM_Try, /*On fail goto*//*Label 1852*/ 73121, // Rule ID 837 // 29549 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 29550 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 29551 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 29552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 29553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 29554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 29555 // (fadd:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) 29556 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv4f16, 29557 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29558 // GIR_Coverage, 837, 29559 GIR_Done, 29560 // Label 1852: @73121 29561 GIM_Reject, 29562 // Label 1844: @73122 29563 GIM_Try, /*On fail goto*//*Label 1853*/ 73153, // Rule ID 840 // 29564 GIM_CheckFeatures, GIFBS_HasNEON, 29565 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 29566 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 29567 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 29568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 29569 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 29570 // (fadd:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) 29571 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv4f32, 29572 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29573 // GIR_Coverage, 840, 29574 GIR_Done, 29575 // Label 1853: @73153 29576 GIM_Reject, 29577 // Label 1845: @73154 29578 GIM_Try, /*On fail goto*//*Label 1854*/ 73185, // Rule ID 838 // 29579 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 29580 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 29581 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 29582 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 29583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 29584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 29585 // (fadd:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) 29586 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv8f16, 29587 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29588 // GIR_Coverage, 838, 29589 GIR_Done, 29590 // Label 1854: @73185 29591 GIM_Reject, 29592 // Label 1846: @73186 29593 GIM_Reject, 29594 // Label 36: @73187 29595 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 1863*/ 73459, 29596 /*GILLT_s16*//*Label 1855*/ 73203, 29597 /*GILLT_s32*//*Label 1856*/ 73235, 29598 /*GILLT_s64*//*Label 1857*/ 73267, 0, 29599 /*GILLT_v2s32*//*Label 1858*/ 73299, 29600 /*GILLT_v2s64*//*Label 1859*/ 73331, 29601 /*GILLT_v4s16*//*Label 1860*/ 73363, 29602 /*GILLT_v4s32*//*Label 1861*/ 73395, 0, 29603 /*GILLT_v8s16*//*Label 1862*/ 73427, 29604 // Label 1855: @73203 29605 GIM_Try, /*On fail goto*//*Label 1864*/ 73234, // Rule ID 431 // 29606 GIM_CheckFeatures, GIFBS_HasFullFP16, 29607 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 29608 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 29609 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 29610 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, 29611 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 29612 // (fsub:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FSUBHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) 29613 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBHrr, 29614 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29615 // GIR_Coverage, 431, 29616 GIR_Done, 29617 // Label 1864: @73234 29618 GIM_Reject, 29619 // Label 1856: @73235 29620 GIM_Try, /*On fail goto*//*Label 1865*/ 73266, // Rule ID 432 // 29621 GIM_CheckFeatures, GIFBS_HasFPARMv8, 29622 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 29623 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 29624 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 29625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 29626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 29627 // (fsub:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FSUBSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) 29628 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBSrr, 29629 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29630 // GIR_Coverage, 432, 29631 GIR_Done, 29632 // Label 1865: @73266 29633 GIM_Reject, 29634 // Label 1857: @73267 29635 GIM_Try, /*On fail goto*//*Label 1866*/ 73298, // Rule ID 433 // 29636 GIM_CheckFeatures, GIFBS_HasFPARMv8, 29637 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 29638 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 29639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 29640 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 29641 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 29642 // (fsub:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FSUBDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) 29643 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBDrr, 29644 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29645 // GIR_Coverage, 433, 29646 GIR_Done, 29647 // Label 1866: @73298 29648 GIM_Reject, 29649 // Label 1858: @73299 29650 GIM_Try, /*On fail goto*//*Label 1867*/ 73330, // Rule ID 934 // 29651 GIM_CheckFeatures, GIFBS_HasNEON, 29652 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 29653 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 29654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 29655 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 29656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 29657 // (fsub:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FSUBv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) 29658 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv2f32, 29659 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29660 // GIR_Coverage, 934, 29661 GIR_Done, 29662 // Label 1867: @73330 29663 GIM_Reject, 29664 // Label 1859: @73331 29665 GIM_Try, /*On fail goto*//*Label 1868*/ 73362, // Rule ID 936 // 29666 GIM_CheckFeatures, GIFBS_HasNEON, 29667 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 29668 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 29669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 29670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 29671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 29672 // (fsub:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FSUBv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) 29673 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv2f64, 29674 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29675 // GIR_Coverage, 936, 29676 GIR_Done, 29677 // Label 1868: @73362 29678 GIM_Reject, 29679 // Label 1860: @73363 29680 GIM_Try, /*On fail goto*//*Label 1869*/ 73394, // Rule ID 932 // 29681 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 29682 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 29683 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 29684 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 29685 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 29686 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 29687 // (fsub:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FSUBv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) 29688 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv4f16, 29689 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29690 // GIR_Coverage, 932, 29691 GIR_Done, 29692 // Label 1869: @73394 29693 GIM_Reject, 29694 // Label 1861: @73395 29695 GIM_Try, /*On fail goto*//*Label 1870*/ 73426, // Rule ID 935 // 29696 GIM_CheckFeatures, GIFBS_HasNEON, 29697 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 29698 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 29699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 29700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 29701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 29702 // (fsub:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FSUBv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) 29703 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv4f32, 29704 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29705 // GIR_Coverage, 935, 29706 GIR_Done, 29707 // Label 1870: @73426 29708 GIM_Reject, 29709 // Label 1862: @73427 29710 GIM_Try, /*On fail goto*//*Label 1871*/ 73458, // Rule ID 933 // 29711 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 29712 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 29713 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 29714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 29715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 29716 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 29717 // (fsub:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FSUBv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) 29718 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv8f16, 29719 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29720 // GIR_Coverage, 933, 29721 GIR_Done, 29722 // Label 1871: @73458 29723 GIM_Reject, 29724 // Label 1863: @73459 29725 GIM_Reject, 29726 // Label 37: @73460 29727 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 1880*/ 73732, 29728 /*GILLT_s16*//*Label 1872*/ 73476, 29729 /*GILLT_s32*//*Label 1873*/ 73508, 29730 /*GILLT_s64*//*Label 1874*/ 73540, 0, 29731 /*GILLT_v2s32*//*Label 1875*/ 73572, 29732 /*GILLT_v2s64*//*Label 1876*/ 73604, 29733 /*GILLT_v4s16*//*Label 1877*/ 73636, 29734 /*GILLT_v4s32*//*Label 1878*/ 73668, 0, 29735 /*GILLT_v8s16*//*Label 1879*/ 73700, 29736 // Label 1872: @73476 29737 GIM_Try, /*On fail goto*//*Label 1881*/ 73507, // Rule ID 425 // 29738 GIM_CheckFeatures, GIFBS_HasFullFP16, 29739 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 29740 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 29741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 29742 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, 29743 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 29744 // (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) 29745 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULHrr, 29746 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29747 // GIR_Coverage, 425, 29748 GIR_Done, 29749 // Label 1881: @73507 29750 GIM_Reject, 29751 // Label 1873: @73508 29752 GIM_Try, /*On fail goto*//*Label 1882*/ 73539, // Rule ID 426 // 29753 GIM_CheckFeatures, GIFBS_HasFPARMv8, 29754 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 29755 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 29756 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 29757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 29758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 29759 // (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) 29760 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULSrr, 29761 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29762 // GIR_Coverage, 426, 29763 GIR_Done, 29764 // Label 1882: @73539 29765 GIM_Reject, 29766 // Label 1874: @73540 29767 GIM_Try, /*On fail goto*//*Label 1883*/ 73571, // Rule ID 427 // 29768 GIM_CheckFeatures, GIFBS_HasFPARMv8, 29769 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 29770 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 29771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 29772 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 29773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 29774 // (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) 29775 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULDrr, 29776 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29777 // GIR_Coverage, 427, 29778 GIR_Done, 29779 // Label 1883: @73571 29780 GIM_Reject, 29781 // Label 1875: @73572 29782 GIM_Try, /*On fail goto*//*Label 1884*/ 73603, // Rule ID 919 // 29783 GIM_CheckFeatures, GIFBS_HasNEON, 29784 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 29785 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 29786 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 29787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 29788 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 29789 // (fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMULv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) 29790 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv2f32, 29791 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29792 // GIR_Coverage, 919, 29793 GIR_Done, 29794 // Label 1884: @73603 29795 GIM_Reject, 29796 // Label 1876: @73604 29797 GIM_Try, /*On fail goto*//*Label 1885*/ 73635, // Rule ID 921 // 29798 GIM_CheckFeatures, GIFBS_HasNEON, 29799 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 29800 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 29801 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 29802 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 29803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 29804 // (fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMULv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) 29805 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv2f64, 29806 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29807 // GIR_Coverage, 921, 29808 GIR_Done, 29809 // Label 1885: @73635 29810 GIM_Reject, 29811 // Label 1877: @73636 29812 GIM_Try, /*On fail goto*//*Label 1886*/ 73667, // Rule ID 917 // 29813 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 29814 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 29815 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 29816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 29817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 29818 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 29819 // (fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMULv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) 29820 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv4f16, 29821 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29822 // GIR_Coverage, 917, 29823 GIR_Done, 29824 // Label 1886: @73667 29825 GIM_Reject, 29826 // Label 1878: @73668 29827 GIM_Try, /*On fail goto*//*Label 1887*/ 73699, // Rule ID 920 // 29828 GIM_CheckFeatures, GIFBS_HasNEON, 29829 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 29830 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 29831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 29832 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 29833 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 29834 // (fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMULv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) 29835 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv4f32, 29836 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29837 // GIR_Coverage, 920, 29838 GIR_Done, 29839 // Label 1887: @73699 29840 GIM_Reject, 29841 // Label 1879: @73700 29842 GIM_Try, /*On fail goto*//*Label 1888*/ 73731, // Rule ID 918 // 29843 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 29844 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 29845 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 29846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 29847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 29848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 29849 // (fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMULv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) 29850 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv8f16, 29851 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29852 // GIR_Coverage, 918, 29853 GIR_Done, 29854 // Label 1888: @73731 29855 GIM_Reject, 29856 // Label 1880: @73732 29857 GIM_Reject, 29858 // Label 38: @73733 29859 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 1897*/ 75256, 29860 /*GILLT_s16*//*Label 1889*/ 73749, 29861 /*GILLT_s32*//*Label 1890*/ 73890, 29862 /*GILLT_s64*//*Label 1891*/ 74218, 0, 29863 /*GILLT_v2s32*//*Label 1892*/ 74546, 29864 /*GILLT_v2s64*//*Label 1893*/ 74710, 29865 /*GILLT_v4s16*//*Label 1894*/ 74874, 29866 /*GILLT_v4s32*//*Label 1895*/ 74983, 0, 29867 /*GILLT_v8s16*//*Label 1896*/ 75147, 29868 // Label 1889: @73749 29869 GIM_Try, /*On fail goto*//*Label 1898*/ 73889, 29870 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 29871 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 29872 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, 29873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 29874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, 29875 GIM_Try, /*On fail goto*//*Label 1899*/ 73820, // Rule ID 437 // 29876 GIM_CheckFeatures, GIFBS_HasFullFP16, 29877 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 29878 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 29879 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, 29880 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, 29881 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, 29882 GIM_CheckIsSafeToFold, /*InsnID*/1, 29883 // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) 29884 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBHrrr, 29885 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29886 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 29887 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 29888 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra 29889 GIR_EraseFromParent, /*InsnID*/0, 29890 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29891 // GIR_Coverage, 437, 29892 GIR_Done, 29893 // Label 1899: @73820 29894 GIM_Try, /*On fail goto*//*Label 1900*/ 73869, // Rule ID 443 // 29895 GIM_CheckFeatures, GIFBS_HasFullFP16, 29896 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 29897 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 29898 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 29899 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, 29900 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, 29901 GIM_CheckIsSafeToFold, /*InsnID*/1, 29902 // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra)) => (FNMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) 29903 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMSUBHrrr, 29904 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29905 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 29906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 29907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra 29908 GIR_EraseFromParent, /*InsnID*/0, 29909 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29910 // GIR_Coverage, 443, 29911 GIR_Done, 29912 // Label 1900: @73869 29913 GIM_Try, /*On fail goto*//*Label 1901*/ 73888, // Rule ID 434 // 29914 GIM_CheckFeatures, GIFBS_HasFullFP16, 29915 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 29916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, 29917 // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) => (FMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) 29918 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMADDHrrr, 29919 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29920 // GIR_Coverage, 434, 29921 GIR_Done, 29922 // Label 1901: @73888 29923 GIM_Reject, 29924 // Label 1898: @73889 29925 GIM_Reject, 29926 // Label 1890: @73890 29927 GIM_Try, /*On fail goto*//*Label 1902*/ 74217, 29928 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 29929 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 29930 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 29931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 29932 GIM_Try, /*On fail goto*//*Label 1903*/ 73972, // Rule ID 2273 // 29933 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 29934 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 29935 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 29936 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 29937 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 29938 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] 29939 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 29940 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 29941 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 29942 GIM_CheckIsSafeToFold, /*InsnID*/1, 29943 GIM_CheckIsSafeToFold, /*InsnID*/2, 29944 // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) 29945 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDSrrr, 29946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29947 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 29948 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 29949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra 29950 GIR_EraseFromParent, /*InsnID*/0, 29951 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29952 // GIR_Coverage, 2273, 29953 GIR_Done, 29954 // Label 1903: @73972 29955 GIM_Try, /*On fail goto*//*Label 1904*/ 74036, // Rule ID 2275 // 29956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 29957 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 29958 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 29959 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 29960 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 29961 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] 29962 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 29963 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 29964 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 29965 GIM_CheckIsSafeToFold, /*InsnID*/1, 29966 GIM_CheckIsSafeToFold, /*InsnID*/2, 29967 // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) 29968 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDSrrr, 29969 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 29971 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 29972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra 29973 GIR_EraseFromParent, /*InsnID*/0, 29974 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29975 // GIR_Coverage, 2275, 29976 GIR_Done, 29977 // Label 1904: @74036 29978 GIM_Try, /*On fail goto*//*Label 1905*/ 74087, // Rule ID 2271 // 29979 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 29980 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 29981 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 29982 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 29983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 29984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 29985 GIM_CheckIsSafeToFold, /*InsnID*/1, 29986 // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) 29987 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBSrrr, 29988 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 29989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 29990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 29991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra 29992 GIR_EraseFromParent, /*InsnID*/0, 29993 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 29994 // GIR_Coverage, 2271, 29995 GIR_Done, 29996 // Label 1905: @74087 29997 GIM_Try, /*On fail goto*//*Label 1906*/ 74140, // Rule ID 438 // 29998 GIM_CheckFeatures, GIFBS_HasFPARMv8, 29999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 30000 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 30001 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 30002 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 30003 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 30004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 30005 GIM_CheckIsSafeToFold, /*InsnID*/1, 30006 // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) 30007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBSrrr, 30008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 30009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 30010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 30011 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra 30012 GIR_EraseFromParent, /*InsnID*/0, 30013 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30014 // GIR_Coverage, 438, 30015 GIR_Done, 30016 // Label 1906: @74140 30017 GIM_Try, /*On fail goto*//*Label 1907*/ 74193, // Rule ID 444 // 30018 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 30020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 30021 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 30022 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 30023 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 30024 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 30025 GIM_CheckIsSafeToFold, /*InsnID*/1, 30026 // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) 30027 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMSUBSrrr, 30028 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 30029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 30030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 30031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra 30032 GIR_EraseFromParent, /*InsnID*/0, 30033 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30034 // GIR_Coverage, 444, 30035 GIR_Done, 30036 // Label 1907: @74193 30037 GIM_Try, /*On fail goto*//*Label 1908*/ 74216, // Rule ID 435 // 30038 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 30040 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 30041 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 30042 // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) => (FMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) 30043 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMADDSrrr, 30044 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30045 // GIR_Coverage, 435, 30046 GIR_Done, 30047 // Label 1908: @74216 30048 GIM_Reject, 30049 // Label 1902: @74217 30050 GIM_Reject, 30051 // Label 1891: @74218 30052 GIM_Try, /*On fail goto*//*Label 1909*/ 74545, 30053 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 30054 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 30055 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 30056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 30057 GIM_Try, /*On fail goto*//*Label 1910*/ 74300, // Rule ID 2274 // 30058 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 30059 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 30060 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 30061 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 30063 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] 30064 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 30065 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 30066 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30067 GIM_CheckIsSafeToFold, /*InsnID*/1, 30068 GIM_CheckIsSafeToFold, /*InsnID*/2, 30069 // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) 30070 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDDrrr, 30071 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 30072 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 30073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 30074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra 30075 GIR_EraseFromParent, /*InsnID*/0, 30076 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30077 // GIR_Coverage, 2274, 30078 GIR_Done, 30079 // Label 1910: @74300 30080 GIM_Try, /*On fail goto*//*Label 1911*/ 74364, // Rule ID 2276 // 30081 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30082 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 30083 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 30084 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 30085 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30086 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] 30087 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 30088 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 30089 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30090 GIM_CheckIsSafeToFold, /*InsnID*/1, 30091 GIM_CheckIsSafeToFold, /*InsnID*/2, 30092 // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) 30093 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDDrrr, 30094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 30095 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 30096 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 30097 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra 30098 GIR_EraseFromParent, /*InsnID*/0, 30099 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30100 // GIR_Coverage, 2276, 30101 GIR_Done, 30102 // Label 1911: @74364 30103 GIM_Try, /*On fail goto*//*Label 1912*/ 74415, // Rule ID 2272 // 30104 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 30105 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 30106 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 30107 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 30109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 30110 GIM_CheckIsSafeToFold, /*InsnID*/1, 30111 // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) 30112 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBDrrr, 30113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 30114 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 30115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 30116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra 30117 GIR_EraseFromParent, /*InsnID*/0, 30118 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30119 // GIR_Coverage, 2272, 30120 GIR_Done, 30121 // Label 1912: @74415 30122 GIM_Try, /*On fail goto*//*Label 1913*/ 74468, // Rule ID 439 // 30123 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30125 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 30126 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 30127 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 30128 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 30130 GIM_CheckIsSafeToFold, /*InsnID*/1, 30131 // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) 30132 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBDrrr, 30133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 30134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 30135 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 30136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra 30137 GIR_EraseFromParent, /*InsnID*/0, 30138 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30139 // GIR_Coverage, 439, 30140 GIR_Done, 30141 // Label 1913: @74468 30142 GIM_Try, /*On fail goto*//*Label 1914*/ 74521, // Rule ID 445 // 30143 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 30146 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 30147 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 30148 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 30149 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30150 GIM_CheckIsSafeToFold, /*InsnID*/1, 30151 // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) 30152 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMSUBDrrr, 30153 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 30154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 30155 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 30156 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra 30157 GIR_EraseFromParent, /*InsnID*/0, 30158 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30159 // GIR_Coverage, 445, 30160 GIR_Done, 30161 // Label 1914: @74521 30162 GIM_Try, /*On fail goto*//*Label 1915*/ 74544, // Rule ID 436 // 30163 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30164 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 30166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 30167 // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) => (FMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) 30168 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMADDDrrr, 30169 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30170 // GIR_Coverage, 436, 30171 GIR_Done, 30172 // Label 1915: @74544 30173 GIM_Reject, 30174 // Label 1909: @74545 30175 GIM_Reject, 30176 // Label 1892: @74546 30177 GIM_Try, /*On fail goto*//*Label 1916*/ 74709, 30178 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 30179 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 30180 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, 30181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 30182 GIM_Try, /*On fail goto*//*Label 1917*/ 74615, // Rule ID 2364 // 30183 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 30184 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 30185 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, 30186 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 30188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 30189 GIM_CheckIsSafeToFold, /*InsnID*/1, 30190 // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rm, V64:{ *:[v2f32] }:$Rd) => (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) 30191 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f32, 30192 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 30193 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd 30194 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 30195 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 30196 GIR_EraseFromParent, /*InsnID*/0, 30197 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30198 // GIR_Coverage, 2364, 30199 GIR_Done, 30200 // Label 1917: @74615 30201 GIM_Try, /*On fail goto*//*Label 1918*/ 74668, // Rule ID 909 // 30202 GIM_CheckFeatures, GIFBS_HasNEON, 30203 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30204 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 30205 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 30206 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, 30207 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 30209 GIM_CheckIsSafeToFold, /*InsnID*/1, 30210 // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rd) => (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) 30211 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f32, 30212 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 30213 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd 30214 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 30215 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 30216 GIR_EraseFromParent, /*InsnID*/0, 30217 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30218 // GIR_Coverage, 909, 30219 GIR_Done, 30220 // Label 1918: @74668 30221 GIM_Try, /*On fail goto*//*Label 1919*/ 74708, // Rule ID 904 // 30222 GIM_CheckFeatures, GIFBS_HasNEON, 30223 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30224 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 30225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 30226 // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLAv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) 30227 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2f32, 30228 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 30229 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd 30230 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 30231 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm 30232 GIR_EraseFromParent, /*InsnID*/0, 30233 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30234 // GIR_Coverage, 904, 30235 GIR_Done, 30236 // Label 1919: @74708 30237 GIM_Reject, 30238 // Label 1916: @74709 30239 GIM_Reject, 30240 // Label 1893: @74710 30241 GIM_Try, /*On fail goto*//*Label 1920*/ 74873, 30242 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 30243 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 30244 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 30245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 30246 GIM_Try, /*On fail goto*//*Label 1921*/ 74779, // Rule ID 2366 // 30247 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 30248 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 30249 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, 30250 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 30251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 30252 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 30253 GIM_CheckIsSafeToFold, /*InsnID*/1, 30254 // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rm, V128:{ *:[v2f64] }:$Rd) => (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) 30255 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f64, 30256 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 30257 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd 30258 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 30259 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 30260 GIR_EraseFromParent, /*InsnID*/0, 30261 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30262 // GIR_Coverage, 2366, 30263 GIR_Done, 30264 // Label 1921: @74779 30265 GIM_Try, /*On fail goto*//*Label 1922*/ 74832, // Rule ID 911 // 30266 GIM_CheckFeatures, GIFBS_HasNEON, 30267 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 30268 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 30269 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 30270 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, 30271 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 30272 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 30273 GIM_CheckIsSafeToFold, /*InsnID*/1, 30274 // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rd) => (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) 30275 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f64, 30276 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 30277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd 30278 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 30279 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 30280 GIR_EraseFromParent, /*InsnID*/0, 30281 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30282 // GIR_Coverage, 911, 30283 GIR_Done, 30284 // Label 1922: @74832 30285 GIM_Try, /*On fail goto*//*Label 1923*/ 74872, // Rule ID 906 // 30286 GIM_CheckFeatures, GIFBS_HasNEON, 30287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 30288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 30289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 30290 // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLAv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) 30291 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2f64, 30292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 30293 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd 30294 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 30295 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm 30296 GIR_EraseFromParent, /*InsnID*/0, 30297 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30298 // GIR_Coverage, 906, 30299 GIR_Done, 30300 // Label 1923: @74872 30301 GIM_Reject, 30302 // Label 1920: @74873 30303 GIM_Reject, 30304 // Label 1894: @74874 30305 GIM_Try, /*On fail goto*//*Label 1924*/ 74982, 30306 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 30307 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 30308 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, 30309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 30310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30311 GIM_Try, /*On fail goto*//*Label 1925*/ 74945, // Rule ID 907 // 30312 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 30313 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 30314 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 30315 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, 30316 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 30318 GIM_CheckIsSafeToFold, /*InsnID*/1, 30319 // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rd) => (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) 30320 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f16, 30321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 30322 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd 30323 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 30324 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 30325 GIR_EraseFromParent, /*InsnID*/0, 30326 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30327 // GIR_Coverage, 907, 30328 GIR_Done, 30329 // Label 1925: @74945 30330 GIM_Try, /*On fail goto*//*Label 1926*/ 74981, // Rule ID 902 // 30331 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 30332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 30333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 30334 // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLAv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) 30335 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4f16, 30336 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 30337 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd 30338 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 30339 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm 30340 GIR_EraseFromParent, /*InsnID*/0, 30341 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30342 // GIR_Coverage, 902, 30343 GIR_Done, 30344 // Label 1926: @74981 30345 GIM_Reject, 30346 // Label 1924: @74982 30347 GIM_Reject, 30348 // Label 1895: @74983 30349 GIM_Try, /*On fail goto*//*Label 1927*/ 75146, 30350 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 30351 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 30352 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 30353 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 30354 GIM_Try, /*On fail goto*//*Label 1928*/ 75052, // Rule ID 2365 // 30355 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 30356 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 30357 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 30358 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 30359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 30360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 30361 GIM_CheckIsSafeToFold, /*InsnID*/1, 30362 // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rm, V128:{ *:[v4f32] }:$Rd) => (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) 30363 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f32, 30364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 30365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd 30366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 30367 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm 30368 GIR_EraseFromParent, /*InsnID*/0, 30369 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30370 // GIR_Coverage, 2365, 30371 GIR_Done, 30372 // Label 1928: @75052 30373 GIM_Try, /*On fail goto*//*Label 1929*/ 75105, // Rule ID 910 // 30374 GIM_CheckFeatures, GIFBS_HasNEON, 30375 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 30376 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 30377 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 30378 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 30379 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 30380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 30381 GIM_CheckIsSafeToFold, /*InsnID*/1, 30382 // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rd) => (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) 30383 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f32, 30384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 30385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd 30386 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 30387 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 30388 GIR_EraseFromParent, /*InsnID*/0, 30389 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30390 // GIR_Coverage, 910, 30391 GIR_Done, 30392 // Label 1929: @75105 30393 GIM_Try, /*On fail goto*//*Label 1930*/ 75145, // Rule ID 905 // 30394 GIM_CheckFeatures, GIFBS_HasNEON, 30395 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 30396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 30397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 30398 // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLAv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) 30399 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4f32, 30400 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 30401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd 30402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 30403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm 30404 GIR_EraseFromParent, /*InsnID*/0, 30405 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30406 // GIR_Coverage, 905, 30407 GIR_Done, 30408 // Label 1930: @75145 30409 GIM_Reject, 30410 // Label 1927: @75146 30411 GIM_Reject, 30412 // Label 1896: @75147 30413 GIM_Try, /*On fail goto*//*Label 1931*/ 75255, 30414 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 30415 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 30416 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 30417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 30418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 30419 GIM_Try, /*On fail goto*//*Label 1932*/ 75218, // Rule ID 908 // 30420 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 30421 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 30422 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 30423 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, 30424 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 30425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 30426 GIM_CheckIsSafeToFold, /*InsnID*/1, 30427 // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rd) => (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) 30428 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8f16, 30429 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 30430 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd 30431 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn 30432 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm 30433 GIR_EraseFromParent, /*InsnID*/0, 30434 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30435 // GIR_Coverage, 908, 30436 GIR_Done, 30437 // Label 1932: @75218 30438 GIM_Try, /*On fail goto*//*Label 1933*/ 75254, // Rule ID 903 // 30439 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 30440 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 30441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, 30442 // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLAv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) 30443 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv8f16, 30444 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 30445 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd 30446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn 30447 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm 30448 GIR_EraseFromParent, /*InsnID*/0, 30449 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30450 // GIR_Coverage, 903, 30451 GIR_Done, 30452 // Label 1933: @75254 30453 GIM_Reject, 30454 // Label 1931: @75255 30455 GIM_Reject, 30456 // Label 1897: @75256 30457 GIM_Reject, 30458 // Label 39: @75257 30459 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 1942*/ 75529, 30460 /*GILLT_s16*//*Label 1934*/ 75273, 30461 /*GILLT_s32*//*Label 1935*/ 75305, 30462 /*GILLT_s64*//*Label 1936*/ 75337, 0, 30463 /*GILLT_v2s32*//*Label 1937*/ 75369, 30464 /*GILLT_v2s64*//*Label 1938*/ 75401, 30465 /*GILLT_v4s16*//*Label 1939*/ 75433, 30466 /*GILLT_v4s32*//*Label 1940*/ 75465, 0, 30467 /*GILLT_v8s16*//*Label 1941*/ 75497, 30468 // Label 1934: @75273 30469 GIM_Try, /*On fail goto*//*Label 1943*/ 75304, // Rule ID 410 // 30470 GIM_CheckFeatures, GIFBS_HasFullFP16, 30471 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 30472 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 30473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 30474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, 30475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 30476 // (fdiv:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FDIVHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) 30477 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVHrr, 30478 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30479 // GIR_Coverage, 410, 30480 GIR_Done, 30481 // Label 1943: @75304 30482 GIM_Reject, 30483 // Label 1935: @75305 30484 GIM_Try, /*On fail goto*//*Label 1944*/ 75336, // Rule ID 411 // 30485 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30486 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 30487 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 30488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 30489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 30490 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 30491 // (fdiv:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FDIVSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) 30492 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVSrr, 30493 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30494 // GIR_Coverage, 411, 30495 GIR_Done, 30496 // Label 1944: @75336 30497 GIM_Reject, 30498 // Label 1936: @75337 30499 GIM_Try, /*On fail goto*//*Label 1945*/ 75368, // Rule ID 412 // 30500 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30501 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 30502 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 30503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 30504 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30505 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 30506 // (fdiv:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FDIVDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) 30507 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVDrr, 30508 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30509 // GIR_Coverage, 412, 30510 GIR_Done, 30511 // Label 1945: @75368 30512 GIM_Reject, 30513 // Label 1937: @75369 30514 GIM_Try, /*On fail goto*//*Label 1946*/ 75400, // Rule ID 859 // 30515 GIM_CheckFeatures, GIFBS_HasNEON, 30516 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 30517 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, 30518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 30519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 30521 // (fdiv:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FDIVv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) 30522 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv2f32, 30523 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30524 // GIR_Coverage, 859, 30525 GIR_Done, 30526 // Label 1946: @75400 30527 GIM_Reject, 30528 // Label 1938: @75401 30529 GIM_Try, /*On fail goto*//*Label 1947*/ 75432, // Rule ID 861 // 30530 GIM_CheckFeatures, GIFBS_HasNEON, 30531 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 30532 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 30533 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 30534 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 30535 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 30536 // (fdiv:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FDIVv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) 30537 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv2f64, 30538 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30539 // GIR_Coverage, 861, 30540 GIR_Done, 30541 // Label 1947: @75432 30542 GIM_Reject, 30543 // Label 1939: @75433 30544 GIM_Try, /*On fail goto*//*Label 1948*/ 75464, // Rule ID 857 // 30545 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 30546 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 30547 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, 30548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 30549 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30550 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 30551 // (fdiv:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FDIVv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) 30552 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv4f16, 30553 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30554 // GIR_Coverage, 857, 30555 GIR_Done, 30556 // Label 1948: @75464 30557 GIM_Reject, 30558 // Label 1940: @75465 30559 GIM_Try, /*On fail goto*//*Label 1949*/ 75496, // Rule ID 860 // 30560 GIM_CheckFeatures, GIFBS_HasNEON, 30561 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 30562 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 30563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 30564 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 30565 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 30566 // (fdiv:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FDIVv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) 30567 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv4f32, 30568 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30569 // GIR_Coverage, 860, 30570 GIR_Done, 30571 // Label 1949: @75496 30572 GIM_Reject, 30573 // Label 1941: @75497 30574 GIM_Try, /*On fail goto*//*Label 1950*/ 75528, // Rule ID 858 // 30575 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 30576 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 30577 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 30578 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 30579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 30580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, 30581 // (fdiv:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FDIVv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) 30582 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv8f16, 30583 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30584 // GIR_Coverage, 858, 30585 GIR_Done, 30586 // Label 1950: @75528 30587 GIM_Reject, 30588 // Label 1942: @75529 30589 GIM_Reject, 30590 // Label 40: @75530 30591 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 1959*/ 76077, 30592 /*GILLT_s16*//*Label 1951*/ 75546, 30593 /*GILLT_s32*//*Label 1952*/ 75683, 30594 /*GILLT_s64*//*Label 1953*/ 75820, 0, 30595 /*GILLT_v2s32*//*Label 1954*/ 75957, 30596 /*GILLT_v2s64*//*Label 1955*/ 75981, 30597 /*GILLT_v4s16*//*Label 1956*/ 76005, 30598 /*GILLT_v4s32*//*Label 1957*/ 76029, 0, 30599 /*GILLT_v8s16*//*Label 1958*/ 76053, 30600 // Label 1951: @75546 30601 GIM_Try, /*On fail goto*//*Label 1960*/ 75682, 30602 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 30603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 30604 GIM_Try, /*On fail goto*//*Label 1961*/ 75617, // Rule ID 440 // 30605 GIM_CheckFeatures, GIFBS_HasFullFP16, 30606 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 30607 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, 30608 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, 30609 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, 30610 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, 30611 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, 30612 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 30613 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, 30614 GIM_CheckIsSafeToFold, /*InsnID*/1, 30615 // (fneg:{ *:[f16] } (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)) => (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) 30616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDHrrr, 30617 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 30618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 30619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 30620 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra 30621 GIR_EraseFromParent, /*InsnID*/0, 30622 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30623 // GIR_Coverage, 440, 30624 GIR_Done, 30625 // Label 1961: @75617 30626 GIM_Try, /*On fail goto*//*Label 1962*/ 75666, // Rule ID 428 // 30627 GIM_CheckFeatures, GIFBS_HasFullFP16, 30628 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 30629 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, 30630 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, 30631 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, 30632 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, 30633 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, 30634 GIM_CheckIsSafeToFold, /*InsnID*/1, 30635 // (fneg:{ *:[f16] } (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)) => (FNMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) 30636 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULHrr, 30637 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 30638 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 30639 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 30640 GIR_EraseFromParent, /*InsnID*/0, 30641 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30642 // GIR_Coverage, 428, 30643 GIR_Done, 30644 // Label 1962: @75666 30645 GIM_Try, /*On fail goto*//*Label 1963*/ 75681, // Rule ID 380 // 30646 GIM_CheckFeatures, GIFBS_HasFullFP16, 30647 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, 30648 // (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FNEGHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) 30649 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGHr, 30650 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30651 // GIR_Coverage, 380, 30652 GIR_Done, 30653 // Label 1963: @75681 30654 GIM_Reject, 30655 // Label 1960: @75682 30656 GIM_Reject, 30657 // Label 1952: @75683 30658 GIM_Try, /*On fail goto*//*Label 1964*/ 75819, 30659 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 30660 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 30661 GIM_Try, /*On fail goto*//*Label 1965*/ 75754, // Rule ID 441 // 30662 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30663 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 30664 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, 30665 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 30666 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 30667 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, 30668 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 30669 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 30670 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, 30671 GIM_CheckIsSafeToFold, /*InsnID*/1, 30672 // (fneg:{ *:[f32] } (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) 30673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDSrrr, 30674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 30675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 30676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 30677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra 30678 GIR_EraseFromParent, /*InsnID*/0, 30679 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30680 // GIR_Coverage, 441, 30681 GIR_Done, 30682 // Label 1965: @75754 30683 GIM_Try, /*On fail goto*//*Label 1966*/ 75803, // Rule ID 429 // 30684 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30685 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 30686 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, 30687 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 30688 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 30689 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 30690 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, 30691 GIM_CheckIsSafeToFold, /*InsnID*/1, 30692 // (fneg:{ *:[f32] } (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)) => (FNMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) 30693 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULSrr, 30694 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 30695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 30696 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 30697 GIR_EraseFromParent, /*InsnID*/0, 30698 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30699 // GIR_Coverage, 429, 30700 GIR_Done, 30701 // Label 1966: @75803 30702 GIM_Try, /*On fail goto*//*Label 1967*/ 75818, // Rule ID 381 // 30703 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30704 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 30705 // (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FNEGSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) 30706 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGSr, 30707 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30708 // GIR_Coverage, 381, 30709 GIR_Done, 30710 // Label 1967: @75818 30711 GIM_Reject, 30712 // Label 1964: @75819 30713 GIM_Reject, 30714 // Label 1953: @75820 30715 GIM_Try, /*On fail goto*//*Label 1968*/ 75956, 30716 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 30717 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 30718 GIM_Try, /*On fail goto*//*Label 1969*/ 75891, // Rule ID 442 // 30719 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30720 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 30721 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, 30722 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 30723 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 30724 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, 30725 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30726 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 30727 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, 30728 GIM_CheckIsSafeToFold, /*InsnID*/1, 30729 // (fneg:{ *:[f64] } (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) 30730 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDDrrr, 30731 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 30732 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 30733 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 30734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra 30735 GIR_EraseFromParent, /*InsnID*/0, 30736 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30737 // GIR_Coverage, 442, 30738 GIR_Done, 30739 // Label 1969: @75891 30740 GIM_Try, /*On fail goto*//*Label 1970*/ 75940, // Rule ID 430 // 30741 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30742 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 30743 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, 30744 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 30745 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 30746 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30747 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, 30748 GIM_CheckIsSafeToFold, /*InsnID*/1, 30749 // (fneg:{ *:[f64] } (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)) => (FNMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) 30750 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULDrr, 30751 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd 30752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn 30753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm 30754 GIR_EraseFromParent, /*InsnID*/0, 30755 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30756 // GIR_Coverage, 430, 30757 GIR_Done, 30758 // Label 1970: @75940 30759 GIM_Try, /*On fail goto*//*Label 1971*/ 75955, // Rule ID 382 // 30760 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30761 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30762 // (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FNEGDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) 30763 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGDr, 30764 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30765 // GIR_Coverage, 382, 30766 GIR_Done, 30767 // Label 1971: @75955 30768 GIM_Reject, 30769 // Label 1968: @75956 30770 GIM_Reject, 30771 // Label 1954: @75957 30772 GIM_Try, /*On fail goto*//*Label 1972*/ 75980, // Rule ID 607 // 30773 GIM_CheckFeatures, GIFBS_HasNEON, 30774 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 30775 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 30776 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30777 // (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FNEGv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) 30778 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv2f32, 30779 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30780 // GIR_Coverage, 607, 30781 GIR_Done, 30782 // Label 1972: @75980 30783 GIM_Reject, 30784 // Label 1955: @75981 30785 GIM_Try, /*On fail goto*//*Label 1973*/ 76004, // Rule ID 609 // 30786 GIM_CheckFeatures, GIFBS_HasNEON, 30787 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 30788 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 30789 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 30790 // (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FNEGv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) 30791 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv2f64, 30792 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30793 // GIR_Coverage, 609, 30794 GIR_Done, 30795 // Label 1973: @76004 30796 GIM_Reject, 30797 // Label 1956: @76005 30798 GIM_Try, /*On fail goto*//*Label 1974*/ 76028, // Rule ID 605 // 30799 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 30800 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 30801 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 30802 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30803 // (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FNEGv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) 30804 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv4f16, 30805 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30806 // GIR_Coverage, 605, 30807 GIR_Done, 30808 // Label 1974: @76028 30809 GIM_Reject, 30810 // Label 1957: @76029 30811 GIM_Try, /*On fail goto*//*Label 1975*/ 76052, // Rule ID 608 // 30812 GIM_CheckFeatures, GIFBS_HasNEON, 30813 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 30814 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 30815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 30816 // (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FNEGv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) 30817 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv4f32, 30818 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30819 // GIR_Coverage, 608, 30820 GIR_Done, 30821 // Label 1975: @76052 30822 GIM_Reject, 30823 // Label 1958: @76053 30824 GIM_Try, /*On fail goto*//*Label 1976*/ 76076, // Rule ID 606 // 30825 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 30826 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 30827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 30828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 30829 // (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FNEGv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) 30830 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv8f16, 30831 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30832 // GIR_Coverage, 606, 30833 GIR_Done, 30834 // Label 1976: @76076 30835 GIM_Reject, 30836 // Label 1959: @76077 30837 GIM_Reject, 30838 // Label 41: @76078 30839 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 8, /*)*//*default:*//*Label 1981*/ 76206, 30840 /*GILLT_s32*//*Label 1977*/ 76091, 30841 /*GILLT_s64*//*Label 1978*/ 76115, 0, 0, 30842 /*GILLT_v2s64*//*Label 1979*/ 76162, 0, 30843 /*GILLT_v4s32*//*Label 1980*/ 76184, 30844 // Label 1977: @76091 30845 GIM_Try, /*On fail goto*//*Label 1982*/ 76114, // Rule ID 374 // 30846 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30847 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 30848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 30849 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, 30850 // (fpextend:{ *:[f32] } FPR16:{ *:[f16] }:$Rn) => (FCVTSHr:{ *:[f32] } FPR16:{ *:[f16] }:$Rn) 30851 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTSHr, 30852 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30853 // GIR_Coverage, 374, 30854 GIR_Done, 30855 // Label 1982: @76114 30856 GIM_Reject, 30857 // Label 1978: @76115 30858 GIM_Try, /*On fail goto*//*Label 1983*/ 76138, // Rule ID 373 // 30859 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30860 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 30861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 30862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, 30863 // (fpextend:{ *:[f64] } FPR16:{ *:[f16] }:$Rn) => (FCVTDHr:{ *:[f64] } FPR16:{ *:[f16] }:$Rn) 30864 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTDHr, 30865 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30866 // GIR_Coverage, 373, 30867 GIR_Done, 30868 // Label 1983: @76138 30869 GIM_Try, /*On fail goto*//*Label 1984*/ 76161, // Rule ID 375 // 30870 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30871 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 30872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 30873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 30874 // (fpextend:{ *:[f64] } FPR32:{ *:[f32] }:$Rn) => (FCVTDSr:{ *:[f64] } FPR32:{ *:[f32] }:$Rn) 30875 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTDSr, 30876 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30877 // GIR_Coverage, 375, 30878 GIR_Done, 30879 // Label 1984: @76161 30880 GIM_Reject, 30881 // Label 1979: @76162 30882 GIM_Try, /*On fail goto*//*Label 1985*/ 76183, // Rule ID 2287 // 30883 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 30884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 30885 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30886 // (fpextend:{ *:[v2f64] } V64:{ *:[v2f32] }:$Rn) => (FCVTLv2i32:{ *:[v2f64] } V64:{ *:[v2f32] }:$Rn) 30887 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTLv2i32, 30888 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30889 // GIR_Coverage, 2287, 30890 GIR_Done, 30891 // Label 1985: @76183 30892 GIM_Reject, 30893 // Label 1980: @76184 30894 GIM_Try, /*On fail goto*//*Label 1986*/ 76205, // Rule ID 2289 // 30895 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 30896 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 30897 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30898 // (fpextend:{ *:[v4f32] } V64:{ *:[v4f16] }:$Rn) => (FCVTLv4i16:{ *:[v4f32] } V64:{ *:[v4f16] }:$Rn) 30899 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTLv4i16, 30900 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30901 // GIR_Coverage, 2289, 30902 GIR_Done, 30903 // Label 1986: @76205 30904 GIM_Reject, 30905 // Label 1981: @76206 30906 GIM_Reject, 30907 // Label 42: @76207 30908 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 7, /*)*//*default:*//*Label 1991*/ 76335, 30909 /*GILLT_s16*//*Label 1987*/ 76220, 30910 /*GILLT_s32*//*Label 1988*/ 76267, 0, 0, 30911 /*GILLT_v2s32*//*Label 1989*/ 76291, 0, 30912 /*GILLT_v4s16*//*Label 1990*/ 76313, 30913 // Label 1987: @76220 30914 GIM_Try, /*On fail goto*//*Label 1992*/ 76243, // Rule ID 371 // 30915 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30916 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 30917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 30918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30919 // (fpround:{ *:[f16] } FPR64:{ *:[f64] }:$Rn) => (FCVTHDr:{ *:[f16] } FPR64:{ *:[f64] }:$Rn) 30920 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTHDr, 30921 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30922 // GIR_Coverage, 371, 30923 GIR_Done, 30924 // Label 1992: @76243 30925 GIM_Try, /*On fail goto*//*Label 1993*/ 76266, // Rule ID 376 // 30926 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30927 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 30928 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 30929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 30930 // (fpround:{ *:[f16] } FPR32:{ *:[f32] }:$Rn) => (FCVTHSr:{ *:[f16] } FPR32:{ *:[f32] }:$Rn) 30931 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTHSr, 30932 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30933 // GIR_Coverage, 376, 30934 GIR_Done, 30935 // Label 1993: @76266 30936 GIM_Reject, 30937 // Label 1988: @76267 30938 GIM_Try, /*On fail goto*//*Label 1994*/ 76290, // Rule ID 372 // 30939 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30940 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 30941 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 30942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 30943 // (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$Rn) => (FCVTSDr:{ *:[f32] } FPR64:{ *:[f64] }:$Rn) 30944 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTSDr, 30945 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30946 // GIR_Coverage, 372, 30947 GIR_Done, 30948 // Label 1994: @76290 30949 GIM_Reject, 30950 // Label 1989: @76291 30951 GIM_Try, /*On fail goto*//*Label 1995*/ 76312, // Rule ID 2293 // 30952 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 30953 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 30954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 30955 // (fpround:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn) => (FCVTNv2i32:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn) 30956 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTNv2i32, 30957 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30958 // GIR_Coverage, 2293, 30959 GIR_Done, 30960 // Label 1995: @76312 30961 GIM_Reject, 30962 // Label 1990: @76313 30963 GIM_Try, /*On fail goto*//*Label 1996*/ 76334, // Rule ID 2294 // 30964 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 30965 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 30966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 30967 // (fpround:{ *:[v4f16] } V128:{ *:[v4f32] }:$Rn) => (FCVTNv4i16:{ *:[v4f16] } V128:{ *:[v4f32] }:$Rn) 30968 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTNv4i16, 30969 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30970 // GIR_Coverage, 2294, 30971 GIR_Done, 30972 // Label 1996: @76334 30973 GIM_Reject, 30974 // Label 1991: @76335 30975 GIM_Reject, 30976 // Label 43: @76336 30977 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 2004*/ 76611, 30978 /*GILLT_s32*//*Label 1997*/ 76351, 30979 /*GILLT_s64*//*Label 1998*/ 76421, 0, 30980 /*GILLT_v2s32*//*Label 1999*/ 76491, 30981 /*GILLT_v2s64*//*Label 2000*/ 76515, 30982 /*GILLT_v4s16*//*Label 2001*/ 76539, 30983 /*GILLT_v4s32*//*Label 2002*/ 76563, 0, 30984 /*GILLT_v8s16*//*Label 2003*/ 76587, 30985 // Label 1997: @76351 30986 GIM_Try, /*On fail goto*//*Label 2005*/ 76374, // Rule ID 320 // 30987 GIM_CheckFeatures, GIFBS_HasFullFP16, 30988 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 30989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 30990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, 30991 // (fp_to_sint:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) => (FCVTZSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) 30992 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUWHr, 30993 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 30994 // GIR_Coverage, 320, 30995 GIR_Done, 30996 // Label 2005: @76374 30997 GIM_Try, /*On fail goto*//*Label 2006*/ 76397, // Rule ID 322 // 30998 GIM_CheckFeatures, GIFBS_HasFPARMv8, 30999 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 31000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 31001 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 31002 // (fp_to_sint:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) => (FCVTZSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) 31003 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUWSr, 31004 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31005 // GIR_Coverage, 322, 31006 GIR_Done, 31007 // Label 2006: @76397 31008 GIM_Try, /*On fail goto*//*Label 2007*/ 76420, // Rule ID 324 // 31009 GIM_CheckFeatures, GIFBS_HasFPARMv8, 31010 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 31011 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 31012 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 31013 // (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) => (FCVTZSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) 31014 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUWDr, 31015 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31016 // GIR_Coverage, 324, 31017 GIR_Done, 31018 // Label 2007: @76420 31019 GIM_Reject, 31020 // Label 1998: @76421 31021 GIM_Try, /*On fail goto*//*Label 2008*/ 76444, // Rule ID 321 // 31022 GIM_CheckFeatures, GIFBS_HasFullFP16, 31023 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 31024 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 31025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, 31026 // (fp_to_sint:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) => (FCVTZSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) 31027 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUXHr, 31028 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31029 // GIR_Coverage, 321, 31030 GIR_Done, 31031 // Label 2008: @76444 31032 GIM_Try, /*On fail goto*//*Label 2009*/ 76467, // Rule ID 323 // 31033 GIM_CheckFeatures, GIFBS_HasFPARMv8, 31034 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 31035 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 31036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 31037 // (fp_to_sint:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) => (FCVTZSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) 31038 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUXSr, 31039 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31040 // GIR_Coverage, 323, 31041 GIR_Done, 31042 // Label 2009: @76467 31043 GIM_Try, /*On fail goto*//*Label 2010*/ 76490, // Rule ID 325 // 31044 GIM_CheckFeatures, GIFBS_HasFPARMv8, 31045 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 31046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 31047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 31048 // (fp_to_sint:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) => (FCVTZSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) 31049 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUXDr, 31050 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31051 // GIR_Coverage, 325, 31052 GIR_Done, 31053 // Label 2010: @76490 31054 GIM_Reject, 31055 // Label 1999: @76491 31056 GIM_Try, /*On fail goto*//*Label 2011*/ 76514, // Rule ID 597 // 31057 GIM_CheckFeatures, GIFBS_HasNEON, 31058 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 31059 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 31060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 31061 // (fp_to_sint:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCVTZSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) 31062 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv2f32, 31063 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31064 // GIR_Coverage, 597, 31065 GIR_Done, 31066 // Label 2011: @76514 31067 GIM_Reject, 31068 // Label 2000: @76515 31069 GIM_Try, /*On fail goto*//*Label 2012*/ 76538, // Rule ID 599 // 31070 GIM_CheckFeatures, GIFBS_HasNEON, 31071 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 31072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 31073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 31074 // (fp_to_sint:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCVTZSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) 31075 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv2f64, 31076 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31077 // GIR_Coverage, 599, 31078 GIR_Done, 31079 // Label 2012: @76538 31080 GIM_Reject, 31081 // Label 2001: @76539 31082 GIM_Try, /*On fail goto*//*Label 2013*/ 76562, // Rule ID 595 // 31083 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 31084 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 31085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 31086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 31087 // (fp_to_sint:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCVTZSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) 31088 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv4f16, 31089 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31090 // GIR_Coverage, 595, 31091 GIR_Done, 31092 // Label 2013: @76562 31093 GIM_Reject, 31094 // Label 2002: @76563 31095 GIM_Try, /*On fail goto*//*Label 2014*/ 76586, // Rule ID 598 // 31096 GIM_CheckFeatures, GIFBS_HasNEON, 31097 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 31098 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 31099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 31100 // (fp_to_sint:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCVTZSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) 31101 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv4f32, 31102 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31103 // GIR_Coverage, 598, 31104 GIR_Done, 31105 // Label 2014: @76586 31106 GIM_Reject, 31107 // Label 2003: @76587 31108 GIM_Try, /*On fail goto*//*Label 2015*/ 76610, // Rule ID 596 // 31109 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 31110 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 31111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 31112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 31113 // (fp_to_sint:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCVTZSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) 31114 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv8f16, 31115 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31116 // GIR_Coverage, 596, 31117 GIR_Done, 31118 // Label 2015: @76610 31119 GIM_Reject, 31120 // Label 2004: @76611 31121 GIM_Reject, 31122 // Label 44: @76612 31123 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 2023*/ 76887, 31124 /*GILLT_s32*//*Label 2016*/ 76627, 31125 /*GILLT_s64*//*Label 2017*/ 76697, 0, 31126 /*GILLT_v2s32*//*Label 2018*/ 76767, 31127 /*GILLT_v2s64*//*Label 2019*/ 76791, 31128 /*GILLT_v4s16*//*Label 2020*/ 76815, 31129 /*GILLT_v4s32*//*Label 2021*/ 76839, 0, 31130 /*GILLT_v8s16*//*Label 2022*/ 76863, 31131 // Label 2016: @76627 31132 GIM_Try, /*On fail goto*//*Label 2024*/ 76650, // Rule ID 326 // 31133 GIM_CheckFeatures, GIFBS_HasFullFP16, 31134 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 31135 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 31136 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, 31137 // (fp_to_uint:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) => (FCVTZUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) 31138 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUWHr, 31139 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31140 // GIR_Coverage, 326, 31141 GIR_Done, 31142 // Label 2024: @76650 31143 GIM_Try, /*On fail goto*//*Label 2025*/ 76673, // Rule ID 328 // 31144 GIM_CheckFeatures, GIFBS_HasFPARMv8, 31145 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 31146 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 31147 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 31148 // (fp_to_uint:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) => (FCVTZUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) 31149 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUWSr, 31150 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31151 // GIR_Coverage, 328, 31152 GIR_Done, 31153 // Label 2025: @76673 31154 GIM_Try, /*On fail goto*//*Label 2026*/ 76696, // Rule ID 330 // 31155 GIM_CheckFeatures, GIFBS_HasFPARMv8, 31156 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 31157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 31158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 31159 // (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) => (FCVTZUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) 31160 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUWDr, 31161 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31162 // GIR_Coverage, 330, 31163 GIR_Done, 31164 // Label 2026: @76696 31165 GIM_Reject, 31166 // Label 2017: @76697 31167 GIM_Try, /*On fail goto*//*Label 2027*/ 76720, // Rule ID 327 // 31168 GIM_CheckFeatures, GIFBS_HasFullFP16, 31169 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 31170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 31171 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, 31172 // (fp_to_uint:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) => (FCVTZUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) 31173 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUXHr, 31174 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31175 // GIR_Coverage, 327, 31176 GIR_Done, 31177 // Label 2027: @76720 31178 GIM_Try, /*On fail goto*//*Label 2028*/ 76743, // Rule ID 329 // 31179 GIM_CheckFeatures, GIFBS_HasFPARMv8, 31180 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 31181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 31182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, 31183 // (fp_to_uint:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) => (FCVTZUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) 31184 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUXSr, 31185 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31186 // GIR_Coverage, 329, 31187 GIR_Done, 31188 // Label 2028: @76743 31189 GIM_Try, /*On fail goto*//*Label 2029*/ 76766, // Rule ID 331 // 31190 GIM_CheckFeatures, GIFBS_HasFPARMv8, 31191 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 31192 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 31193 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 31194 // (fp_to_uint:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) => (FCVTZUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) 31195 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUXDr, 31196 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31197 // GIR_Coverage, 331, 31198 GIR_Done, 31199 // Label 2029: @76766 31200 GIM_Reject, 31201 // Label 2018: @76767 31202 GIM_Try, /*On fail goto*//*Label 2030*/ 76790, // Rule ID 602 // 31203 GIM_CheckFeatures, GIFBS_HasNEON, 31204 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 31205 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 31206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 31207 // (fp_to_uint:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCVTZUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) 31208 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv2f32, 31209 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31210 // GIR_Coverage, 602, 31211 GIR_Done, 31212 // Label 2030: @76790 31213 GIM_Reject, 31214 // Label 2019: @76791 31215 GIM_Try, /*On fail goto*//*Label 2031*/ 76814, // Rule ID 604 // 31216 GIM_CheckFeatures, GIFBS_HasNEON, 31217 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 31218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 31219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 31220 // (fp_to_uint:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCVTZUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) 31221 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv2f64, 31222 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31223 // GIR_Coverage, 604, 31224 GIR_Done, 31225 // Label 2031: @76814 31226 GIM_Reject, 31227 // Label 2020: @76815 31228 GIM_Try, /*On fail goto*//*Label 2032*/ 76838, // Rule ID 600 // 31229 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 31230 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 31231 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 31232 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 31233 // (fp_to_uint:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCVTZUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) 31234 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv4f16, 31235 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31236 // GIR_Coverage, 600, 31237 GIR_Done, 31238 // Label 2032: @76838 31239 GIM_Reject, 31240 // Label 2021: @76839 31241 GIM_Try, /*On fail goto*//*Label 2033*/ 76862, // Rule ID 603 // 31242 GIM_CheckFeatures, GIFBS_HasNEON, 31243 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 31244 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 31245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 31246 // (fp_to_uint:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCVTZUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) 31247 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv4f32, 31248 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31249 // GIR_Coverage, 603, 31250 GIR_Done, 31251 // Label 2033: @76862 31252 GIM_Reject, 31253 // Label 2022: @76863 31254 GIM_Try, /*On fail goto*//*Label 2034*/ 76886, // Rule ID 601 // 31255 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 31256 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 31257 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 31258 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 31259 // (fp_to_uint:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCVTZUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) 31260 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv8f16, 31261 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31262 // GIR_Coverage, 601, 31263 GIR_Done, 31264 // Label 2034: @76886 31265 GIM_Reject, 31266 // Label 2023: @76887 31267 GIM_Reject, 31268 // Label 45: @76888 31269 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 2043*/ 77165, 31270 /*GILLT_s16*//*Label 2035*/ 76904, 31271 /*GILLT_s32*//*Label 2036*/ 76951, 31272 /*GILLT_s64*//*Label 2037*/ 76998, 0, 31273 /*GILLT_v2s32*//*Label 2038*/ 77045, 31274 /*GILLT_v2s64*//*Label 2039*/ 77069, 31275 /*GILLT_v4s16*//*Label 2040*/ 77093, 31276 /*GILLT_v4s32*//*Label 2041*/ 77117, 0, 31277 /*GILLT_v8s16*//*Label 2042*/ 77141, 31278 // Label 2035: @76904 31279 GIM_Try, /*On fail goto*//*Label 2044*/ 76927, // Rule ID 344 // 31280 GIM_CheckFeatures, GIFBS_HasFullFP16, 31281 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 31282 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 31283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 31284 // (sint_to_fp:{ *:[f16] } GPR32:{ *:[i32] }:$Rn) => (SCVTFUWHri:{ *:[f16] } GPR32:{ *:[i32] }:$Rn) 31285 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUWHri, 31286 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31287 // GIR_Coverage, 344, 31288 GIR_Done, 31289 // Label 2044: @76927 31290 GIM_Try, /*On fail goto*//*Label 2045*/ 76950, // Rule ID 347 // 31291 GIM_CheckFeatures, GIFBS_HasFullFP16, 31292 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 31293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 31294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 31295 // (sint_to_fp:{ *:[f16] } GPR64:{ *:[i64] }:$Rn) => (SCVTFUXHri:{ *:[f16] } GPR64:{ *:[i64] }:$Rn) 31296 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUXHri, 31297 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31298 // GIR_Coverage, 347, 31299 GIR_Done, 31300 // Label 2045: @76950 31301 GIM_Reject, 31302 // Label 2036: @76951 31303 GIM_Try, /*On fail goto*//*Label 2046*/ 76974, // Rule ID 345 // 31304 GIM_CheckFeatures, GIFBS_HasFPARMv8, 31305 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 31306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 31307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 31308 // (sint_to_fp:{ *:[f32] } GPR32:{ *:[i32] }:$Rn) => (SCVTFUWSri:{ *:[f32] } GPR32:{ *:[i32] }:$Rn) 31309 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUWSri, 31310 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31311 // GIR_Coverage, 345, 31312 GIR_Done, 31313 // Label 2046: @76974 31314 GIM_Try, /*On fail goto*//*Label 2047*/ 76997, // Rule ID 348 // 31315 GIM_CheckFeatures, GIFBS_HasFPARMv8, 31316 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 31317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 31318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 31319 // (sint_to_fp:{ *:[f32] } GPR64:{ *:[i64] }:$Rn) => (SCVTFUXSri:{ *:[f32] } GPR64:{ *:[i64] }:$Rn) 31320 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUXSri, 31321 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31322 // GIR_Coverage, 348, 31323 GIR_Done, 31324 // Label 2047: @76997 31325 GIM_Reject, 31326 // Label 2037: @76998 31327 GIM_Try, /*On fail goto*//*Label 2048*/ 77021, // Rule ID 346 // 31328 GIM_CheckFeatures, GIFBS_HasFPARMv8, 31329 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 31330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 31331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 31332 // (sint_to_fp:{ *:[f64] } GPR32:{ *:[i32] }:$Rn) => (SCVTFUWDri:{ *:[f64] } GPR32:{ *:[i32] }:$Rn) 31333 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUWDri, 31334 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31335 // GIR_Coverage, 346, 31336 GIR_Done, 31337 // Label 2048: @77021 31338 GIM_Try, /*On fail goto*//*Label 2049*/ 77044, // Rule ID 349 // 31339 GIM_CheckFeatures, GIFBS_HasFPARMv8, 31340 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 31341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 31342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 31343 // (sint_to_fp:{ *:[f64] } GPR64:{ *:[i64] }:$Rn) => (SCVTFUXDri:{ *:[f64] } GPR64:{ *:[i64] }:$Rn) 31344 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUXDri, 31345 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31346 // GIR_Coverage, 349, 31347 GIR_Done, 31348 // Label 2049: @77044 31349 GIM_Reject, 31350 // Label 2038: @77045 31351 GIM_Try, /*On fail goto*//*Label 2050*/ 77068, // Rule ID 697 // 31352 GIM_CheckFeatures, GIFBS_HasNEON, 31353 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 31354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 31355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 31356 // (sint_to_fp:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn) => (SCVTFv2f32:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn) 31357 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv2f32, 31358 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31359 // GIR_Coverage, 697, 31360 GIR_Done, 31361 // Label 2050: @77068 31362 GIM_Reject, 31363 // Label 2039: @77069 31364 GIM_Try, /*On fail goto*//*Label 2051*/ 77092, // Rule ID 699 // 31365 GIM_CheckFeatures, GIFBS_HasNEON, 31366 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 31367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 31368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 31369 // (sint_to_fp:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn) => (SCVTFv2f64:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn) 31370 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv2f64, 31371 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31372 // GIR_Coverage, 699, 31373 GIR_Done, 31374 // Label 2051: @77092 31375 GIM_Reject, 31376 // Label 2040: @77093 31377 GIM_Try, /*On fail goto*//*Label 2052*/ 77116, // Rule ID 695 // 31378 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 31379 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 31380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 31381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 31382 // (sint_to_fp:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn) => (SCVTFv4f16:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn) 31383 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv4f16, 31384 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31385 // GIR_Coverage, 695, 31386 GIR_Done, 31387 // Label 2052: @77116 31388 GIM_Reject, 31389 // Label 2041: @77117 31390 GIM_Try, /*On fail goto*//*Label 2053*/ 77140, // Rule ID 698 // 31391 GIM_CheckFeatures, GIFBS_HasNEON, 31392 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 31393 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 31394 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 31395 // (sint_to_fp:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn) => (SCVTFv4f32:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn) 31396 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv4f32, 31397 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31398 // GIR_Coverage, 698, 31399 GIR_Done, 31400 // Label 2053: @77140 31401 GIM_Reject, 31402 // Label 2042: @77141 31403 GIM_Try, /*On fail goto*//*Label 2054*/ 77164, // Rule ID 696 // 31404 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 31405 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 31406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 31407 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 31408 // (sint_to_fp:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn) => (SCVTFv8f16:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn) 31409 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv8f16, 31410 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31411 // GIR_Coverage, 696, 31412 GIR_Done, 31413 // Label 2054: @77164 31414 GIM_Reject, 31415 // Label 2043: @77165 31416 GIM_Reject, 31417 // Label 46: @77166 31418 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 2063*/ 77443, 31419 /*GILLT_s16*//*Label 2055*/ 77182, 31420 /*GILLT_s32*//*Label 2056*/ 77229, 31421 /*GILLT_s64*//*Label 2057*/ 77276, 0, 31422 /*GILLT_v2s32*//*Label 2058*/ 77323, 31423 /*GILLT_v2s64*//*Label 2059*/ 77347, 31424 /*GILLT_v4s16*//*Label 2060*/ 77371, 31425 /*GILLT_v4s32*//*Label 2061*/ 77395, 0, 31426 /*GILLT_v8s16*//*Label 2062*/ 77419, 31427 // Label 2055: @77182 31428 GIM_Try, /*On fail goto*//*Label 2064*/ 77205, // Rule ID 356 // 31429 GIM_CheckFeatures, GIFBS_HasFullFP16, 31430 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 31431 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 31432 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 31433 // (uint_to_fp:{ *:[f16] } GPR32:{ *:[i32] }:$Rn) => (UCVTFUWHri:{ *:[f16] } GPR32:{ *:[i32] }:$Rn) 31434 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUWHri, 31435 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31436 // GIR_Coverage, 356, 31437 GIR_Done, 31438 // Label 2064: @77205 31439 GIM_Try, /*On fail goto*//*Label 2065*/ 77228, // Rule ID 359 // 31440 GIM_CheckFeatures, GIFBS_HasFullFP16, 31441 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 31442 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, 31443 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 31444 // (uint_to_fp:{ *:[f16] } GPR64:{ *:[i64] }:$Rn) => (UCVTFUXHri:{ *:[f16] } GPR64:{ *:[i64] }:$Rn) 31445 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUXHri, 31446 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31447 // GIR_Coverage, 359, 31448 GIR_Done, 31449 // Label 2065: @77228 31450 GIM_Reject, 31451 // Label 2056: @77229 31452 GIM_Try, /*On fail goto*//*Label 2066*/ 77252, // Rule ID 357 // 31453 GIM_CheckFeatures, GIFBS_HasFPARMv8, 31454 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 31455 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 31456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 31457 // (uint_to_fp:{ *:[f32] } GPR32:{ *:[i32] }:$Rn) => (UCVTFUWSri:{ *:[f32] } GPR32:{ *:[i32] }:$Rn) 31458 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUWSri, 31459 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31460 // GIR_Coverage, 357, 31461 GIR_Done, 31462 // Label 2066: @77252 31463 GIM_Try, /*On fail goto*//*Label 2067*/ 77275, // Rule ID 360 // 31464 GIM_CheckFeatures, GIFBS_HasFPARMv8, 31465 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 31466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, 31467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 31468 // (uint_to_fp:{ *:[f32] } GPR64:{ *:[i64] }:$Rn) => (UCVTFUXSri:{ *:[f32] } GPR64:{ *:[i64] }:$Rn) 31469 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUXSri, 31470 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31471 // GIR_Coverage, 360, 31472 GIR_Done, 31473 // Label 2067: @77275 31474 GIM_Reject, 31475 // Label 2057: @77276 31476 GIM_Try, /*On fail goto*//*Label 2068*/ 77299, // Rule ID 358 // 31477 GIM_CheckFeatures, GIFBS_HasFPARMv8, 31478 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 31479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 31480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 31481 // (uint_to_fp:{ *:[f64] } GPR32:{ *:[i32] }:$Rn) => (UCVTFUWDri:{ *:[f64] } GPR32:{ *:[i32] }:$Rn) 31482 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUWDri, 31483 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31484 // GIR_Coverage, 358, 31485 GIR_Done, 31486 // Label 2068: @77299 31487 GIM_Try, /*On fail goto*//*Label 2069*/ 77322, // Rule ID 361 // 31488 GIM_CheckFeatures, GIFBS_HasFPARMv8, 31489 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 31490 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 31491 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 31492 // (uint_to_fp:{ *:[f64] } GPR64:{ *:[i64] }:$Rn) => (UCVTFUXDri:{ *:[f64] } GPR64:{ *:[i64] }:$Rn) 31493 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUXDri, 31494 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31495 // GIR_Coverage, 361, 31496 GIR_Done, 31497 // Label 2069: @77322 31498 GIM_Reject, 31499 // Label 2058: @77323 31500 GIM_Try, /*On fail goto*//*Label 2070*/ 77346, // Rule ID 741 // 31501 GIM_CheckFeatures, GIFBS_HasNEON, 31502 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, 31503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 31504 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 31505 // (uint_to_fp:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn) => (UCVTFv2f32:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn) 31506 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv2f32, 31507 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31508 // GIR_Coverage, 741, 31509 GIR_Done, 31510 // Label 2070: @77346 31511 GIM_Reject, 31512 // Label 2059: @77347 31513 GIM_Try, /*On fail goto*//*Label 2071*/ 77370, // Rule ID 743 // 31514 GIM_CheckFeatures, GIFBS_HasNEON, 31515 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 31516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 31517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 31518 // (uint_to_fp:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn) => (UCVTFv2f64:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn) 31519 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv2f64, 31520 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31521 // GIR_Coverage, 743, 31522 GIR_Done, 31523 // Label 2071: @77370 31524 GIM_Reject, 31525 // Label 2060: @77371 31526 GIM_Try, /*On fail goto*//*Label 2072*/ 77394, // Rule ID 739 // 31527 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 31528 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, 31529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, 31530 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, 31531 // (uint_to_fp:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn) => (UCVTFv4f16:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn) 31532 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv4f16, 31533 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31534 // GIR_Coverage, 739, 31535 GIR_Done, 31536 // Label 2072: @77394 31537 GIM_Reject, 31538 // Label 2061: @77395 31539 GIM_Try, /*On fail goto*//*Label 2073*/ 77418, // Rule ID 742 // 31540 GIM_CheckFeatures, GIFBS_HasNEON, 31541 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 31542 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 31543 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 31544 // (uint_to_fp:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn) => (UCVTFv4f32:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn) 31545 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv4f32, 31546 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31547 // GIR_Coverage, 742, 31548 GIR_Done, 31549 // Label 2073: @77418 31550 GIM_Reject, 31551 // Label 2062: @77419 31552 GIM_Try, /*On fail goto*//*Label 2074*/ 77442, // Rule ID 740 // 31553 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, 31554 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 31555 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, 31556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, 31557 // (uint_to_fp:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn) => (UCVTFv8f16:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn) 31558 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv8f16, 31559 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31560 // GIR_Coverage, 740, 31561 GIR_Done, 31562 // Label 2074: @77442 31563 GIM_Reject, 31564 // Label 2063: @77443 31565 GIM_Reject, 31566 // Label 47: @77444 31567 GIM_Try, /*On fail goto*//*Label 2075*/ 77456, // Rule ID 159 // 31568 // MIs[0] addr 31569 GIM_CheckIsMBB, /*MI*/0, /*Op*/0, 31570 // (br (bb:{ *:[Other] }):$addr) => (B (bb:{ *:[Other] }):$addr) 31571 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::B, 31572 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31573 // GIR_Coverage, 159, 31574 GIR_Done, 31575 // Label 2075: @77456 31576 GIM_Reject, 31577 // Label 48: @77457 31578 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 2078*/ 77509, 31579 /*GILLT_s32*//*Label 2076*/ 77465, 31580 /*GILLT_s64*//*Label 2077*/ 77487, 31581 // Label 2076: @77465 31582 GIM_Try, /*On fail goto*//*Label 2079*/ 77486, // Rule ID 124 // 31583 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 31584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, 31585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, 31586 // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (REVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) 31587 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REVWr, 31588 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31589 // GIR_Coverage, 124, 31590 GIR_Done, 31591 // Label 2079: @77486 31592 GIM_Reject, 31593 // Label 2077: @77487 31594 GIM_Try, /*On fail goto*//*Label 2080*/ 77508, // Rule ID 125 // 31595 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 31596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, 31597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, 31598 // (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (REVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) 31599 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REVXr, 31600 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 31601 // GIR_Coverage, 125, 31602 GIR_Done, 31603 // Label 2080: @77508 31604 GIM_Reject, 31605 // Label 2078: @77509 31606 GIM_Reject, 31607 // Label 49: @77510 31608 GIM_Reject, 31609 }; 31610 return MatchTable0; 31611} 31612#endif // ifdef GET_GLOBALISEL_IMPL 31613#ifdef GET_GLOBALISEL_PREDICATES_DECL 31614PredicateBitset AvailableModuleFeatures; 31615mutable PredicateBitset AvailableFunctionFeatures; 31616PredicateBitset getAvailableFeatures() const { 31617 return AvailableModuleFeatures | AvailableFunctionFeatures; 31618} 31619PredicateBitset 31620computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const; 31621PredicateBitset 31622computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget, 31623 const MachineFunction *MF) const; 31624#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL 31625#ifdef GET_GLOBALISEL_PREDICATES_INIT 31626AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), 31627AvailableFunctionFeatures() 31628#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT 31629