1//===-- AMDGPURegisterInfo.td - AMDGPU register info -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Tablegen register definitions common to all hw codegen targets. 11// 12//===----------------------------------------------------------------------===// 13 14let Namespace = "AMDGPU" in { 15 16foreach Index = 0-15 in { 17 def sub#Index : SubRegIndex<32, !shl(Index, 5)>; 18} 19 20} 21 22include "SIRegisterInfo.td" 23