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1//===- HexagonDepInstrFormats.td ------------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// Automatically generated file, please consult code owner before editing.
10//===----------------------------------------------------------------------===//
11
12
13class Enc_890909 : OpcodeHexagon {
14  bits <5> Rs32;
15  let Inst{20-16} = Rs32{4-0};
16  bits <5> Rd32;
17  let Inst{4-0} = Rd32{4-0};
18  bits <2> Pe4;
19  let Inst{6-5} = Pe4{1-0};
20}
21class Enc_9be1de : OpcodeHexagon {
22  bits <2> Qs4;
23  let Inst{6-5} = Qs4{1-0};
24  bits <5> Rt32;
25  let Inst{20-16} = Rt32{4-0};
26  bits <1> Mu2;
27  let Inst{13-13} = Mu2{0-0};
28  bits <5> Vv32;
29  let Inst{12-8} = Vv32{4-0};
30  bits <5> Vw32;
31  let Inst{4-0} = Vw32{4-0};
32}
33class Enc_527412 : OpcodeHexagon {
34  bits <2> Ps4;
35  let Inst{17-16} = Ps4{1-0};
36  bits <2> Pt4;
37  let Inst{9-8} = Pt4{1-0};
38  bits <5> Rd32;
39  let Inst{4-0} = Rd32{4-0};
40}
41class Enc_efaed8 : OpcodeHexagon {
42  bits <1> Ii;
43  let Inst{8-8} = Ii{0-0};
44}
45class Enc_a568d4 : OpcodeHexagon {
46  bits <5> Rt32;
47  let Inst{12-8} = Rt32{4-0};
48  bits <5> Rs32;
49  let Inst{20-16} = Rs32{4-0};
50  bits <5> Rx32;
51  let Inst{4-0} = Rx32{4-0};
52}
53class Enc_27b757 : OpcodeHexagon {
54  bits <4> Ii;
55  let Inst{13-13} = Ii{3-3};
56  let Inst{10-8} = Ii{2-0};
57  bits <2> Pv4;
58  let Inst{12-11} = Pv4{1-0};
59  bits <5> Rt32;
60  let Inst{20-16} = Rt32{4-0};
61  bits <5> Vs32;
62  let Inst{4-0} = Vs32{4-0};
63}
64class Enc_8d04c3 : OpcodeHexagon {
65  bits <5> Vu32;
66  let Inst{20-16} = Vu32{4-0};
67  bits <5> Vv32;
68  let Inst{12-8} = Vv32{4-0};
69  bits <5> Vd32;
70  let Inst{7-3} = Vd32{4-0};
71}
72class Enc_1de724 : OpcodeHexagon {
73  bits <11> Ii;
74  let Inst{21-20} = Ii{10-9};
75  let Inst{7-1} = Ii{8-2};
76  bits <4> Rs16;
77  let Inst{19-16} = Rs16{3-0};
78  bits <4> n1;
79  let Inst{28-28} = n1{3-3};
80  let Inst{24-22} = n1{2-0};
81}
82class Enc_0e41fa : OpcodeHexagon {
83  bits <5> Vuu32;
84  let Inst{12-8} = Vuu32{4-0};
85  bits <5> Rt32;
86  let Inst{20-16} = Rt32{4-0};
87  bits <5> Vd32;
88  let Inst{4-0} = Vd32{4-0};
89}
90class Enc_2a736a : OpcodeHexagon {
91  bits <5> Vuu32;
92  let Inst{20-16} = Vuu32{4-0};
93  bits <5> Vdd32;
94  let Inst{7-3} = Vdd32{4-0};
95}
96class Enc_3d6d37 : OpcodeHexagon {
97  bits <2> Qs4;
98  let Inst{6-5} = Qs4{1-0};
99  bits <5> Rt32;
100  let Inst{20-16} = Rt32{4-0};
101  bits <1> Mu2;
102  let Inst{13-13} = Mu2{0-0};
103  bits <5> Vvv32;
104  let Inst{12-8} = Vvv32{4-0};
105  bits <5> Vw32;
106  let Inst{4-0} = Vw32{4-0};
107}
108class Enc_a641d0 : OpcodeHexagon {
109  bits <5> Rt32;
110  let Inst{20-16} = Rt32{4-0};
111  bits <1> Mu2;
112  let Inst{13-13} = Mu2{0-0};
113  bits <5> Vvv32;
114  let Inst{12-8} = Vvv32{4-0};
115  bits <5> Vw32;
116  let Inst{4-0} = Vw32{4-0};
117}
118class Enc_802dc0 : OpcodeHexagon {
119  bits <1> Ii;
120  let Inst{8-8} = Ii{0-0};
121  bits <2> Qv4;
122  let Inst{23-22} = Qv4{1-0};
123}
124class Enc_6a4549 : OpcodeHexagon {
125  bits <5> Vu32;
126  let Inst{12-8} = Vu32{4-0};
127  bits <5> Rt32;
128  let Inst{20-16} = Rt32{4-0};
129  bits <5> Vd32;
130  let Inst{7-3} = Vd32{4-0};
131}
132class Enc_6b197f : OpcodeHexagon {
133  bits <4> Ii;
134  let Inst{8-5} = Ii{3-0};
135  bits <5> Ryy32;
136  let Inst{4-0} = Ryy32{4-0};
137  bits <5> Rx32;
138  let Inst{20-16} = Rx32{4-0};
139}
140class Enc_1f3376 : OpcodeHexagon {
141  bits <5> Vu32;
142  let Inst{20-16} = Vu32{4-0};
143  bits <5> Vv32;
144  let Inst{12-8} = Vv32{4-0};
145  bits <5> Vxx32;
146  let Inst{7-3} = Vxx32{4-0};
147}
148class Enc_1f5d8f : OpcodeHexagon {
149  bits <1> Mu2;
150  let Inst{13-13} = Mu2{0-0};
151  bits <5> Ryy32;
152  let Inst{4-0} = Ryy32{4-0};
153  bits <5> Rx32;
154  let Inst{20-16} = Rx32{4-0};
155}
156class Enc_51436c : OpcodeHexagon {
157  bits <16> Ii;
158  let Inst{23-22} = Ii{15-14};
159  let Inst{13-0} = Ii{13-0};
160  bits <5> Rx32;
161  let Inst{20-16} = Rx32{4-0};
162}
163class Enc_c7a204 : OpcodeHexagon {
164  bits <6> II;
165  let Inst{5-0} = II{5-0};
166  bits <5> Rtt32;
167  let Inst{12-8} = Rtt32{4-0};
168  bits <5> Re32;
169  let Inst{20-16} = Re32{4-0};
170}
171class Enc_db40cd : OpcodeHexagon {
172  bits <6> Ii;
173  let Inst{6-3} = Ii{5-2};
174  bits <5> Rt32;
175  let Inst{12-8} = Rt32{4-0};
176  bits <5> Rx32;
177  let Inst{20-16} = Rx32{4-0};
178}
179class Enc_a1e29d : OpcodeHexagon {
180  bits <5> Ii;
181  let Inst{12-8} = Ii{4-0};
182  bits <5> II;
183  let Inst{22-21} = II{4-3};
184  let Inst{7-5} = II{2-0};
185  bits <5> Rs32;
186  let Inst{20-16} = Rs32{4-0};
187  bits <5> Rx32;
188  let Inst{4-0} = Rx32{4-0};
189}
190class Enc_d15d19 : OpcodeHexagon {
191  bits <1> Mu2;
192  let Inst{13-13} = Mu2{0-0};
193  bits <5> Vs32;
194  let Inst{4-0} = Vs32{4-0};
195  bits <5> Rx32;
196  let Inst{20-16} = Rx32{4-0};
197}
198class Enc_e90a15 : OpcodeHexagon {
199  bits <11> Ii;
200  let Inst{21-20} = Ii{10-9};
201  let Inst{7-1} = Ii{8-2};
202  bits <3> Ns8;
203  let Inst{18-16} = Ns8{2-0};
204  bits <4> n1;
205  let Inst{29-29} = n1{3-3};
206  let Inst{26-25} = n1{2-1};
207  let Inst{22-22} = n1{0-0};
208}
209class Enc_e0a47a : OpcodeHexagon {
210  bits <4> Ii;
211  let Inst{8-5} = Ii{3-0};
212  bits <1> Mu2;
213  let Inst{13-13} = Mu2{0-0};
214  bits <5> Rd32;
215  let Inst{4-0} = Rd32{4-0};
216  bits <5> Rx32;
217  let Inst{20-16} = Rx32{4-0};
218}
219class Enc_140c83 : OpcodeHexagon {
220  bits <10> Ii;
221  let Inst{21-21} = Ii{9-9};
222  let Inst{13-5} = Ii{8-0};
223  bits <5> Rs32;
224  let Inst{20-16} = Rs32{4-0};
225  bits <5> Rd32;
226  let Inst{4-0} = Rd32{4-0};
227}
228class Enc_7eee72 : OpcodeHexagon {
229  bits <1> Mu2;
230  let Inst{13-13} = Mu2{0-0};
231  bits <5> Rdd32;
232  let Inst{4-0} = Rdd32{4-0};
233  bits <5> Rx32;
234  let Inst{20-16} = Rx32{4-0};
235}
236class Enc_310ba1 : OpcodeHexagon {
237  bits <5> Vu32;
238  let Inst{12-8} = Vu32{4-0};
239  bits <5> Rtt32;
240  let Inst{20-16} = Rtt32{4-0};
241  bits <5> Vx32;
242  let Inst{4-0} = Vx32{4-0};
243}
244class Enc_d7dc10 : OpcodeHexagon {
245  bits <5> Rs32;
246  let Inst{20-16} = Rs32{4-0};
247  bits <5> Rtt32;
248  let Inst{12-8} = Rtt32{4-0};
249  bits <2> Pd4;
250  let Inst{1-0} = Pd4{1-0};
251}
252class Enc_736575 : OpcodeHexagon {
253  bits <11> Ii;
254  let Inst{21-20} = Ii{10-9};
255  let Inst{7-1} = Ii{8-2};
256  bits <4> Rs16;
257  let Inst{19-16} = Rs16{3-0};
258  bits <4> n1;
259  let Inst{28-28} = n1{3-3};
260  let Inst{25-23} = n1{2-0};
261}
262class Enc_8dec2e : OpcodeHexagon {
263  bits <5> Ii;
264  let Inst{12-8} = Ii{4-0};
265  bits <5> Rss32;
266  let Inst{20-16} = Rss32{4-0};
267  bits <5> Rd32;
268  let Inst{4-0} = Rd32{4-0};
269}
270class Enc_28dcbb : OpcodeHexagon {
271  bits <5> Rt32;
272  let Inst{20-16} = Rt32{4-0};
273  bits <1> Mu2;
274  let Inst{13-13} = Mu2{0-0};
275  bits <5> Vvv32;
276  let Inst{4-0} = Vvv32{4-0};
277}
278class Enc_eaa9f8 : OpcodeHexagon {
279  bits <5> Vu32;
280  let Inst{12-8} = Vu32{4-0};
281  bits <5> Vv32;
282  let Inst{20-16} = Vv32{4-0};
283  bits <2> Qx4;
284  let Inst{1-0} = Qx4{1-0};
285}
286class Enc_509701 : OpcodeHexagon {
287  bits <19> Ii;
288  let Inst{26-25} = Ii{18-17};
289  let Inst{20-16} = Ii{16-12};
290  let Inst{13-5} = Ii{11-3};
291  bits <5> Rdd32;
292  let Inst{4-0} = Rdd32{4-0};
293}
294class Enc_c84567 : OpcodeHexagon {
295  bits <5> Vuu32;
296  let Inst{20-16} = Vuu32{4-0};
297  bits <5> Vv32;
298  let Inst{12-8} = Vv32{4-0};
299  bits <5> Vdd32;
300  let Inst{7-3} = Vdd32{4-0};
301}
302class Enc_830e5d : OpcodeHexagon {
303  bits <8> Ii;
304  let Inst{12-5} = Ii{7-0};
305  bits <8> II;
306  let Inst{22-16} = II{7-1};
307  let Inst{13-13} = II{0-0};
308  bits <2> Pu4;
309  let Inst{24-23} = Pu4{1-0};
310  bits <5> Rd32;
311  let Inst{4-0} = Rd32{4-0};
312}
313class Enc_ae0040 : OpcodeHexagon {
314  bits <5> Rs32;
315  let Inst{20-16} = Rs32{4-0};
316  bits <6> Sd64;
317  let Inst{5-0} = Sd64{5-0};
318}
319class Enc_79b8c8 : OpcodeHexagon {
320  bits <6> Ii;
321  let Inst{6-3} = Ii{5-2};
322  bits <1> Mu2;
323  let Inst{13-13} = Mu2{0-0};
324  bits <5> Rt32;
325  let Inst{12-8} = Rt32{4-0};
326  bits <5> Rx32;
327  let Inst{20-16} = Rx32{4-0};
328}
329class Enc_58a8bf : OpcodeHexagon {
330  bits <3> Ii;
331  let Inst{10-8} = Ii{2-0};
332  bits <2> Pv4;
333  let Inst{12-11} = Pv4{1-0};
334  bits <5> Vd32;
335  let Inst{4-0} = Vd32{4-0};
336  bits <5> Rx32;
337  let Inst{20-16} = Rx32{4-0};
338}
339class Enc_e8ddd5 : OpcodeHexagon {
340  bits <16> Ii;
341  let Inst{21-21} = Ii{15-15};
342  let Inst{13-8} = Ii{14-9};
343  let Inst{2-0} = Ii{8-6};
344  bits <5> Vss32;
345  let Inst{7-3} = Vss32{4-0};
346  bits <5> Rx32;
347  let Inst{20-16} = Rx32{4-0};
348}
349class Enc_041d7b : OpcodeHexagon {
350  bits <11> Ii;
351  let Inst{21-20} = Ii{10-9};
352  let Inst{7-1} = Ii{8-2};
353  bits <4> Rs16;
354  let Inst{19-16} = Rs16{3-0};
355  bits <5> n1;
356  let Inst{28-28} = n1{4-4};
357  let Inst{24-23} = n1{3-2};
358  let Inst{13-13} = n1{1-1};
359  let Inst{8-8} = n1{0-0};
360}
361class Enc_f44229 : OpcodeHexagon {
362  bits <7> Ii;
363  let Inst{13-13} = Ii{6-6};
364  let Inst{7-3} = Ii{5-1};
365  bits <2> Pv4;
366  let Inst{1-0} = Pv4{1-0};
367  bits <5> Rs32;
368  let Inst{20-16} = Rs32{4-0};
369  bits <3> Nt8;
370  let Inst{10-8} = Nt8{2-0};
371}
372class Enc_fc563d : OpcodeHexagon {
373  bits <5> Vuu32;
374  let Inst{20-16} = Vuu32{4-0};
375  bits <5> Vv32;
376  let Inst{12-8} = Vv32{4-0};
377  bits <5> Vd32;
378  let Inst{7-3} = Vd32{4-0};
379}
380class Enc_aad80c : OpcodeHexagon {
381  bits <5> Vuu32;
382  let Inst{12-8} = Vuu32{4-0};
383  bits <5> Rt32;
384  let Inst{20-16} = Rt32{4-0};
385  bits <5> Vdd32;
386  let Inst{4-0} = Vdd32{4-0};
387}
388class Enc_87c142 : OpcodeHexagon {
389  bits <7> Ii;
390  let Inst{8-4} = Ii{6-2};
391  bits <4> Rt16;
392  let Inst{3-0} = Rt16{3-0};
393}
394class Enc_86a14b : OpcodeHexagon {
395  bits <8> Ii;
396  let Inst{7-3} = Ii{7-3};
397  bits <3> Rdd8;
398  let Inst{2-0} = Rdd8{2-0};
399}
400class Enc_9a33d5 : OpcodeHexagon {
401  bits <7> Ii;
402  let Inst{6-3} = Ii{6-3};
403  bits <2> Pv4;
404  let Inst{1-0} = Pv4{1-0};
405  bits <5> Rtt32;
406  let Inst{12-8} = Rtt32{4-0};
407  bits <5> Rx32;
408  let Inst{20-16} = Rx32{4-0};
409}
410class Enc_a56825 : OpcodeHexagon {
411  bits <5> Rss32;
412  let Inst{20-16} = Rss32{4-0};
413  bits <5> Rtt32;
414  let Inst{12-8} = Rtt32{4-0};
415  bits <5> Rdd32;
416  let Inst{4-0} = Rdd32{4-0};
417}
418class Enc_9ea4cf : OpcodeHexagon {
419  bits <2> Ii;
420  let Inst{13-13} = Ii{1-1};
421  let Inst{6-6} = Ii{0-0};
422  bits <6> II;
423  let Inst{5-0} = II{5-0};
424  bits <5> Ru32;
425  let Inst{20-16} = Ru32{4-0};
426  bits <5> Rt32;
427  let Inst{12-8} = Rt32{4-0};
428}
429class Enc_ee5ed0 : OpcodeHexagon {
430  bits <4> Rs16;
431  let Inst{7-4} = Rs16{3-0};
432  bits <4> Rd16;
433  let Inst{3-0} = Rd16{3-0};
434  bits <2> n1;
435  let Inst{9-8} = n1{1-0};
436}
437class Enc_935d9b : OpcodeHexagon {
438  bits <5> Ii;
439  let Inst{6-3} = Ii{4-1};
440  bits <1> Mu2;
441  let Inst{13-13} = Mu2{0-0};
442  bits <5> Rt32;
443  let Inst{12-8} = Rt32{4-0};
444  bits <5> Rx32;
445  let Inst{20-16} = Rx32{4-0};
446}
447class Enc_61f0b0 : OpcodeHexagon {
448  bits <5> Rs32;
449  let Inst{20-16} = Rs32{4-0};
450  bits <5> Rt32;
451  let Inst{12-8} = Rt32{4-0};
452  bits <5> Rxx32;
453  let Inst{4-0} = Rxx32{4-0};
454}
455class Enc_bd6011 : OpcodeHexagon {
456  bits <5> Rt32;
457  let Inst{12-8} = Rt32{4-0};
458  bits <5> Rs32;
459  let Inst{20-16} = Rs32{4-0};
460  bits <5> Rd32;
461  let Inst{4-0} = Rd32{4-0};
462}
463class Enc_65d691 : OpcodeHexagon {
464  bits <2> Ps4;
465  let Inst{17-16} = Ps4{1-0};
466  bits <2> Pd4;
467  let Inst{1-0} = Pd4{1-0};
468}
469class Enc_e8c45e : OpcodeHexagon {
470  bits <7> Ii;
471  let Inst{13-13} = Ii{6-6};
472  let Inst{7-3} = Ii{5-1};
473  bits <2> Pv4;
474  let Inst{1-0} = Pv4{1-0};
475  bits <5> Rs32;
476  let Inst{20-16} = Rs32{4-0};
477  bits <5> Rt32;
478  let Inst{12-8} = Rt32{4-0};
479}
480class Enc_ca3887 : OpcodeHexagon {
481  bits <5> Rs32;
482  let Inst{20-16} = Rs32{4-0};
483  bits <5> Rt32;
484  let Inst{12-8} = Rt32{4-0};
485}
486class Enc_a94f3b : OpcodeHexagon {
487  bits <5> Rs32;
488  let Inst{20-16} = Rs32{4-0};
489  bits <5> Rt32;
490  let Inst{12-8} = Rt32{4-0};
491  bits <5> Rd32;
492  let Inst{4-0} = Rd32{4-0};
493  bits <2> Pe4;
494  let Inst{6-5} = Pe4{1-0};
495}
496class Enc_625deb : OpcodeHexagon {
497  bits <4> Ii;
498  let Inst{10-8} = Ii{3-1};
499  bits <4> Rs16;
500  let Inst{7-4} = Rs16{3-0};
501  bits <4> Rt16;
502  let Inst{3-0} = Rt16{3-0};
503}
504class Enc_1f5ba6 : OpcodeHexagon {
505  bits <4> Rd16;
506  let Inst{3-0} = Rd16{3-0};
507}
508class Enc_cd82bc : OpcodeHexagon {
509  bits <4> Ii;
510  let Inst{21-21} = Ii{3-3};
511  let Inst{7-5} = Ii{2-0};
512  bits <6> II;
513  let Inst{13-8} = II{5-0};
514  bits <5> Rs32;
515  let Inst{20-16} = Rs32{4-0};
516  bits <5> Rx32;
517  let Inst{4-0} = Rx32{4-0};
518}
519class Enc_399e12 : OpcodeHexagon {
520  bits <4> Rs16;
521  let Inst{7-4} = Rs16{3-0};
522  bits <3> Rdd8;
523  let Inst{2-0} = Rdd8{2-0};
524}
525class Enc_d7a65e : OpcodeHexagon {
526  bits <6> Ii;
527  let Inst{12-7} = Ii{5-0};
528  bits <6> II;
529  let Inst{13-13} = II{5-5};
530  let Inst{4-0} = II{4-0};
531  bits <2> Pv4;
532  let Inst{6-5} = Pv4{1-0};
533  bits <5> Rs32;
534  let Inst{20-16} = Rs32{4-0};
535}
536class Enc_607661 : OpcodeHexagon {
537  bits <6> Ii;
538  let Inst{12-7} = Ii{5-0};
539  bits <5> Rd32;
540  let Inst{4-0} = Rd32{4-0};
541}
542class Enc_6a5972 : OpcodeHexagon {
543  bits <11> Ii;
544  let Inst{21-20} = Ii{10-9};
545  let Inst{7-1} = Ii{8-2};
546  bits <4> Rs16;
547  let Inst{19-16} = Rs16{3-0};
548  bits <4> Rt16;
549  let Inst{11-8} = Rt16{3-0};
550}
551class Enc_ff3442 : OpcodeHexagon {
552  bits <4> Ii;
553  let Inst{13-13} = Ii{3-3};
554  let Inst{10-8} = Ii{2-0};
555  bits <5> Rt32;
556  let Inst{20-16} = Rt32{4-0};
557}
558class Enc_53dca9 : OpcodeHexagon {
559  bits <6> Ii;
560  let Inst{11-8} = Ii{5-2};
561  bits <4> Rs16;
562  let Inst{7-4} = Rs16{3-0};
563  bits <4> Rd16;
564  let Inst{3-0} = Rd16{3-0};
565}
566class Enc_27fd0e : OpcodeHexagon {
567  bits <6> Ii;
568  let Inst{8-5} = Ii{5-2};
569  bits <1> Mu2;
570  let Inst{13-13} = Mu2{0-0};
571  bits <5> Rd32;
572  let Inst{4-0} = Rd32{4-0};
573  bits <5> Rx32;
574  let Inst{20-16} = Rx32{4-0};
575}
576class Enc_93af4c : OpcodeHexagon {
577  bits <7> Ii;
578  let Inst{10-4} = Ii{6-0};
579  bits <4> Rx16;
580  let Inst{3-0} = Rx16{3-0};
581}
582class Enc_621fba : OpcodeHexagon {
583  bits <5> Rs32;
584  let Inst{20-16} = Rs32{4-0};
585  bits <5> Gd32;
586  let Inst{4-0} = Gd32{4-0};
587}
588class Enc_5bdd42 : OpcodeHexagon {
589  bits <7> Ii;
590  let Inst{8-5} = Ii{6-3};
591  bits <5> Rdd32;
592  let Inst{4-0} = Rdd32{4-0};
593  bits <5> Rx32;
594  let Inst{20-16} = Rx32{4-0};
595}
596class Enc_ad9bef : OpcodeHexagon {
597  bits <5> Vu32;
598  let Inst{12-8} = Vu32{4-0};
599  bits <5> Rtt32;
600  let Inst{20-16} = Rtt32{4-0};
601  bits <5> Vxx32;
602  let Inst{4-0} = Vxx32{4-0};
603}
604class Enc_71f1b4 : OpcodeHexagon {
605  bits <6> Ii;
606  let Inst{8-5} = Ii{5-2};
607  bits <5> Rdd32;
608  let Inst{4-0} = Rdd32{4-0};
609  bits <5> Rx32;
610  let Inst{20-16} = Rx32{4-0};
611}
612class Enc_14640c : OpcodeHexagon {
613  bits <11> Ii;
614  let Inst{21-20} = Ii{10-9};
615  let Inst{7-1} = Ii{8-2};
616  bits <4> Rs16;
617  let Inst{19-16} = Rs16{3-0};
618  bits <5> n1;
619  let Inst{28-28} = n1{4-4};
620  let Inst{24-22} = n1{3-1};
621  let Inst{13-13} = n1{0-0};
622}
623class Enc_2516bf : OpcodeHexagon {
624  bits <5> Vu32;
625  let Inst{20-16} = Vu32{4-0};
626  bits <5> Vd32;
627  let Inst{7-3} = Vd32{4-0};
628}
629class Enc_31db33 : OpcodeHexagon {
630  bits <2> Qt4;
631  let Inst{6-5} = Qt4{1-0};
632  bits <5> Vu32;
633  let Inst{12-8} = Vu32{4-0};
634  bits <5> Vv32;
635  let Inst{20-16} = Vv32{4-0};
636  bits <5> Vd32;
637  let Inst{4-0} = Vd32{4-0};
638}
639class Enc_65f095 : OpcodeHexagon {
640  bits <6> Ii;
641  let Inst{6-3} = Ii{5-2};
642  bits <2> Pv4;
643  let Inst{1-0} = Pv4{1-0};
644  bits <3> Nt8;
645  let Inst{10-8} = Nt8{2-0};
646  bits <5> Rx32;
647  let Inst{20-16} = Rx32{4-0};
648}
649class Enc_784502 : OpcodeHexagon {
650  bits <3> Ii;
651  let Inst{10-8} = Ii{2-0};
652  bits <2> Pv4;
653  let Inst{12-11} = Pv4{1-0};
654  bits <3> Os8;
655  let Inst{2-0} = Os8{2-0};
656  bits <5> Rx32;
657  let Inst{20-16} = Rx32{4-0};
658}
659class Enc_9a9d62 : OpcodeHexagon {
660  bits <1> Mu2;
661  let Inst{13-13} = Mu2{0-0};
662  bits <5> Rt32;
663  let Inst{12-8} = Rt32{4-0};
664  bits <5> Vs32;
665  let Inst{7-3} = Vs32{4-0};
666  bits <5> Rx32;
667  let Inst{20-16} = Rx32{4-0};
668}
669class Enc_3a81ac : OpcodeHexagon {
670  bits <1> Mu2;
671  let Inst{13-13} = Mu2{0-0};
672  bits <5> Vd32;
673  let Inst{7-3} = Vd32{4-0};
674  bits <5> Rx32;
675  let Inst{20-16} = Rx32{4-0};
676}
677class Enc_6413b6 : OpcodeHexagon {
678  bits <11> Ii;
679  let Inst{21-20} = Ii{10-9};
680  let Inst{7-1} = Ii{8-2};
681  bits <3> Ns8;
682  let Inst{18-16} = Ns8{2-0};
683  bits <5> n1;
684  let Inst{29-29} = n1{4-4};
685  let Inst{26-25} = n1{3-2};
686  let Inst{23-23} = n1{1-1};
687  let Inst{13-13} = n1{0-0};
688}
689class Enc_7a0ea6 : OpcodeHexagon {
690  bits <4> Rd16;
691  let Inst{3-0} = Rd16{3-0};
692  bits <1> n1;
693  let Inst{9-9} = n1{0-0};
694}
695class Enc_84bff1 : OpcodeHexagon {
696  bits <2> Ii;
697  let Inst{13-13} = Ii{1-1};
698  let Inst{7-7} = Ii{0-0};
699  bits <5> Rs32;
700  let Inst{20-16} = Rs32{4-0};
701  bits <5> Rt32;
702  let Inst{12-8} = Rt32{4-0};
703  bits <5> Rdd32;
704  let Inst{4-0} = Rdd32{4-0};
705}
706class Enc_74aef2 : OpcodeHexagon {
707  bits <4> Ii;
708  let Inst{8-5} = Ii{3-0};
709  bits <1> Mu2;
710  let Inst{13-13} = Mu2{0-0};
711  bits <5> Ryy32;
712  let Inst{4-0} = Ryy32{4-0};
713  bits <5> Rx32;
714  let Inst{20-16} = Rx32{4-0};
715}
716class Enc_78e566 : OpcodeHexagon {
717  bits <2> Pt4;
718  let Inst{9-8} = Pt4{1-0};
719  bits <5> Rdd32;
720  let Inst{4-0} = Rdd32{4-0};
721}
722class Enc_437f33 : OpcodeHexagon {
723  bits <5> Rs32;
724  let Inst{20-16} = Rs32{4-0};
725  bits <5> Rt32;
726  let Inst{12-8} = Rt32{4-0};
727  bits <2> Pu4;
728  let Inst{6-5} = Pu4{1-0};
729  bits <5> Rx32;
730  let Inst{4-0} = Rx32{4-0};
731}
732class Enc_0527db : OpcodeHexagon {
733  bits <4> Rs16;
734  let Inst{7-4} = Rs16{3-0};
735  bits <4> Rx16;
736  let Inst{3-0} = Rx16{3-0};
737}
738class Enc_420cf3 : OpcodeHexagon {
739  bits <6> Ii;
740  let Inst{22-21} = Ii{5-4};
741  let Inst{13-13} = Ii{3-3};
742  let Inst{7-5} = Ii{2-0};
743  bits <5> Ru32;
744  let Inst{4-0} = Ru32{4-0};
745  bits <5> Rs32;
746  let Inst{20-16} = Rs32{4-0};
747  bits <5> Rd32;
748  let Inst{12-8} = Rd32{4-0};
749}
750class Enc_e39bb2 : OpcodeHexagon {
751  bits <6> Ii;
752  let Inst{9-4} = Ii{5-0};
753  bits <4> Rd16;
754  let Inst{3-0} = Rd16{3-0};
755}
756class Enc_7db2f8 : OpcodeHexagon {
757  bits <5> Vu32;
758  let Inst{13-9} = Vu32{4-0};
759  bits <5> Vv32;
760  let Inst{8-4} = Vv32{4-0};
761  bits <4> Vdd16;
762  let Inst{3-0} = Vdd16{3-0};
763  bits <5> Rx32;
764  let Inst{20-16} = Rx32{4-0};
765}
766class Enc_1b64fb : OpcodeHexagon {
767  bits <16> Ii;
768  let Inst{26-25} = Ii{15-14};
769  let Inst{20-16} = Ii{13-9};
770  let Inst{13-13} = Ii{8-8};
771  let Inst{7-0} = Ii{7-0};
772  bits <5> Rt32;
773  let Inst{12-8} = Rt32{4-0};
774}
775class Enc_c6220b : OpcodeHexagon {
776  bits <2> Ii;
777  let Inst{13-13} = Ii{1-1};
778  let Inst{7-7} = Ii{0-0};
779  bits <5> Rs32;
780  let Inst{20-16} = Rs32{4-0};
781  bits <5> Ru32;
782  let Inst{12-8} = Ru32{4-0};
783  bits <3> Nt8;
784  let Inst{2-0} = Nt8{2-0};
785}
786class Enc_322e1b : OpcodeHexagon {
787  bits <6> Ii;
788  let Inst{22-21} = Ii{5-4};
789  let Inst{13-13} = Ii{3-3};
790  let Inst{7-5} = Ii{2-0};
791  bits <6> II;
792  let Inst{23-23} = II{5-5};
793  let Inst{4-0} = II{4-0};
794  bits <5> Rs32;
795  let Inst{20-16} = Rs32{4-0};
796  bits <5> Rd32;
797  let Inst{12-8} = Rd32{4-0};
798}
799class Enc_989021 : OpcodeHexagon {
800  bits <5> Rt32;
801  let Inst{20-16} = Rt32{4-0};
802  bits <5> Vy32;
803  let Inst{12-8} = Vy32{4-0};
804  bits <5> Vx32;
805  let Inst{4-0} = Vx32{4-0};
806}
807class Enc_178717 : OpcodeHexagon {
808  bits <11> Ii;
809  let Inst{21-20} = Ii{10-9};
810  let Inst{7-1} = Ii{8-2};
811  bits <4> Rs16;
812  let Inst{19-16} = Rs16{3-0};
813  bits <6> n1;
814  let Inst{28-28} = n1{5-5};
815  let Inst{25-23} = n1{4-2};
816  let Inst{13-13} = n1{1-1};
817  let Inst{8-8} = n1{0-0};
818}
819class Enc_78cbf0 : OpcodeHexagon {
820  bits <18> Ii;
821  let Inst{26-25} = Ii{17-16};
822  let Inst{20-16} = Ii{15-11};
823  let Inst{13-13} = Ii{10-10};
824  let Inst{7-0} = Ii{9-2};
825  bits <3> Nt8;
826  let Inst{10-8} = Nt8{2-0};
827}
828class Enc_052c7d : OpcodeHexagon {
829  bits <5> Ii;
830  let Inst{6-3} = Ii{4-1};
831  bits <5> Rt32;
832  let Inst{12-8} = Rt32{4-0};
833  bits <5> Rx32;
834  let Inst{20-16} = Rx32{4-0};
835}
836class Enc_fcf7a7 : OpcodeHexagon {
837  bits <5> Rss32;
838  let Inst{20-16} = Rss32{4-0};
839  bits <5> Rtt32;
840  let Inst{12-8} = Rtt32{4-0};
841  bits <2> Pd4;
842  let Inst{1-0} = Pd4{1-0};
843}
844class Enc_2c3281 : OpcodeHexagon {
845  bits <5> Vdd32;
846  let Inst{7-3} = Vdd32{4-0};
847}
848class Enc_55355c : OpcodeHexagon {
849  bits <2> Ii;
850  let Inst{13-13} = Ii{1-1};
851  let Inst{7-7} = Ii{0-0};
852  bits <5> Rs32;
853  let Inst{20-16} = Rs32{4-0};
854  bits <5> Ru32;
855  let Inst{12-8} = Ru32{4-0};
856  bits <5> Rtt32;
857  let Inst{4-0} = Rtt32{4-0};
858}
859class Enc_211aaa : OpcodeHexagon {
860  bits <11> Ii;
861  let Inst{26-25} = Ii{10-9};
862  let Inst{13-5} = Ii{8-0};
863  bits <5> Rs32;
864  let Inst{20-16} = Rs32{4-0};
865  bits <5> Rd32;
866  let Inst{4-0} = Rd32{4-0};
867}
868class Enc_6185fe : OpcodeHexagon {
869  bits <2> Ii;
870  let Inst{13-13} = Ii{1-1};
871  let Inst{7-7} = Ii{0-0};
872  bits <6> II;
873  let Inst{11-8} = II{5-2};
874  let Inst{6-5} = II{1-0};
875  bits <5> Rt32;
876  let Inst{20-16} = Rt32{4-0};
877  bits <5> Rdd32;
878  let Inst{4-0} = Rdd32{4-0};
879}
880class Enc_cd4705 : OpcodeHexagon {
881  bits <3> Ii;
882  let Inst{7-5} = Ii{2-0};
883  bits <5> Vu32;
884  let Inst{12-8} = Vu32{4-0};
885  bits <5> Vv32;
886  let Inst{20-16} = Vv32{4-0};
887  bits <5> Vx32;
888  let Inst{4-0} = Vx32{4-0};
889}
890class Enc_2ebe3b : OpcodeHexagon {
891  bits <1> Mu2;
892  let Inst{13-13} = Mu2{0-0};
893  bits <5> Vd32;
894  let Inst{4-0} = Vd32{4-0};
895  bits <5> Rx32;
896  let Inst{20-16} = Rx32{4-0};
897}
898class Enc_3d5b28 : OpcodeHexagon {
899  bits <5> Rss32;
900  let Inst{20-16} = Rss32{4-0};
901  bits <5> Rt32;
902  let Inst{12-8} = Rt32{4-0};
903  bits <5> Rd32;
904  let Inst{4-0} = Rd32{4-0};
905}
906class Enc_5ab2be : OpcodeHexagon {
907  bits <5> Rs32;
908  let Inst{20-16} = Rs32{4-0};
909  bits <5> Rt32;
910  let Inst{12-8} = Rt32{4-0};
911  bits <5> Rd32;
912  let Inst{4-0} = Rd32{4-0};
913}
914class Enc_fef969 : OpcodeHexagon {
915  bits <6> Ii;
916  let Inst{20-16} = Ii{5-1};
917  let Inst{5-5} = Ii{0-0};
918  bits <5> Rt32;
919  let Inst{12-8} = Rt32{4-0};
920  bits <5> Rd32;
921  let Inst{4-0} = Rd32{4-0};
922}
923class Enc_b2ffce : OpcodeHexagon {
924  bits <5> Vd32;
925  let Inst{7-3} = Vd32{4-0};
926}
927class Enc_63eaeb : OpcodeHexagon {
928  bits <2> Ii;
929  let Inst{1-0} = Ii{1-0};
930  bits <4> Rs16;
931  let Inst{7-4} = Rs16{3-0};
932}
933class Enc_95441f : OpcodeHexagon {
934  bits <5> Vu32;
935  let Inst{12-8} = Vu32{4-0};
936  bits <5> Vv32;
937  let Inst{20-16} = Vv32{4-0};
938  bits <2> Qd4;
939  let Inst{1-0} = Qd4{1-0};
940}
941class Enc_372c9d : OpcodeHexagon {
942  bits <2> Pv4;
943  let Inst{12-11} = Pv4{1-0};
944  bits <1> Mu2;
945  let Inst{13-13} = Mu2{0-0};
946  bits <3> Os8;
947  let Inst{2-0} = Os8{2-0};
948  bits <5> Rx32;
949  let Inst{20-16} = Rx32{4-0};
950}
951class Enc_9e9047 : OpcodeHexagon {
952  bits <2> Pt4;
953  let Inst{9-8} = Pt4{1-0};
954  bits <5> Rs32;
955  let Inst{20-16} = Rs32{4-0};
956}
957class Enc_4dff07 : OpcodeHexagon {
958  bits <2> Qv4;
959  let Inst{12-11} = Qv4{1-0};
960  bits <1> Mu2;
961  let Inst{13-13} = Mu2{0-0};
962  bits <5> Vs32;
963  let Inst{4-0} = Vs32{4-0};
964  bits <5> Rx32;
965  let Inst{20-16} = Rx32{4-0};
966}
967class Enc_04c959 : OpcodeHexagon {
968  bits <2> Ii;
969  let Inst{13-13} = Ii{1-1};
970  let Inst{7-7} = Ii{0-0};
971  bits <6> II;
972  let Inst{11-8} = II{5-2};
973  let Inst{6-5} = II{1-0};
974  bits <5> Rt32;
975  let Inst{20-16} = Rt32{4-0};
976  bits <5> Ryy32;
977  let Inst{4-0} = Ryy32{4-0};
978}
979class Enc_b62ef7 : OpcodeHexagon {
980  bits <3> Ii;
981  let Inst{10-8} = Ii{2-0};
982  bits <5> Vs32;
983  let Inst{4-0} = Vs32{4-0};
984  bits <5> Rx32;
985  let Inst{20-16} = Rx32{4-0};
986}
987class Enc_2b518f : OpcodeHexagon {
988  bits <32> Ii;
989  let Inst{27-16} = Ii{31-20};
990  let Inst{13-0} = Ii{19-6};
991}
992class Enc_b388cf : OpcodeHexagon {
993  bits <5> Ii;
994  let Inst{12-8} = Ii{4-0};
995  bits <5> II;
996  let Inst{22-21} = II{4-3};
997  let Inst{7-5} = II{2-0};
998  bits <5> Rs32;
999  let Inst{20-16} = Rs32{4-0};
1000  bits <5> Rd32;
1001  let Inst{4-0} = Rd32{4-0};
1002}
1003class Enc_880793 : OpcodeHexagon {
1004  bits <3> Qt8;
1005  let Inst{2-0} = Qt8{2-0};
1006  bits <5> Vu32;
1007  let Inst{20-16} = Vu32{4-0};
1008  bits <5> Vv32;
1009  let Inst{12-8} = Vv32{4-0};
1010  bits <5> Vdd32;
1011  let Inst{7-3} = Vdd32{4-0};
1012}
1013class Enc_ad1c74 : OpcodeHexagon {
1014  bits <11> Ii;
1015  let Inst{21-20} = Ii{10-9};
1016  let Inst{7-1} = Ii{8-2};
1017  bits <4> Rs16;
1018  let Inst{19-16} = Rs16{3-0};
1019}
1020class Enc_74d4e5 : OpcodeHexagon {
1021  bits <1> Mu2;
1022  let Inst{13-13} = Mu2{0-0};
1023  bits <5> Rd32;
1024  let Inst{4-0} = Rd32{4-0};
1025  bits <5> Rx32;
1026  let Inst{20-16} = Rx32{4-0};
1027}
1028class Enc_c90aca : OpcodeHexagon {
1029  bits <8> Ii;
1030  let Inst{12-5} = Ii{7-0};
1031  bits <5> Rs32;
1032  let Inst{20-16} = Rs32{4-0};
1033  bits <5> Rx32;
1034  let Inst{4-0} = Rx32{4-0};
1035}
1036class Enc_222336 : OpcodeHexagon {
1037  bits <4> Ii;
1038  let Inst{8-5} = Ii{3-0};
1039  bits <5> Rd32;
1040  let Inst{4-0} = Rd32{4-0};
1041  bits <5> Rx32;
1042  let Inst{20-16} = Rx32{4-0};
1043}
1044class Enc_5e87ce : OpcodeHexagon {
1045  bits <16> Ii;
1046  let Inst{23-22} = Ii{15-14};
1047  let Inst{20-16} = Ii{13-9};
1048  let Inst{13-5} = Ii{8-0};
1049  bits <5> Rd32;
1050  let Inst{4-0} = Rd32{4-0};
1051}
1052class Enc_158beb : OpcodeHexagon {
1053  bits <2> Qs4;
1054  let Inst{6-5} = Qs4{1-0};
1055  bits <5> Rt32;
1056  let Inst{20-16} = Rt32{4-0};
1057  bits <1> Mu2;
1058  let Inst{13-13} = Mu2{0-0};
1059  bits <5> Vv32;
1060  let Inst{4-0} = Vv32{4-0};
1061}
1062class Enc_f7ea77 : OpcodeHexagon {
1063  bits <11> Ii;
1064  let Inst{21-20} = Ii{10-9};
1065  let Inst{7-1} = Ii{8-2};
1066  bits <3> Ns8;
1067  let Inst{18-16} = Ns8{2-0};
1068  bits <4> n1;
1069  let Inst{29-29} = n1{3-3};
1070  let Inst{26-25} = n1{2-1};
1071  let Inst{13-13} = n1{0-0};
1072}
1073class Enc_245865 : OpcodeHexagon {
1074  bits <5> Vu32;
1075  let Inst{12-8} = Vu32{4-0};
1076  bits <5> Vv32;
1077  let Inst{23-19} = Vv32{4-0};
1078  bits <3> Rt8;
1079  let Inst{18-16} = Rt8{2-0};
1080  bits <5> Vx32;
1081  let Inst{4-0} = Vx32{4-0};
1082}
1083class Enc_88d4d9 : OpcodeHexagon {
1084  bits <2> Pu4;
1085  let Inst{9-8} = Pu4{1-0};
1086  bits <5> Rs32;
1087  let Inst{20-16} = Rs32{4-0};
1088}
1089class Enc_c0cdde : OpcodeHexagon {
1090  bits <9> Ii;
1091  let Inst{13-5} = Ii{8-0};
1092  bits <5> Rs32;
1093  let Inst{20-16} = Rs32{4-0};
1094  bits <2> Pd4;
1095  let Inst{1-0} = Pd4{1-0};
1096}
1097class Enc_226535 : OpcodeHexagon {
1098  bits <8> Ii;
1099  let Inst{12-7} = Ii{7-2};
1100  bits <5> Rs32;
1101  let Inst{20-16} = Rs32{4-0};
1102  bits <5> Rt32;
1103  let Inst{4-0} = Rt32{4-0};
1104}
1105class Enc_96f0fd : OpcodeHexagon {
1106  bits <5> Rt32;
1107  let Inst{20-16} = Rt32{4-0};
1108  bits <5> Vx32;
1109  let Inst{7-3} = Vx32{4-0};
1110  bits <3> Qdd8;
1111  let Inst{2-0} = Qdd8{2-0};
1112}
1113class Enc_31aa6a : OpcodeHexagon {
1114  bits <5> Ii;
1115  let Inst{6-3} = Ii{4-1};
1116  bits <2> Pv4;
1117  let Inst{1-0} = Pv4{1-0};
1118  bits <3> Nt8;
1119  let Inst{10-8} = Nt8{2-0};
1120  bits <5> Rx32;
1121  let Inst{20-16} = Rx32{4-0};
1122}
1123class Enc_932b58 : OpcodeHexagon {
1124  bits <5> Vu32;
1125  let Inst{12-8} = Vu32{4-0};
1126  bits <5> Rt32;
1127  let Inst{20-16} = Rt32{4-0};
1128}
1129class Enc_397f23 : OpcodeHexagon {
1130  bits <8> Ii;
1131  let Inst{13-13} = Ii{7-7};
1132  let Inst{7-3} = Ii{6-2};
1133  bits <2> Pv4;
1134  let Inst{1-0} = Pv4{1-0};
1135  bits <5> Rs32;
1136  let Inst{20-16} = Rs32{4-0};
1137  bits <5> Rt32;
1138  let Inst{12-8} = Rt32{4-0};
1139}
1140class Enc_865390 : OpcodeHexagon {
1141  bits <3> Ii;
1142  let Inst{10-8} = Ii{2-0};
1143  bits <2> Pv4;
1144  let Inst{12-11} = Pv4{1-0};
1145  bits <5> Vs32;
1146  let Inst{4-0} = Vs32{4-0};
1147  bits <5> Rx32;
1148  let Inst{20-16} = Rx32{4-0};
1149}
1150class Enc_98c0b8 : OpcodeHexagon {
1151  bits <2> Ii;
1152  let Inst{13-13} = Ii{1-1};
1153  let Inst{7-7} = Ii{0-0};
1154  bits <2> Pv4;
1155  let Inst{6-5} = Pv4{1-0};
1156  bits <5> Rs32;
1157  let Inst{20-16} = Rs32{4-0};
1158  bits <5> Rt32;
1159  let Inst{12-8} = Rt32{4-0};
1160  bits <5> Rdd32;
1161  let Inst{4-0} = Rdd32{4-0};
1162}
1163class Enc_bfbf03 : OpcodeHexagon {
1164  bits <2> Qs4;
1165  let Inst{9-8} = Qs4{1-0};
1166  bits <2> Qd4;
1167  let Inst{1-0} = Qd4{1-0};
1168}
1169class Enc_ecbcc8 : OpcodeHexagon {
1170  bits <5> Rs32;
1171  let Inst{20-16} = Rs32{4-0};
1172}
1173class Enc_f5e933 : OpcodeHexagon {
1174  bits <2> Ps4;
1175  let Inst{17-16} = Ps4{1-0};
1176  bits <5> Rd32;
1177  let Inst{4-0} = Rd32{4-0};
1178}
1179class Enc_3fc427 : OpcodeHexagon {
1180  bits <5> Vu32;
1181  let Inst{12-8} = Vu32{4-0};
1182  bits <5> Vv32;
1183  let Inst{20-16} = Vv32{4-0};
1184  bits <5> Vxx32;
1185  let Inst{4-0} = Vxx32{4-0};
1186}
1187class Enc_01d3d0 : OpcodeHexagon {
1188  bits <5> Vu32;
1189  let Inst{12-8} = Vu32{4-0};
1190  bits <5> Rt32;
1191  let Inst{20-16} = Rt32{4-0};
1192  bits <5> Vdd32;
1193  let Inst{4-0} = Vdd32{4-0};
1194}
1195class Enc_3126d7 : OpcodeHexagon {
1196  bits <5> Vu32;
1197  let Inst{20-16} = Vu32{4-0};
1198  bits <5> Vv32;
1199  let Inst{12-8} = Vv32{4-0};
1200  bits <5> Vdd32;
1201  let Inst{7-3} = Vdd32{4-0};
1202}
1203class Enc_b0e9d8 : OpcodeHexagon {
1204  bits <10> Ii;
1205  let Inst{21-21} = Ii{9-9};
1206  let Inst{13-5} = Ii{8-0};
1207  bits <5> Rs32;
1208  let Inst{20-16} = Rs32{4-0};
1209  bits <5> Rx32;
1210  let Inst{4-0} = Rx32{4-0};
1211}
1212class Enc_3694bd : OpcodeHexagon {
1213  bits <11> Ii;
1214  let Inst{21-20} = Ii{10-9};
1215  let Inst{7-1} = Ii{8-2};
1216  bits <3> Ns8;
1217  let Inst{18-16} = Ns8{2-0};
1218  bits <5> n1;
1219  let Inst{29-29} = n1{4-4};
1220  let Inst{26-25} = n1{3-2};
1221  let Inst{23-22} = n1{1-0};
1222}
1223class Enc_a42857 : OpcodeHexagon {
1224  bits <11> Ii;
1225  let Inst{21-20} = Ii{10-9};
1226  let Inst{7-1} = Ii{8-2};
1227  bits <4> Rs16;
1228  let Inst{19-16} = Rs16{3-0};
1229  bits <5> n1;
1230  let Inst{28-28} = n1{4-4};
1231  let Inst{24-22} = n1{3-1};
1232  let Inst{8-8} = n1{0-0};
1233}
1234class Enc_b7fad3 : OpcodeHexagon {
1235  bits <2> Pv4;
1236  let Inst{9-8} = Pv4{1-0};
1237  bits <5> Rs32;
1238  let Inst{20-16} = Rs32{4-0};
1239  bits <5> Rdd32;
1240  let Inst{4-0} = Rdd32{4-0};
1241}
1242class Enc_223005 : OpcodeHexagon {
1243  bits <6> Ii;
1244  let Inst{6-3} = Ii{5-2};
1245  bits <3> Nt8;
1246  let Inst{10-8} = Nt8{2-0};
1247  bits <5> Rx32;
1248  let Inst{20-16} = Rx32{4-0};
1249}
1250class Enc_9e4c3f : OpcodeHexagon {
1251  bits <6> II;
1252  let Inst{13-8} = II{5-0};
1253  bits <11> Ii;
1254  let Inst{21-20} = Ii{10-9};
1255  let Inst{7-1} = Ii{8-2};
1256  bits <4> Rd16;
1257  let Inst{19-16} = Rd16{3-0};
1258}
1259class Enc_8b8d61 : OpcodeHexagon {
1260  bits <6> Ii;
1261  let Inst{22-21} = Ii{5-4};
1262  let Inst{13-13} = Ii{3-3};
1263  let Inst{7-5} = Ii{2-0};
1264  bits <5> Rs32;
1265  let Inst{20-16} = Rs32{4-0};
1266  bits <5> Ru32;
1267  let Inst{4-0} = Ru32{4-0};
1268  bits <5> Rd32;
1269  let Inst{12-8} = Rd32{4-0};
1270}
1271class Enc_88c16c : OpcodeHexagon {
1272  bits <5> Rss32;
1273  let Inst{20-16} = Rss32{4-0};
1274  bits <5> Rtt32;
1275  let Inst{12-8} = Rtt32{4-0};
1276  bits <5> Rxx32;
1277  let Inst{4-0} = Rxx32{4-0};
1278}
1279class Enc_e7408c : OpcodeHexagon {
1280  bits <6> Sss64;
1281  let Inst{21-16} = Sss64{5-0};
1282  bits <5> Rdd32;
1283  let Inst{4-0} = Rdd32{4-0};
1284}
1285class Enc_770858 : OpcodeHexagon {
1286  bits <2> Ps4;
1287  let Inst{6-5} = Ps4{1-0};
1288  bits <5> Vu32;
1289  let Inst{12-8} = Vu32{4-0};
1290  bits <5> Vd32;
1291  let Inst{4-0} = Vd32{4-0};
1292}
1293class Enc_bd811a : OpcodeHexagon {
1294  bits <5> Rs32;
1295  let Inst{20-16} = Rs32{4-0};
1296  bits <5> Cd32;
1297  let Inst{4-0} = Cd32{4-0};
1298}
1299class Enc_b05839 : OpcodeHexagon {
1300  bits <7> Ii;
1301  let Inst{8-5} = Ii{6-3};
1302  bits <1> Mu2;
1303  let Inst{13-13} = Mu2{0-0};
1304  bits <5> Rdd32;
1305  let Inst{4-0} = Rdd32{4-0};
1306  bits <5> Rx32;
1307  let Inst{20-16} = Rx32{4-0};
1308}
1309class Enc_bc03e5 : OpcodeHexagon {
1310  bits <17> Ii;
1311  let Inst{26-25} = Ii{16-15};
1312  let Inst{20-16} = Ii{14-10};
1313  let Inst{13-13} = Ii{9-9};
1314  let Inst{7-0} = Ii{8-1};
1315  bits <3> Nt8;
1316  let Inst{10-8} = Nt8{2-0};
1317}
1318class Enc_412ff0 : OpcodeHexagon {
1319  bits <5> Rss32;
1320  let Inst{20-16} = Rss32{4-0};
1321  bits <5> Ru32;
1322  let Inst{4-0} = Ru32{4-0};
1323  bits <5> Rxx32;
1324  let Inst{12-8} = Rxx32{4-0};
1325}
1326class Enc_8e9fbd : OpcodeHexagon {
1327  bits <5> Vu32;
1328  let Inst{20-16} = Vu32{4-0};
1329  bits <3> Rt8;
1330  let Inst{2-0} = Rt8{2-0};
1331  bits <5> Vd32;
1332  let Inst{7-3} = Vd32{4-0};
1333  bits <5> Vy32;
1334  let Inst{12-8} = Vy32{4-0};
1335}
1336class Enc_c9a18e : OpcodeHexagon {
1337  bits <11> Ii;
1338  let Inst{21-20} = Ii{10-9};
1339  let Inst{7-1} = Ii{8-2};
1340  bits <3> Ns8;
1341  let Inst{18-16} = Ns8{2-0};
1342  bits <5> Rt32;
1343  let Inst{12-8} = Rt32{4-0};
1344}
1345class Enc_be32a5 : OpcodeHexagon {
1346  bits <5> Rs32;
1347  let Inst{20-16} = Rs32{4-0};
1348  bits <5> Rt32;
1349  let Inst{12-8} = Rt32{4-0};
1350  bits <5> Rdd32;
1351  let Inst{4-0} = Rdd32{4-0};
1352}
1353class Enc_e6abcf : OpcodeHexagon {
1354  bits <5> Rs32;
1355  let Inst{20-16} = Rs32{4-0};
1356  bits <5> Rtt32;
1357  let Inst{12-8} = Rtt32{4-0};
1358}
1359class Enc_6339d5 : OpcodeHexagon {
1360  bits <2> Ii;
1361  let Inst{13-13} = Ii{1-1};
1362  let Inst{7-7} = Ii{0-0};
1363  bits <2> Pv4;
1364  let Inst{6-5} = Pv4{1-0};
1365  bits <5> Rs32;
1366  let Inst{20-16} = Rs32{4-0};
1367  bits <5> Ru32;
1368  let Inst{12-8} = Ru32{4-0};
1369  bits <5> Rt32;
1370  let Inst{4-0} = Rt32{4-0};
1371}
1372class Enc_d6990d : OpcodeHexagon {
1373  bits <5> Vuu32;
1374  let Inst{12-8} = Vuu32{4-0};
1375  bits <5> Rt32;
1376  let Inst{20-16} = Rt32{4-0};
1377  bits <5> Vxx32;
1378  let Inst{4-0} = Vxx32{4-0};
1379}
1380class Enc_6c4697 : OpcodeHexagon {
1381  bits <1> Mu2;
1382  let Inst{13-13} = Mu2{0-0};
1383  bits <5> Rt32;
1384  let Inst{12-8} = Rt32{4-0};
1385  bits <5> Vd32;
1386  let Inst{7-3} = Vd32{4-0};
1387  bits <5> Rx32;
1388  let Inst{20-16} = Rx32{4-0};
1389}
1390class Enc_6c9440 : OpcodeHexagon {
1391  bits <10> Ii;
1392  let Inst{21-21} = Ii{9-9};
1393  let Inst{13-5} = Ii{8-0};
1394  bits <5> Rd32;
1395  let Inst{4-0} = Rd32{4-0};
1396}
1397class Enc_0d8adb : OpcodeHexagon {
1398  bits <8> Ii;
1399  let Inst{12-5} = Ii{7-0};
1400  bits <5> Rss32;
1401  let Inst{20-16} = Rss32{4-0};
1402  bits <2> Pd4;
1403  let Inst{1-0} = Pd4{1-0};
1404}
1405class Enc_50e578 : OpcodeHexagon {
1406  bits <5> Vu32;
1407  let Inst{12-8} = Vu32{4-0};
1408  bits <5> Rs32;
1409  let Inst{20-16} = Rs32{4-0};
1410  bits <5> Rd32;
1411  let Inst{4-0} = Rd32{4-0};
1412}
1413class Enc_1cf4ca : OpcodeHexagon {
1414  bits <6> Ii;
1415  let Inst{17-16} = Ii{5-4};
1416  let Inst{6-3} = Ii{3-0};
1417  bits <2> Pv4;
1418  let Inst{1-0} = Pv4{1-0};
1419  bits <5> Rt32;
1420  let Inst{12-8} = Rt32{4-0};
1421}
1422class Enc_48b75f : OpcodeHexagon {
1423  bits <5> Rs32;
1424  let Inst{20-16} = Rs32{4-0};
1425  bits <2> Pd4;
1426  let Inst{1-0} = Pd4{1-0};
1427}
1428class Enc_b97f71 : OpcodeHexagon {
1429  bits <6> Ii;
1430  let Inst{8-5} = Ii{5-2};
1431  bits <2> Pt4;
1432  let Inst{10-9} = Pt4{1-0};
1433  bits <5> Rd32;
1434  let Inst{4-0} = Rd32{4-0};
1435  bits <5> Rx32;
1436  let Inst{20-16} = Rx32{4-0};
1437}
1438class Enc_9d1247 : OpcodeHexagon {
1439  bits <7> Ii;
1440  let Inst{8-5} = Ii{6-3};
1441  bits <2> Pt4;
1442  let Inst{10-9} = Pt4{1-0};
1443  bits <5> Rdd32;
1444  let Inst{4-0} = Rdd32{4-0};
1445  bits <5> Rx32;
1446  let Inst{20-16} = Rx32{4-0};
1447}
1448class Enc_f4413a : OpcodeHexagon {
1449  bits <4> Ii;
1450  let Inst{8-5} = Ii{3-0};
1451  bits <2> Pt4;
1452  let Inst{10-9} = Pt4{1-0};
1453  bits <5> Rd32;
1454  let Inst{4-0} = Rd32{4-0};
1455  bits <5> Rx32;
1456  let Inst{20-16} = Rx32{4-0};
1457}
1458class Enc_f7430e : OpcodeHexagon {
1459  bits <4> Ii;
1460  let Inst{13-13} = Ii{3-3};
1461  let Inst{10-8} = Ii{2-0};
1462  bits <2> Pv4;
1463  let Inst{12-11} = Pv4{1-0};
1464  bits <5> Rt32;
1465  let Inst{20-16} = Rt32{4-0};
1466  bits <3> Os8;
1467  let Inst{2-0} = Os8{2-0};
1468}
1469class Enc_e7581c : OpcodeHexagon {
1470  bits <5> Vu32;
1471  let Inst{12-8} = Vu32{4-0};
1472  bits <5> Vd32;
1473  let Inst{4-0} = Vd32{4-0};
1474}
1475class Enc_2301d6 : OpcodeHexagon {
1476  bits <6> Ii;
1477  let Inst{20-16} = Ii{5-1};
1478  let Inst{8-8} = Ii{0-0};
1479  bits <2> Pt4;
1480  let Inst{10-9} = Pt4{1-0};
1481  bits <5> Rd32;
1482  let Inst{4-0} = Rd32{4-0};
1483}
1484class Enc_c31910 : OpcodeHexagon {
1485  bits <8> Ii;
1486  let Inst{23-21} = Ii{7-5};
1487  let Inst{13-13} = Ii{4-4};
1488  let Inst{7-5} = Ii{3-1};
1489  let Inst{3-3} = Ii{0-0};
1490  bits <5> II;
1491  let Inst{12-8} = II{4-0};
1492  bits <5> Rx32;
1493  let Inst{20-16} = Rx32{4-0};
1494}
1495class Enc_2f2f04 : OpcodeHexagon {
1496  bits <1> Ii;
1497  let Inst{5-5} = Ii{0-0};
1498  bits <5> Vuu32;
1499  let Inst{12-8} = Vuu32{4-0};
1500  bits <5> Rt32;
1501  let Inst{20-16} = Rt32{4-0};
1502  bits <5> Vdd32;
1503  let Inst{4-0} = Vdd32{4-0};
1504}
1505class Enc_8d8a30 : OpcodeHexagon {
1506  bits <4> Ii;
1507  let Inst{13-13} = Ii{3-3};
1508  let Inst{10-8} = Ii{2-0};
1509  bits <2> Pv4;
1510  let Inst{12-11} = Pv4{1-0};
1511  bits <5> Rt32;
1512  let Inst{20-16} = Rt32{4-0};
1513  bits <5> Vd32;
1514  let Inst{4-0} = Vd32{4-0};
1515}
1516class Enc_2d7491 : OpcodeHexagon {
1517  bits <13> Ii;
1518  let Inst{26-25} = Ii{12-11};
1519  let Inst{13-5} = Ii{10-2};
1520  bits <5> Rs32;
1521  let Inst{20-16} = Rs32{4-0};
1522  bits <5> Rdd32;
1523  let Inst{4-0} = Rdd32{4-0};
1524}
1525class Enc_a803e0 : OpcodeHexagon {
1526  bits <7> Ii;
1527  let Inst{12-7} = Ii{6-1};
1528  bits <8> II;
1529  let Inst{13-13} = II{7-7};
1530  let Inst{6-0} = II{6-0};
1531  bits <5> Rs32;
1532  let Inst{20-16} = Rs32{4-0};
1533}
1534class Enc_fde0e3 : OpcodeHexagon {
1535  bits <5> Rtt32;
1536  let Inst{20-16} = Rtt32{4-0};
1537  bits <5> Vd32;
1538  let Inst{7-3} = Vd32{4-0};
1539}
1540class Enc_45364e : OpcodeHexagon {
1541  bits <5> Vu32;
1542  let Inst{12-8} = Vu32{4-0};
1543  bits <5> Vv32;
1544  let Inst{20-16} = Vv32{4-0};
1545  bits <5> Vd32;
1546  let Inst{4-0} = Vd32{4-0};
1547}
1548class Enc_b909d2 : OpcodeHexagon {
1549  bits <11> Ii;
1550  let Inst{21-20} = Ii{10-9};
1551  let Inst{7-1} = Ii{8-2};
1552  bits <4> Rs16;
1553  let Inst{19-16} = Rs16{3-0};
1554  bits <7> n1;
1555  let Inst{28-28} = n1{6-6};
1556  let Inst{25-22} = n1{5-2};
1557  let Inst{13-13} = n1{1-1};
1558  let Inst{8-8} = n1{0-0};
1559}
1560class Enc_790d6e : OpcodeHexagon {
1561  bits <5> Rt32;
1562  let Inst{20-16} = Rt32{4-0};
1563  bits <5> Vd32;
1564  let Inst{7-3} = Vd32{4-0};
1565}
1566class Enc_e6c957 : OpcodeHexagon {
1567  bits <10> Ii;
1568  let Inst{21-21} = Ii{9-9};
1569  let Inst{13-5} = Ii{8-0};
1570  bits <5> Rdd32;
1571  let Inst{4-0} = Rdd32{4-0};
1572}
1573class Enc_fa3ba4 : OpcodeHexagon {
1574  bits <14> Ii;
1575  let Inst{26-25} = Ii{13-12};
1576  let Inst{13-5} = Ii{11-3};
1577  bits <5> Rs32;
1578  let Inst{20-16} = Rs32{4-0};
1579  bits <5> Rdd32;
1580  let Inst{4-0} = Rdd32{4-0};
1581}
1582class Enc_0d8870 : OpcodeHexagon {
1583  bits <12> Ii;
1584  let Inst{26-25} = Ii{11-10};
1585  let Inst{13-13} = Ii{9-9};
1586  let Inst{7-0} = Ii{8-1};
1587  bits <5> Rs32;
1588  let Inst{20-16} = Rs32{4-0};
1589  bits <3> Nt8;
1590  let Inst{10-8} = Nt8{2-0};
1591}
1592class Enc_9fae8a : OpcodeHexagon {
1593  bits <6> Ii;
1594  let Inst{13-8} = Ii{5-0};
1595  bits <5> Rs32;
1596  let Inst{20-16} = Rs32{4-0};
1597  bits <5> Rd32;
1598  let Inst{4-0} = Rd32{4-0};
1599}
1600class Enc_18c338 : OpcodeHexagon {
1601  bits <8> Ii;
1602  let Inst{12-5} = Ii{7-0};
1603  bits <8> II;
1604  let Inst{22-16} = II{7-1};
1605  let Inst{13-13} = II{0-0};
1606  bits <5> Rdd32;
1607  let Inst{4-0} = Rdd32{4-0};
1608}
1609class Enc_5ccba9 : OpcodeHexagon {
1610  bits <8> Ii;
1611  let Inst{12-7} = Ii{7-2};
1612  bits <6> II;
1613  let Inst{13-13} = II{5-5};
1614  let Inst{4-0} = II{4-0};
1615  bits <2> Pv4;
1616  let Inst{6-5} = Pv4{1-0};
1617  bits <5> Rs32;
1618  let Inst{20-16} = Rs32{4-0};
1619}
1620class Enc_0ed752 : OpcodeHexagon {
1621  bits <5> Rss32;
1622  let Inst{20-16} = Rss32{4-0};
1623  bits <5> Cdd32;
1624  let Inst{4-0} = Cdd32{4-0};
1625}
1626class Enc_908985 : OpcodeHexagon {
1627  bits <1> Mu2;
1628  let Inst{13-13} = Mu2{0-0};
1629  bits <5> Vss32;
1630  let Inst{7-3} = Vss32{4-0};
1631  bits <5> Rx32;
1632  let Inst{20-16} = Rx32{4-0};
1633}
1634class Enc_143445 : OpcodeHexagon {
1635  bits <13> Ii;
1636  let Inst{26-25} = Ii{12-11};
1637  let Inst{13-13} = Ii{10-10};
1638  let Inst{7-0} = Ii{9-2};
1639  bits <5> Rs32;
1640  let Inst{20-16} = Rs32{4-0};
1641  bits <5> Rt32;
1642  let Inst{12-8} = Rt32{4-0};
1643}
1644class Enc_3a3d62 : OpcodeHexagon {
1645  bits <5> Rs32;
1646  let Inst{20-16} = Rs32{4-0};
1647  bits <5> Rdd32;
1648  let Inst{4-0} = Rdd32{4-0};
1649}
1650class Enc_3e3989 : OpcodeHexagon {
1651  bits <11> Ii;
1652  let Inst{21-20} = Ii{10-9};
1653  let Inst{7-1} = Ii{8-2};
1654  bits <4> Rs16;
1655  let Inst{19-16} = Rs16{3-0};
1656  bits <6> n1;
1657  let Inst{28-28} = n1{5-5};
1658  let Inst{25-22} = n1{4-1};
1659  let Inst{8-8} = n1{0-0};
1660}
1661class Enc_12dd8f : OpcodeHexagon {
1662  bits <5> Vu32;
1663  let Inst{20-16} = Vu32{4-0};
1664  bits <5> Vv32;
1665  let Inst{12-8} = Vv32{4-0};
1666  bits <3> Rt8;
1667  let Inst{2-0} = Rt8{2-0};
1668  bits <5> Vx32;
1669  let Inst{7-3} = Vx32{4-0};
1670}
1671class Enc_152467 : OpcodeHexagon {
1672  bits <5> Ii;
1673  let Inst{8-5} = Ii{4-1};
1674  bits <5> Rd32;
1675  let Inst{4-0} = Rd32{4-0};
1676  bits <5> Rx32;
1677  let Inst{20-16} = Rx32{4-0};
1678}
1679class Enc_6b1bc4 : OpcodeHexagon {
1680  bits <5> Vuu32;
1681  let Inst{20-16} = Vuu32{4-0};
1682  bits <3> Qt8;
1683  let Inst{10-8} = Qt8{2-0};
1684  bits <5> Vdd32;
1685  let Inst{7-3} = Vdd32{4-0};
1686}
1687class Enc_daea09 : OpcodeHexagon {
1688  bits <17> Ii;
1689  let Inst{23-22} = Ii{16-15};
1690  let Inst{20-16} = Ii{14-10};
1691  let Inst{13-13} = Ii{9-9};
1692  let Inst{7-1} = Ii{8-2};
1693  bits <2> Pu4;
1694  let Inst{9-8} = Pu4{1-0};
1695}
1696class Enc_f37377 : OpcodeHexagon {
1697  bits <8> Ii;
1698  let Inst{12-7} = Ii{7-2};
1699  bits <8> II;
1700  let Inst{13-13} = II{7-7};
1701  let Inst{6-0} = II{6-0};
1702  bits <5> Rs32;
1703  let Inst{20-16} = Rs32{4-0};
1704}
1705class Enc_a198f6 : OpcodeHexagon {
1706  bits <7> Ii;
1707  let Inst{10-5} = Ii{6-1};
1708  bits <2> Pt4;
1709  let Inst{12-11} = Pt4{1-0};
1710  bits <5> Rs32;
1711  let Inst{20-16} = Rs32{4-0};
1712  bits <5> Rd32;
1713  let Inst{4-0} = Rd32{4-0};
1714}
1715class Enc_a265b7 : OpcodeHexagon {
1716  bits <5> Vuu32;
1717  let Inst{20-16} = Vuu32{4-0};
1718  bits <5> Vd32;
1719  let Inst{7-3} = Vd32{4-0};
1720}
1721class Enc_4e4a80 : OpcodeHexagon {
1722  bits <2> Qs4;
1723  let Inst{6-5} = Qs4{1-0};
1724  bits <5> Rt32;
1725  let Inst{20-16} = Rt32{4-0};
1726  bits <1> Mu2;
1727  let Inst{13-13} = Mu2{0-0};
1728  bits <5> Vvv32;
1729  let Inst{4-0} = Vvv32{4-0};
1730}
1731class Enc_8d5d98 : OpcodeHexagon {
1732  bits <5> Vu32;
1733  let Inst{20-16} = Vu32{4-0};
1734  bits <5> Vv32;
1735  let Inst{12-8} = Vv32{4-0};
1736  bits <3> Rt8;
1737  let Inst{2-0} = Rt8{2-0};
1738  bits <5> Vxx32;
1739  let Inst{7-3} = Vxx32{4-0};
1740}
1741class Enc_3dac0b : OpcodeHexagon {
1742  bits <2> Qt4;
1743  let Inst{6-5} = Qt4{1-0};
1744  bits <5> Vu32;
1745  let Inst{12-8} = Vu32{4-0};
1746  bits <5> Vv32;
1747  let Inst{20-16} = Vv32{4-0};
1748  bits <5> Vdd32;
1749  let Inst{4-0} = Vdd32{4-0};
1750}
1751class Enc_e38e1f : OpcodeHexagon {
1752  bits <8> Ii;
1753  let Inst{12-5} = Ii{7-0};
1754  bits <2> Pu4;
1755  let Inst{22-21} = Pu4{1-0};
1756  bits <5> Rs32;
1757  let Inst{20-16} = Rs32{4-0};
1758  bits <5> Rd32;
1759  let Inst{4-0} = Rd32{4-0};
1760}
1761class Enc_f8ecf9 : OpcodeHexagon {
1762  bits <5> Vuu32;
1763  let Inst{12-8} = Vuu32{4-0};
1764  bits <5> Vvv32;
1765  let Inst{20-16} = Vvv32{4-0};
1766  bits <5> Vdd32;
1767  let Inst{4-0} = Vdd32{4-0};
1768}
1769class Enc_7f1a05 : OpcodeHexagon {
1770  bits <5> Ru32;
1771  let Inst{4-0} = Ru32{4-0};
1772  bits <5> Rs32;
1773  let Inst{20-16} = Rs32{4-0};
1774  bits <5> Ry32;
1775  let Inst{12-8} = Ry32{4-0};
1776}
1777class Enc_2df31d : OpcodeHexagon {
1778  bits <8> Ii;
1779  let Inst{9-4} = Ii{7-2};
1780  bits <4> Rd16;
1781  let Inst{3-0} = Rd16{3-0};
1782}
1783class Enc_b0e553 : OpcodeHexagon {
1784  bits <16> Ii;
1785  let Inst{21-21} = Ii{15-15};
1786  let Inst{13-8} = Ii{14-9};
1787  let Inst{2-0} = Ii{8-6};
1788  bits <5> Vd32;
1789  let Inst{7-3} = Vd32{4-0};
1790  bits <5> Rx32;
1791  let Inst{20-16} = Rx32{4-0};
1792}
1793class Enc_25bef0 : OpcodeHexagon {
1794  bits <16> Ii;
1795  let Inst{26-25} = Ii{15-14};
1796  let Inst{20-16} = Ii{13-9};
1797  let Inst{13-5} = Ii{8-0};
1798  bits <5> Rd32;
1799  let Inst{4-0} = Rd32{4-0};
1800}
1801class Enc_f82302 : OpcodeHexagon {
1802  bits <11> Ii;
1803  let Inst{21-20} = Ii{10-9};
1804  let Inst{7-1} = Ii{8-2};
1805  bits <3> Ns8;
1806  let Inst{18-16} = Ns8{2-0};
1807  bits <4> n1;
1808  let Inst{29-29} = n1{3-3};
1809  let Inst{26-25} = n1{2-1};
1810  let Inst{23-23} = n1{0-0};
1811}
1812class Enc_44271f : OpcodeHexagon {
1813  bits <5> Gs32;
1814  let Inst{20-16} = Gs32{4-0};
1815  bits <5> Rd32;
1816  let Inst{4-0} = Rd32{4-0};
1817}
1818class Enc_83ee64 : OpcodeHexagon {
1819  bits <5> Ii;
1820  let Inst{12-8} = Ii{4-0};
1821  bits <5> Rs32;
1822  let Inst{20-16} = Rs32{4-0};
1823  bits <2> Pd4;
1824  let Inst{1-0} = Pd4{1-0};
1825}
1826class Enc_adf111 : OpcodeHexagon {
1827  bits <5> Vu32;
1828  let Inst{12-8} = Vu32{4-0};
1829  bits <5> Rt32;
1830  let Inst{20-16} = Rt32{4-0};
1831  bits <2> Qx4;
1832  let Inst{1-0} = Qx4{1-0};
1833}
1834class Enc_46c951 : OpcodeHexagon {
1835  bits <6> Ii;
1836  let Inst{12-7} = Ii{5-0};
1837  bits <5> II;
1838  let Inst{4-0} = II{4-0};
1839  bits <5> Rs32;
1840  let Inst{20-16} = Rs32{4-0};
1841}
1842class Enc_5d6c34 : OpcodeHexagon {
1843  bits <6> Ii;
1844  let Inst{13-8} = Ii{5-0};
1845  bits <5> Rs32;
1846  let Inst{20-16} = Rs32{4-0};
1847  bits <2> Pd4;
1848  let Inst{1-0} = Pd4{1-0};
1849}
1850class Enc_4df4e9 : OpcodeHexagon {
1851  bits <11> Ii;
1852  let Inst{26-25} = Ii{10-9};
1853  let Inst{13-13} = Ii{8-8};
1854  let Inst{7-0} = Ii{7-0};
1855  bits <5> Rs32;
1856  let Inst{20-16} = Rs32{4-0};
1857  bits <3> Nt8;
1858  let Inst{10-8} = Nt8{2-0};
1859}
1860class Enc_263841 : OpcodeHexagon {
1861  bits <5> Vu32;
1862  let Inst{12-8} = Vu32{4-0};
1863  bits <5> Rtt32;
1864  let Inst{20-16} = Rtt32{4-0};
1865  bits <5> Vd32;
1866  let Inst{4-0} = Vd32{4-0};
1867}
1868class Enc_91b9fe : OpcodeHexagon {
1869  bits <5> Ii;
1870  let Inst{6-3} = Ii{4-1};
1871  bits <1> Mu2;
1872  let Inst{13-13} = Mu2{0-0};
1873  bits <3> Nt8;
1874  let Inst{10-8} = Nt8{2-0};
1875  bits <5> Rx32;
1876  let Inst{20-16} = Rx32{4-0};
1877}
1878class Enc_a7b8e8 : OpcodeHexagon {
1879  bits <6> Ii;
1880  let Inst{22-21} = Ii{5-4};
1881  let Inst{13-13} = Ii{3-3};
1882  let Inst{7-5} = Ii{2-0};
1883  bits <5> Rs32;
1884  let Inst{20-16} = Rs32{4-0};
1885  bits <5> Rt32;
1886  let Inst{12-8} = Rt32{4-0};
1887  bits <5> Rd32;
1888  let Inst{4-0} = Rd32{4-0};
1889}
1890class Enc_2b3f60 : OpcodeHexagon {
1891  bits <5> Rss32;
1892  let Inst{20-16} = Rss32{4-0};
1893  bits <5> Rtt32;
1894  let Inst{12-8} = Rtt32{4-0};
1895  bits <5> Rdd32;
1896  let Inst{4-0} = Rdd32{4-0};
1897  bits <2> Px4;
1898  let Inst{6-5} = Px4{1-0};
1899}
1900class Enc_bd1cbc : OpcodeHexagon {
1901  bits <5> Ii;
1902  let Inst{8-5} = Ii{4-1};
1903  bits <5> Ryy32;
1904  let Inst{4-0} = Ryy32{4-0};
1905  bits <5> Rx32;
1906  let Inst{20-16} = Rx32{4-0};
1907}
1908class Enc_d0fe02 : OpcodeHexagon {
1909  bits <5> Rxx32;
1910  let Inst{20-16} = Rxx32{4-0};
1911  bits <0> sgp10;
1912}
1913class Enc_a30110 : OpcodeHexagon {
1914  bits <5> Vu32;
1915  let Inst{12-8} = Vu32{4-0};
1916  bits <5> Vv32;
1917  let Inst{23-19} = Vv32{4-0};
1918  bits <3> Rt8;
1919  let Inst{18-16} = Rt8{2-0};
1920  bits <5> Vd32;
1921  let Inst{4-0} = Vd32{4-0};
1922}
1923class Enc_f3f408 : OpcodeHexagon {
1924  bits <4> Ii;
1925  let Inst{13-13} = Ii{3-3};
1926  let Inst{10-8} = Ii{2-0};
1927  bits <5> Rt32;
1928  let Inst{20-16} = Rt32{4-0};
1929  bits <5> Vd32;
1930  let Inst{4-0} = Vd32{4-0};
1931}
1932class Enc_ce4c54 : OpcodeHexagon {
1933  bits <16> Ii;
1934  let Inst{21-21} = Ii{15-15};
1935  let Inst{13-8} = Ii{14-9};
1936  let Inst{2-0} = Ii{8-6};
1937  bits <5> Rt32;
1938  let Inst{20-16} = Rt32{4-0};
1939  bits <5> Vd32;
1940  let Inst{7-3} = Vd32{4-0};
1941}
1942class Enc_690862 : OpcodeHexagon {
1943  bits <13> Ii;
1944  let Inst{26-25} = Ii{12-11};
1945  let Inst{13-13} = Ii{10-10};
1946  let Inst{7-0} = Ii{9-2};
1947  bits <5> Rs32;
1948  let Inst{20-16} = Rs32{4-0};
1949  bits <3> Nt8;
1950  let Inst{10-8} = Nt8{2-0};
1951}
1952class Enc_e570b0 : OpcodeHexagon {
1953  bits <5> Rtt32;
1954  let Inst{20-16} = Rtt32{4-0};
1955  bits <5> Vdd32;
1956  let Inst{7-3} = Vdd32{4-0};
1957}
1958class Enc_3c46e8 : OpcodeHexagon {
1959  bits <5> Vuu32;
1960  let Inst{12-8} = Vuu32{4-0};
1961  bits <5> Rt32;
1962  let Inst{20-16} = Rt32{4-0};
1963  bits <5> Vdd32;
1964  let Inst{7-3} = Vdd32{4-0};
1965}
1966class Enc_2a3787 : OpcodeHexagon {
1967  bits <13> Ii;
1968  let Inst{26-25} = Ii{12-11};
1969  let Inst{13-5} = Ii{10-2};
1970  bits <5> Rs32;
1971  let Inst{20-16} = Rs32{4-0};
1972  bits <5> Rd32;
1973  let Inst{4-0} = Rd32{4-0};
1974}
1975class Enc_d5c73f : OpcodeHexagon {
1976  bits <1> Mu2;
1977  let Inst{13-13} = Mu2{0-0};
1978  bits <5> Rt32;
1979  let Inst{12-8} = Rt32{4-0};
1980  bits <5> Rx32;
1981  let Inst{20-16} = Rx32{4-0};
1982}
1983class Enc_3f97c8 : OpcodeHexagon {
1984  bits <6> Ii;
1985  let Inst{6-3} = Ii{5-2};
1986  bits <1> Mu2;
1987  let Inst{13-13} = Mu2{0-0};
1988  bits <3> Nt8;
1989  let Inst{10-8} = Nt8{2-0};
1990  bits <5> Rx32;
1991  let Inst{20-16} = Rx32{4-0};
1992}
1993class Enc_d50cd3 : OpcodeHexagon {
1994  bits <3> Ii;
1995  let Inst{7-5} = Ii{2-0};
1996  bits <5> Rss32;
1997  let Inst{20-16} = Rss32{4-0};
1998  bits <5> Rtt32;
1999  let Inst{12-8} = Rtt32{4-0};
2000  bits <5> Rdd32;
2001  let Inst{4-0} = Rdd32{4-0};
2002}
2003class Enc_729ff7 : OpcodeHexagon {
2004  bits <3> Ii;
2005  let Inst{7-5} = Ii{2-0};
2006  bits <5> Rtt32;
2007  let Inst{12-8} = Rtt32{4-0};
2008  bits <5> Rss32;
2009  let Inst{20-16} = Rss32{4-0};
2010  bits <5> Rdd32;
2011  let Inst{4-0} = Rdd32{4-0};
2012}
2013class Enc_5883d0 : OpcodeHexagon {
2014  bits <16> Ii;
2015  let Inst{21-21} = Ii{15-15};
2016  let Inst{13-8} = Ii{14-9};
2017  let Inst{2-0} = Ii{8-6};
2018  bits <5> Rt32;
2019  let Inst{20-16} = Rt32{4-0};
2020  bits <5> Vdd32;
2021  let Inst{7-3} = Vdd32{4-0};
2022}
2023class Enc_ff0e49 : OpcodeHexagon {
2024  bits <5> Rss32;
2025  let Inst{20-16} = Rss32{4-0};
2026  bits <6> Sdd64;
2027  let Inst{5-0} = Sdd64{5-0};
2028}
2029class Enc_217147 : OpcodeHexagon {
2030  bits <2> Qv4;
2031  let Inst{23-22} = Qv4{1-0};
2032}
2033class Enc_b9c5fb : OpcodeHexagon {
2034  bits <5> Rss32;
2035  let Inst{20-16} = Rss32{4-0};
2036  bits <5> Rdd32;
2037  let Inst{4-0} = Rdd32{4-0};
2038}
2039class Enc_f394d3 : OpcodeHexagon {
2040  bits <6> II;
2041  let Inst{11-8} = II{5-2};
2042  let Inst{6-5} = II{1-0};
2043  bits <5> Ryy32;
2044  let Inst{4-0} = Ryy32{4-0};
2045  bits <5> Re32;
2046  let Inst{20-16} = Re32{4-0};
2047}
2048class Enc_0cb018 : OpcodeHexagon {
2049  bits <5> Cs32;
2050  let Inst{20-16} = Cs32{4-0};
2051  bits <5> Rd32;
2052  let Inst{4-0} = Rd32{4-0};
2053}
2054class Enc_541f26 : OpcodeHexagon {
2055  bits <18> Ii;
2056  let Inst{26-25} = Ii{17-16};
2057  let Inst{20-16} = Ii{15-11};
2058  let Inst{13-13} = Ii{10-10};
2059  let Inst{7-0} = Ii{9-2};
2060  bits <5> Rt32;
2061  let Inst{12-8} = Rt32{4-0};
2062}
2063class Enc_9aae4a : OpcodeHexagon {
2064  bits <5> Rt32;
2065  let Inst{20-16} = Rt32{4-0};
2066  bits <5> Vx32;
2067  let Inst{7-3} = Vx32{4-0};
2068  bits <3> Qd8;
2069  let Inst{2-0} = Qd8{2-0};
2070}
2071class Enc_724154 : OpcodeHexagon {
2072  bits <6> II;
2073  let Inst{5-0} = II{5-0};
2074  bits <3> Nt8;
2075  let Inst{10-8} = Nt8{2-0};
2076  bits <5> Re32;
2077  let Inst{20-16} = Re32{4-0};
2078}
2079class Enc_179b35 : OpcodeHexagon {
2080  bits <5> Rs32;
2081  let Inst{20-16} = Rs32{4-0};
2082  bits <5> Rtt32;
2083  let Inst{12-8} = Rtt32{4-0};
2084  bits <5> Rx32;
2085  let Inst{4-0} = Rx32{4-0};
2086}
2087class Enc_585242 : OpcodeHexagon {
2088  bits <6> Ii;
2089  let Inst{13-13} = Ii{5-5};
2090  let Inst{7-3} = Ii{4-0};
2091  bits <2> Pv4;
2092  let Inst{1-0} = Pv4{1-0};
2093  bits <5> Rs32;
2094  let Inst{20-16} = Rs32{4-0};
2095  bits <3> Nt8;
2096  let Inst{10-8} = Nt8{2-0};
2097}
2098class Enc_cf1927 : OpcodeHexagon {
2099  bits <1> Mu2;
2100  let Inst{13-13} = Mu2{0-0};
2101  bits <3> Os8;
2102  let Inst{2-0} = Os8{2-0};
2103  bits <5> Rx32;
2104  let Inst{20-16} = Rx32{4-0};
2105}
2106class Enc_b84c4c : OpcodeHexagon {
2107  bits <6> Ii;
2108  let Inst{13-8} = Ii{5-0};
2109  bits <6> II;
2110  let Inst{23-21} = II{5-3};
2111  let Inst{7-5} = II{2-0};
2112  bits <5> Rss32;
2113  let Inst{20-16} = Rss32{4-0};
2114  bits <5> Rdd32;
2115  let Inst{4-0} = Rdd32{4-0};
2116}
2117class Enc_9ac432 : OpcodeHexagon {
2118  bits <2> Ps4;
2119  let Inst{17-16} = Ps4{1-0};
2120  bits <2> Pt4;
2121  let Inst{9-8} = Pt4{1-0};
2122  bits <2> Pu4;
2123  let Inst{7-6} = Pu4{1-0};
2124  bits <2> Pd4;
2125  let Inst{1-0} = Pd4{1-0};
2126}
2127class Enc_8203bb : OpcodeHexagon {
2128  bits <6> Ii;
2129  let Inst{12-7} = Ii{5-0};
2130  bits <8> II;
2131  let Inst{13-13} = II{7-7};
2132  let Inst{6-0} = II{6-0};
2133  bits <5> Rs32;
2134  let Inst{20-16} = Rs32{4-0};
2135}
2136class Enc_e66a97 : OpcodeHexagon {
2137  bits <7> Ii;
2138  let Inst{12-7} = Ii{6-1};
2139  bits <5> II;
2140  let Inst{4-0} = II{4-0};
2141  bits <5> Rs32;
2142  let Inst{20-16} = Rs32{4-0};
2143}
2144class Enc_8c2412 : OpcodeHexagon {
2145  bits <2> Ps4;
2146  let Inst{6-5} = Ps4{1-0};
2147  bits <5> Vu32;
2148  let Inst{12-8} = Vu32{4-0};
2149  bits <5> Vv32;
2150  let Inst{20-16} = Vv32{4-0};
2151  bits <5> Vdd32;
2152  let Inst{4-0} = Vdd32{4-0};
2153}
2154class Enc_284ebb : OpcodeHexagon {
2155  bits <2> Ps4;
2156  let Inst{17-16} = Ps4{1-0};
2157  bits <2> Pt4;
2158  let Inst{9-8} = Pt4{1-0};
2159  bits <2> Pd4;
2160  let Inst{1-0} = Pd4{1-0};
2161}
2162class Enc_733b27 : OpcodeHexagon {
2163  bits <5> Ii;
2164  let Inst{8-5} = Ii{4-1};
2165  bits <2> Pt4;
2166  let Inst{10-9} = Pt4{1-0};
2167  bits <5> Rd32;
2168  let Inst{4-0} = Rd32{4-0};
2169  bits <5> Rx32;
2170  let Inst{20-16} = Rx32{4-0};
2171}
2172class Enc_22c845 : OpcodeHexagon {
2173  bits <14> Ii;
2174  let Inst{10-0} = Ii{13-3};
2175  bits <5> Rx32;
2176  let Inst{20-16} = Rx32{4-0};
2177}
2178class Enc_ed5027 : OpcodeHexagon {
2179  bits <5> Rss32;
2180  let Inst{20-16} = Rss32{4-0};
2181  bits <5> Gdd32;
2182  let Inst{4-0} = Gdd32{4-0};
2183}
2184class Enc_9b0bc1 : OpcodeHexagon {
2185  bits <2> Pu4;
2186  let Inst{6-5} = Pu4{1-0};
2187  bits <5> Rt32;
2188  let Inst{12-8} = Rt32{4-0};
2189  bits <5> Rs32;
2190  let Inst{20-16} = Rs32{4-0};
2191  bits <5> Rd32;
2192  let Inst{4-0} = Rd32{4-0};
2193}
2194class Enc_ea4c54 : OpcodeHexagon {
2195  bits <2> Pu4;
2196  let Inst{6-5} = Pu4{1-0};
2197  bits <5> Rs32;
2198  let Inst{20-16} = Rs32{4-0};
2199  bits <5> Rt32;
2200  let Inst{12-8} = Rt32{4-0};
2201  bits <5> Rd32;
2202  let Inst{4-0} = Rd32{4-0};
2203}
2204class Enc_b72622 : OpcodeHexagon {
2205  bits <2> Ii;
2206  let Inst{13-13} = Ii{1-1};
2207  let Inst{5-5} = Ii{0-0};
2208  bits <5> Rss32;
2209  let Inst{20-16} = Rss32{4-0};
2210  bits <5> Rt32;
2211  let Inst{12-8} = Rt32{4-0};
2212  bits <5> Rxx32;
2213  let Inst{4-0} = Rxx32{4-0};
2214}
2215class Enc_569cfe : OpcodeHexagon {
2216  bits <5> Rt32;
2217  let Inst{20-16} = Rt32{4-0};
2218  bits <5> Vx32;
2219  let Inst{4-0} = Vx32{4-0};
2220}
2221class Enc_96ce4f : OpcodeHexagon {
2222  bits <4> Ii;
2223  let Inst{6-3} = Ii{3-0};
2224  bits <1> Mu2;
2225  let Inst{13-13} = Mu2{0-0};
2226  bits <3> Nt8;
2227  let Inst{10-8} = Nt8{2-0};
2228  bits <5> Rx32;
2229  let Inst{20-16} = Rx32{4-0};
2230}
2231class Enc_2bbae6 : OpcodeHexagon {
2232  bits <6> Ss64;
2233  let Inst{21-16} = Ss64{5-0};
2234  bits <5> Rd32;
2235  let Inst{4-0} = Rd32{4-0};
2236}
2237class Enc_143a3c : OpcodeHexagon {
2238  bits <6> Ii;
2239  let Inst{13-8} = Ii{5-0};
2240  bits <6> II;
2241  let Inst{23-21} = II{5-3};
2242  let Inst{7-5} = II{2-0};
2243  bits <5> Rss32;
2244  let Inst{20-16} = Rss32{4-0};
2245  bits <5> Rxx32;
2246  let Inst{4-0} = Rxx32{4-0};
2247}
2248class Enc_57a33e : OpcodeHexagon {
2249  bits <9> Ii;
2250  let Inst{13-13} = Ii{8-8};
2251  let Inst{7-3} = Ii{7-3};
2252  bits <2> Pv4;
2253  let Inst{1-0} = Pv4{1-0};
2254  bits <5> Rs32;
2255  let Inst{20-16} = Rs32{4-0};
2256  bits <5> Rtt32;
2257  let Inst{12-8} = Rtt32{4-0};
2258}
2259class Enc_311abd : OpcodeHexagon {
2260  bits <5> Ii;
2261  let Inst{12-8} = Ii{4-0};
2262  bits <5> Rs32;
2263  let Inst{20-16} = Rs32{4-0};
2264  bits <5> Rdd32;
2265  let Inst{4-0} = Rdd32{4-0};
2266}
2267class Enc_a1640c : OpcodeHexagon {
2268  bits <6> Ii;
2269  let Inst{13-8} = Ii{5-0};
2270  bits <5> Rss32;
2271  let Inst{20-16} = Rss32{4-0};
2272  bits <5> Rd32;
2273  let Inst{4-0} = Rd32{4-0};
2274}
2275class Enc_de0214 : OpcodeHexagon {
2276  bits <12> Ii;
2277  let Inst{26-25} = Ii{11-10};
2278  let Inst{13-5} = Ii{9-1};
2279  bits <5> Rs32;
2280  let Inst{20-16} = Rs32{4-0};
2281  bits <5> Rd32;
2282  let Inst{4-0} = Rd32{4-0};
2283}
2284class Enc_a90628 : OpcodeHexagon {
2285  bits <2> Qv4;
2286  let Inst{23-22} = Qv4{1-0};
2287  bits <5> Vu32;
2288  let Inst{12-8} = Vu32{4-0};
2289  bits <5> Vx32;
2290  let Inst{4-0} = Vx32{4-0};
2291}
2292class Enc_fda92c : OpcodeHexagon {
2293  bits <17> Ii;
2294  let Inst{26-25} = Ii{16-15};
2295  let Inst{20-16} = Ii{14-10};
2296  let Inst{13-13} = Ii{9-9};
2297  let Inst{7-0} = Ii{8-1};
2298  bits <5> Rt32;
2299  let Inst{12-8} = Rt32{4-0};
2300}
2301class Enc_831a7d : OpcodeHexagon {
2302  bits <5> Rss32;
2303  let Inst{20-16} = Rss32{4-0};
2304  bits <5> Rtt32;
2305  let Inst{12-8} = Rtt32{4-0};
2306  bits <5> Rxx32;
2307  let Inst{4-0} = Rxx32{4-0};
2308  bits <2> Pe4;
2309  let Inst{6-5} = Pe4{1-0};
2310}
2311class Enc_11a146 : OpcodeHexagon {
2312  bits <4> Ii;
2313  let Inst{11-8} = Ii{3-0};
2314  bits <5> Rss32;
2315  let Inst{20-16} = Rss32{4-0};
2316  bits <5> Rd32;
2317  let Inst{4-0} = Rd32{4-0};
2318}
2319class Enc_b15941 : OpcodeHexagon {
2320  bits <4> Ii;
2321  let Inst{6-3} = Ii{3-0};
2322  bits <1> Mu2;
2323  let Inst{13-13} = Mu2{0-0};
2324  bits <5> Rt32;
2325  let Inst{12-8} = Rt32{4-0};
2326  bits <5> Rx32;
2327  let Inst{20-16} = Rx32{4-0};
2328}
2329class Enc_b78edd : OpcodeHexagon {
2330  bits <11> Ii;
2331  let Inst{21-20} = Ii{10-9};
2332  let Inst{7-1} = Ii{8-2};
2333  bits <4> Rs16;
2334  let Inst{19-16} = Rs16{3-0};
2335  bits <4> n1;
2336  let Inst{28-28} = n1{3-3};
2337  let Inst{24-23} = n1{2-1};
2338  let Inst{8-8} = n1{0-0};
2339}
2340class Enc_a27588 : OpcodeHexagon {
2341  bits <11> Ii;
2342  let Inst{26-25} = Ii{10-9};
2343  let Inst{13-5} = Ii{8-0};
2344  bits <5> Rs32;
2345  let Inst{20-16} = Rs32{4-0};
2346  bits <5> Ryy32;
2347  let Inst{4-0} = Ryy32{4-0};
2348}
2349class Enc_2a7b91 : OpcodeHexagon {
2350  bits <6> Ii;
2351  let Inst{20-16} = Ii{5-1};
2352  let Inst{8-8} = Ii{0-0};
2353  bits <2> Pt4;
2354  let Inst{10-9} = Pt4{1-0};
2355  bits <5> Rdd32;
2356  let Inst{4-0} = Rdd32{4-0};
2357}
2358class Enc_b43b67 : OpcodeHexagon {
2359  bits <5> Vu32;
2360  let Inst{12-8} = Vu32{4-0};
2361  bits <5> Vv32;
2362  let Inst{20-16} = Vv32{4-0};
2363  bits <5> Vd32;
2364  let Inst{4-0} = Vd32{4-0};
2365  bits <2> Qx4;
2366  let Inst{6-5} = Qx4{1-0};
2367}
2368class Enc_1cd70f : OpcodeHexagon {
2369  bits <5> Vu32;
2370  let Inst{20-16} = Vu32{4-0};
2371  bits <5> Vv32;
2372  let Inst{12-8} = Vv32{4-0};
2373  bits <3> Rt8;
2374  let Inst{2-0} = Rt8{2-0};
2375  bits <5> Vd32;
2376  let Inst{7-3} = Vd32{4-0};
2377}
2378class Enc_3a527f : OpcodeHexagon {
2379  bits <16> Ii;
2380  let Inst{21-21} = Ii{15-15};
2381  let Inst{13-8} = Ii{14-9};
2382  let Inst{2-0} = Ii{8-6};
2383  bits <5> Vs32;
2384  let Inst{7-3} = Vs32{4-0};
2385  bits <5> Rx32;
2386  let Inst{20-16} = Rx32{4-0};
2387}
2388class Enc_4aca3a : OpcodeHexagon {
2389  bits <11> Ii;
2390  let Inst{21-20} = Ii{10-9};
2391  let Inst{7-1} = Ii{8-2};
2392  bits <3> Ns8;
2393  let Inst{18-16} = Ns8{2-0};
2394  bits <3> n1;
2395  let Inst{29-29} = n1{2-2};
2396  let Inst{26-25} = n1{1-0};
2397}
2398class Enc_b38ffc : OpcodeHexagon {
2399  bits <4> Ii;
2400  let Inst{11-8} = Ii{3-0};
2401  bits <4> Rs16;
2402  let Inst{7-4} = Rs16{3-0};
2403  bits <4> Rt16;
2404  let Inst{3-0} = Rt16{3-0};
2405}
2406class Enc_5c3a80 : OpcodeHexagon {
2407  bits <3> Qt8;
2408  let Inst{10-8} = Qt8{2-0};
2409  bits <3> Qd8;
2410  let Inst{5-3} = Qd8{2-0};
2411}
2412class Enc_cda00a : OpcodeHexagon {
2413  bits <12> Ii;
2414  let Inst{19-16} = Ii{11-8};
2415  let Inst{12-5} = Ii{7-0};
2416  bits <2> Pu4;
2417  let Inst{22-21} = Pu4{1-0};
2418  bits <5> Rd32;
2419  let Inst{4-0} = Rd32{4-0};
2420}
2421class Enc_2fbf3c : OpcodeHexagon {
2422  bits <3> Ii;
2423  let Inst{10-8} = Ii{2-0};
2424  bits <4> Rs16;
2425  let Inst{7-4} = Rs16{3-0};
2426  bits <4> Rd16;
2427  let Inst{3-0} = Rd16{3-0};
2428}
2429class Enc_a4ae28 : OpcodeHexagon {
2430  bits <5> Vu32;
2431  let Inst{20-16} = Vu32{4-0};
2432  bits <5> Vv32;
2433  let Inst{12-8} = Vv32{4-0};
2434  bits <3> Qd8;
2435  let Inst{5-3} = Qd8{2-0};
2436}
2437class Enc_dd5f9f : OpcodeHexagon {
2438  bits <3> Qtt8;
2439  let Inst{2-0} = Qtt8{2-0};
2440  bits <5> Vuu32;
2441  let Inst{20-16} = Vuu32{4-0};
2442  bits <5> Vvv32;
2443  let Inst{12-8} = Vvv32{4-0};
2444  bits <5> Vdd32;
2445  let Inst{7-3} = Vdd32{4-0};
2446}
2447class Enc_70b24b : OpcodeHexagon {
2448  bits <6> Ii;
2449  let Inst{8-5} = Ii{5-2};
2450  bits <1> Mu2;
2451  let Inst{13-13} = Mu2{0-0};
2452  bits <5> Rdd32;
2453  let Inst{4-0} = Rdd32{4-0};
2454  bits <5> Rx32;
2455  let Inst{20-16} = Rx32{4-0};
2456}
2457class Enc_2ae154 : OpcodeHexagon {
2458  bits <5> Rs32;
2459  let Inst{20-16} = Rs32{4-0};
2460  bits <5> Rt32;
2461  let Inst{12-8} = Rt32{4-0};
2462  bits <5> Rx32;
2463  let Inst{4-0} = Rx32{4-0};
2464}
2465class Enc_50b5ac : OpcodeHexagon {
2466  bits <6> Ii;
2467  let Inst{17-16} = Ii{5-4};
2468  let Inst{6-3} = Ii{3-0};
2469  bits <2> Pv4;
2470  let Inst{1-0} = Pv4{1-0};
2471  bits <5> Rtt32;
2472  let Inst{12-8} = Rtt32{4-0};
2473}
2474class Enc_2ea740 : OpcodeHexagon {
2475  bits <4> Ii;
2476  let Inst{13-13} = Ii{3-3};
2477  let Inst{10-8} = Ii{2-0};
2478  bits <2> Qv4;
2479  let Inst{12-11} = Qv4{1-0};
2480  bits <5> Rt32;
2481  let Inst{20-16} = Rt32{4-0};
2482  bits <5> Vs32;
2483  let Inst{4-0} = Vs32{4-0};
2484}
2485class Enc_08d755 : OpcodeHexagon {
2486  bits <8> Ii;
2487  let Inst{12-5} = Ii{7-0};
2488  bits <5> Rs32;
2489  let Inst{20-16} = Rs32{4-0};
2490  bits <2> Pd4;
2491  let Inst{1-0} = Pd4{1-0};
2492}
2493class Enc_a7ca29 : OpcodeHexagon {
2494  bits <3> Qt8;
2495  let Inst{2-0} = Qt8{2-0};
2496  bits <5> Vu32;
2497  let Inst{20-16} = Vu32{4-0};
2498  bits <5> Vv32;
2499  let Inst{12-8} = Vv32{4-0};
2500  bits <5> Vd32;
2501  let Inst{7-3} = Vd32{4-0};
2502}
2503class Enc_1178da : OpcodeHexagon {
2504  bits <3> Ii;
2505  let Inst{7-5} = Ii{2-0};
2506  bits <5> Vu32;
2507  let Inst{12-8} = Vu32{4-0};
2508  bits <5> Vv32;
2509  let Inst{20-16} = Vv32{4-0};
2510  bits <5> Vxx32;
2511  let Inst{4-0} = Vxx32{4-0};
2512}
2513class Enc_8dbe85 : OpcodeHexagon {
2514  bits <1> Mu2;
2515  let Inst{13-13} = Mu2{0-0};
2516  bits <3> Nt8;
2517  let Inst{10-8} = Nt8{2-0};
2518  bits <5> Rx32;
2519  let Inst{20-16} = Rx32{4-0};
2520}
2521class Enc_17a474 : OpcodeHexagon {
2522  bits <1> Mu2;
2523  let Inst{13-13} = Mu2{0-0};
2524  bits <5> Vs32;
2525  let Inst{7-3} = Vs32{4-0};
2526  bits <5> Rx32;
2527  let Inst{20-16} = Rx32{4-0};
2528}
2529class Enc_5a18b3 : OpcodeHexagon {
2530  bits <11> Ii;
2531  let Inst{21-20} = Ii{10-9};
2532  let Inst{7-1} = Ii{8-2};
2533  bits <3> Ns8;
2534  let Inst{18-16} = Ns8{2-0};
2535  bits <5> n1;
2536  let Inst{29-29} = n1{4-4};
2537  let Inst{26-25} = n1{3-2};
2538  let Inst{22-22} = n1{1-1};
2539  let Inst{13-13} = n1{0-0};
2540}
2541class Enc_14d27a : OpcodeHexagon {
2542  bits <5> II;
2543  let Inst{12-8} = II{4-0};
2544  bits <11> Ii;
2545  let Inst{21-20} = Ii{10-9};
2546  let Inst{7-1} = Ii{8-2};
2547  bits <4> Rs16;
2548  let Inst{19-16} = Rs16{3-0};
2549}
2550class Enc_a05677 : OpcodeHexagon {
2551  bits <5> Ii;
2552  let Inst{12-8} = Ii{4-0};
2553  bits <5> Rs32;
2554  let Inst{20-16} = Rs32{4-0};
2555  bits <5> Rd32;
2556  let Inst{4-0} = Rd32{4-0};
2557}
2558class Enc_f0cca7 : OpcodeHexagon {
2559  bits <8> Ii;
2560  let Inst{12-5} = Ii{7-0};
2561  bits <6> II;
2562  let Inst{20-16} = II{5-1};
2563  let Inst{13-13} = II{0-0};
2564  bits <5> Rdd32;
2565  let Inst{4-0} = Rdd32{4-0};
2566}
2567class Enc_500cb0 : OpcodeHexagon {
2568  bits <5> Vu32;
2569  let Inst{12-8} = Vu32{4-0};
2570  bits <5> Vxx32;
2571  let Inst{4-0} = Vxx32{4-0};
2572}
2573class Enc_7e5a82 : OpcodeHexagon {
2574  bits <5> Ii;
2575  let Inst{12-8} = Ii{4-0};
2576  bits <5> Rss32;
2577  let Inst{20-16} = Rss32{4-0};
2578  bits <5> Rdd32;
2579  let Inst{4-0} = Rdd32{4-0};
2580}
2581class Enc_12b6e9 : OpcodeHexagon {
2582  bits <4> Ii;
2583  let Inst{11-8} = Ii{3-0};
2584  bits <5> Rss32;
2585  let Inst{20-16} = Rss32{4-0};
2586  bits <5> Rdd32;
2587  let Inst{4-0} = Rdd32{4-0};
2588}
2589class Enc_9a895f : OpcodeHexagon {
2590  bits <1> Mu2;
2591  let Inst{13-13} = Mu2{0-0};
2592  bits <5> Vdd32;
2593  let Inst{7-3} = Vdd32{4-0};
2594  bits <5> Rx32;
2595  let Inst{20-16} = Rx32{4-0};
2596}
2597class Enc_6f70ca : OpcodeHexagon {
2598  bits <8> Ii;
2599  let Inst{8-4} = Ii{7-3};
2600}
2601class Enc_7222b7 : OpcodeHexagon {
2602  bits <5> Rt32;
2603  let Inst{20-16} = Rt32{4-0};
2604  bits <2> Qd4;
2605  let Inst{1-0} = Qd4{1-0};
2606}
2607class Enc_e3b0c4 : OpcodeHexagon {
2608}
2609class Enc_d7e8ba : OpcodeHexagon {
2610  bits <5> Vu32;
2611  let Inst{20-16} = Vu32{4-0};
2612  bits <5> Vdd32;
2613  let Inst{7-3} = Vdd32{4-0};
2614}
2615class Enc_a255dc : OpcodeHexagon {
2616  bits <3> Ii;
2617  let Inst{10-8} = Ii{2-0};
2618  bits <5> Vd32;
2619  let Inst{4-0} = Vd32{4-0};
2620  bits <5> Rx32;
2621  let Inst{20-16} = Rx32{4-0};
2622}
2623class Enc_cb785b : OpcodeHexagon {
2624  bits <5> Vu32;
2625  let Inst{12-8} = Vu32{4-0};
2626  bits <5> Rtt32;
2627  let Inst{20-16} = Rtt32{4-0};
2628  bits <5> Vdd32;
2629  let Inst{4-0} = Vdd32{4-0};
2630}
2631class Enc_5b76ab : OpcodeHexagon {
2632  bits <10> Ii;
2633  let Inst{21-21} = Ii{9-9};
2634  let Inst{13-8} = Ii{8-3};
2635  let Inst{2-0} = Ii{2-0};
2636  bits <5> Vs32;
2637  let Inst{7-3} = Vs32{4-0};
2638  bits <5> Rx32;
2639  let Inst{20-16} = Rx32{4-0};
2640}
2641class Enc_cb4b4e : OpcodeHexagon {
2642  bits <2> Pu4;
2643  let Inst{6-5} = Pu4{1-0};
2644  bits <5> Rs32;
2645  let Inst{20-16} = Rs32{4-0};
2646  bits <5> Rt32;
2647  let Inst{12-8} = Rt32{4-0};
2648  bits <5> Rdd32;
2649  let Inst{4-0} = Rdd32{4-0};
2650}
2651class Enc_fbacc2 : OpcodeHexagon {
2652  bits <5> Vu32;
2653  let Inst{20-16} = Vu32{4-0};
2654  bits <3> Rt8;
2655  let Inst{2-0} = Rt8{2-0};
2656  bits <5> Vxx32;
2657  let Inst{7-3} = Vxx32{4-0};
2658  bits <5> Vy32;
2659  let Inst{12-8} = Vy32{4-0};
2660}
2661class Enc_2ad23d : OpcodeHexagon {
2662  bits <5> Vu32;
2663  let Inst{20-16} = Vu32{4-0};
2664  bits <5> Vv32;
2665  let Inst{12-8} = Vv32{4-0};
2666  bits <5> Vx32;
2667  let Inst{7-3} = Vx32{4-0};
2668}
2669class Enc_9cdba7 : OpcodeHexagon {
2670  bits <8> Ii;
2671  let Inst{12-5} = Ii{7-0};
2672  bits <5> Rs32;
2673  let Inst{20-16} = Rs32{4-0};
2674  bits <5> Rdd32;
2675  let Inst{4-0} = Rdd32{4-0};
2676}
2677class Enc_5cd7e9 : OpcodeHexagon {
2678  bits <12> Ii;
2679  let Inst{26-25} = Ii{11-10};
2680  let Inst{13-5} = Ii{9-1};
2681  bits <5> Rs32;
2682  let Inst{20-16} = Rs32{4-0};
2683  bits <5> Ryy32;
2684  let Inst{4-0} = Ryy32{4-0};
2685}
2686class Enc_e7c9de : OpcodeHexagon {
2687  bits <5> Vu32;
2688  let Inst{20-16} = Vu32{4-0};
2689}
2690class Enc_454a26 : OpcodeHexagon {
2691  bits <2> Pt4;
2692  let Inst{9-8} = Pt4{1-0};
2693  bits <2> Ps4;
2694  let Inst{17-16} = Ps4{1-0};
2695  bits <2> Pd4;
2696  let Inst{1-0} = Pd4{1-0};
2697}
2698class Enc_a6853f : OpcodeHexagon {
2699  bits <11> Ii;
2700  let Inst{21-20} = Ii{10-9};
2701  let Inst{7-1} = Ii{8-2};
2702  bits <3> Ns8;
2703  let Inst{18-16} = Ns8{2-0};
2704  bits <6> n1;
2705  let Inst{29-29} = n1{5-5};
2706  let Inst{26-25} = n1{4-3};
2707  let Inst{23-22} = n1{2-1};
2708  let Inst{13-13} = n1{0-0};
2709}
2710class Enc_c175d0 : OpcodeHexagon {
2711  bits <4> Ii;
2712  let Inst{11-8} = Ii{3-0};
2713  bits <4> Rs16;
2714  let Inst{7-4} = Rs16{3-0};
2715  bits <4> Rd16;
2716  let Inst{3-0} = Rd16{3-0};
2717}
2718class Enc_16c48b : OpcodeHexagon {
2719  bits <5> Rt32;
2720  let Inst{20-16} = Rt32{4-0};
2721  bits <1> Mu2;
2722  let Inst{13-13} = Mu2{0-0};
2723  bits <5> Vv32;
2724  let Inst{12-8} = Vv32{4-0};
2725  bits <5> Vw32;
2726  let Inst{4-0} = Vw32{4-0};
2727}
2728class Enc_895bd9 : OpcodeHexagon {
2729  bits <2> Qu4;
2730  let Inst{9-8} = Qu4{1-0};
2731  bits <5> Rt32;
2732  let Inst{20-16} = Rt32{4-0};
2733  bits <5> Vx32;
2734  let Inst{4-0} = Vx32{4-0};
2735}
2736class Enc_ea23e4 : OpcodeHexagon {
2737  bits <5> Rtt32;
2738  let Inst{12-8} = Rtt32{4-0};
2739  bits <5> Rss32;
2740  let Inst{20-16} = Rss32{4-0};
2741  bits <5> Rdd32;
2742  let Inst{4-0} = Rdd32{4-0};
2743}
2744class Enc_4dc228 : OpcodeHexagon {
2745  bits <9> Ii;
2746  let Inst{12-8} = Ii{8-4};
2747  let Inst{4-3} = Ii{3-2};
2748  bits <10> II;
2749  let Inst{20-16} = II{9-5};
2750  let Inst{7-5} = II{4-2};
2751  let Inst{1-0} = II{1-0};
2752}
2753class Enc_10bc21 : OpcodeHexagon {
2754  bits <4> Ii;
2755  let Inst{6-3} = Ii{3-0};
2756  bits <5> Rt32;
2757  let Inst{12-8} = Rt32{4-0};
2758  bits <5> Rx32;
2759  let Inst{20-16} = Rx32{4-0};
2760}
2761class Enc_1aaec1 : OpcodeHexagon {
2762  bits <3> Ii;
2763  let Inst{10-8} = Ii{2-0};
2764  bits <3> Os8;
2765  let Inst{2-0} = Os8{2-0};
2766  bits <5> Rx32;
2767  let Inst{20-16} = Rx32{4-0};
2768}
2769class Enc_329361 : OpcodeHexagon {
2770  bits <2> Pu4;
2771  let Inst{6-5} = Pu4{1-0};
2772  bits <5> Rss32;
2773  let Inst{20-16} = Rss32{4-0};
2774  bits <5> Rtt32;
2775  let Inst{12-8} = Rtt32{4-0};
2776  bits <5> Rdd32;
2777  let Inst{4-0} = Rdd32{4-0};
2778}
2779class Enc_d2c7f1 : OpcodeHexagon {
2780  bits <5> Rtt32;
2781  let Inst{12-8} = Rtt32{4-0};
2782  bits <5> Rss32;
2783  let Inst{20-16} = Rss32{4-0};
2784  bits <5> Rdd32;
2785  let Inst{4-0} = Rdd32{4-0};
2786  bits <2> Pe4;
2787  let Inst{6-5} = Pe4{1-0};
2788}
2789class Enc_dcfcbb : OpcodeHexagon {
2790  bits <5> Vu32;
2791  let Inst{20-16} = Vu32{4-0};
2792  bits <5> Vvv32;
2793  let Inst{12-8} = Vvv32{4-0};
2794  bits <5> Vd32;
2795  let Inst{7-3} = Vd32{4-0};
2796}
2797class Enc_3680c2 : OpcodeHexagon {
2798  bits <7> Ii;
2799  let Inst{11-5} = Ii{6-0};
2800  bits <5> Rss32;
2801  let Inst{20-16} = Rss32{4-0};
2802  bits <2> Pd4;
2803  let Inst{1-0} = Pd4{1-0};
2804}
2805class Enc_1ef990 : OpcodeHexagon {
2806  bits <2> Pv4;
2807  let Inst{12-11} = Pv4{1-0};
2808  bits <1> Mu2;
2809  let Inst{13-13} = Mu2{0-0};
2810  bits <5> Vs32;
2811  let Inst{4-0} = Vs32{4-0};
2812  bits <5> Rx32;
2813  let Inst{20-16} = Rx32{4-0};
2814}
2815class Enc_e957fb : OpcodeHexagon {
2816  bits <12> Ii;
2817  let Inst{26-25} = Ii{11-10};
2818  let Inst{13-13} = Ii{9-9};
2819  let Inst{7-0} = Ii{8-1};
2820  bits <5> Rs32;
2821  let Inst{20-16} = Rs32{4-0};
2822  bits <5> Rt32;
2823  let Inst{12-8} = Rt32{4-0};
2824}
2825class Enc_2146c1 : OpcodeHexagon {
2826  bits <5> Vuu32;
2827  let Inst{20-16} = Vuu32{4-0};
2828  bits <5> Vvv32;
2829  let Inst{12-8} = Vvv32{4-0};
2830  bits <3> Qss8;
2831  let Inst{2-0} = Qss8{2-0};
2832  bits <5> Vd32;
2833  let Inst{7-3} = Vd32{4-0};
2834}
2835class Enc_a662ae : OpcodeHexagon {
2836  bits <5> Vuu32;
2837  let Inst{20-16} = Vuu32{4-0};
2838  bits <5> Vvv32;
2839  let Inst{12-8} = Vvv32{4-0};
2840  bits <3> Rt8;
2841  let Inst{2-0} = Rt8{2-0};
2842  bits <5> Vdd32;
2843  let Inst{7-3} = Vdd32{4-0};
2844}
2845class Enc_8f7cc3 : OpcodeHexagon {
2846  bits <3> Qtt8;
2847  let Inst{10-8} = Qtt8{2-0};
2848  bits <3> Qdd8;
2849  let Inst{5-3} = Qdd8{2-0};
2850}
2851class Enc_c9e3bc : OpcodeHexagon {
2852  bits <4> Ii;
2853  let Inst{13-13} = Ii{3-3};
2854  let Inst{10-8} = Ii{2-0};
2855  bits <5> Rt32;
2856  let Inst{20-16} = Rt32{4-0};
2857  bits <5> Vs32;
2858  let Inst{4-0} = Vs32{4-0};
2859}
2860class Enc_2e1979 : OpcodeHexagon {
2861  bits <2> Ii;
2862  let Inst{13-13} = Ii{1-1};
2863  let Inst{7-7} = Ii{0-0};
2864  bits <2> Pv4;
2865  let Inst{6-5} = Pv4{1-0};
2866  bits <5> Rs32;
2867  let Inst{20-16} = Rs32{4-0};
2868  bits <5> Rt32;
2869  let Inst{12-8} = Rt32{4-0};
2870  bits <5> Rd32;
2871  let Inst{4-0} = Rd32{4-0};
2872}
2873class Enc_0b2e5b : OpcodeHexagon {
2874  bits <3> Ii;
2875  let Inst{7-5} = Ii{2-0};
2876  bits <5> Vu32;
2877  let Inst{12-8} = Vu32{4-0};
2878  bits <5> Vv32;
2879  let Inst{20-16} = Vv32{4-0};
2880  bits <5> Vd32;
2881  let Inst{4-0} = Vd32{4-0};
2882}
2883class Enc_6f83e7 : OpcodeHexagon {
2884  bits <2> Qv4;
2885  let Inst{23-22} = Qv4{1-0};
2886  bits <5> Vd32;
2887  let Inst{4-0} = Vd32{4-0};
2888}
2889class Enc_46f33d : OpcodeHexagon {
2890  bits <5> Rss32;
2891  let Inst{20-16} = Rss32{4-0};
2892  bits <5> Rt32;
2893  let Inst{12-8} = Rt32{4-0};
2894}
2895class Enc_c1652e : OpcodeHexagon {
2896  bits <5> Vu32;
2897  let Inst{12-8} = Vu32{4-0};
2898  bits <5> Rt32;
2899  let Inst{20-16} = Rt32{4-0};
2900  bits <3> Qd8;
2901  let Inst{5-3} = Qd8{2-0};
2902}
2903class Enc_b5b643 : OpcodeHexagon {
2904  bits <5> Rtt32;
2905  let Inst{20-16} = Rtt32{4-0};
2906  bits <5> Vx32;
2907  let Inst{7-3} = Vx32{4-0};
2908}
2909class Enc_85daf5 : OpcodeHexagon {
2910  bits <5> Vu32;
2911  let Inst{12-8} = Vu32{4-0};
2912  bits <5> Rtt32;
2913  let Inst{20-16} = Rtt32{4-0};
2914  bits <5> Vx32;
2915  let Inst{7-3} = Vx32{4-0};
2916}
2917class Enc_d483b9 : OpcodeHexagon {
2918  bits <1> Ii;
2919  let Inst{5-5} = Ii{0-0};
2920  bits <5> Vuu32;
2921  let Inst{12-8} = Vuu32{4-0};
2922  bits <5> Rt32;
2923  let Inst{20-16} = Rt32{4-0};
2924  bits <5> Vxx32;
2925  let Inst{4-0} = Vxx32{4-0};
2926}
2927class Enc_51635c : OpcodeHexagon {
2928  bits <7> Ii;
2929  let Inst{8-4} = Ii{6-2};
2930  bits <4> Rd16;
2931  let Inst{3-0} = Rd16{3-0};
2932}
2933class Enc_e26546 : OpcodeHexagon {
2934  bits <5> Ii;
2935  let Inst{6-3} = Ii{4-1};
2936  bits <3> Nt8;
2937  let Inst{10-8} = Nt8{2-0};
2938  bits <5> Rx32;
2939  let Inst{20-16} = Rx32{4-0};
2940}
2941class Enc_70fb07 : OpcodeHexagon {
2942  bits <6> Ii;
2943  let Inst{13-8} = Ii{5-0};
2944  bits <5> Rss32;
2945  let Inst{20-16} = Rss32{4-0};
2946  bits <5> Rxx32;
2947  let Inst{4-0} = Rxx32{4-0};
2948}
2949class Enc_6c9ee0 : OpcodeHexagon {
2950  bits <3> Ii;
2951  let Inst{10-8} = Ii{2-0};
2952  bits <5> Rx32;
2953  let Inst{20-16} = Rx32{4-0};
2954}
2955class Enc_72a92d : OpcodeHexagon {
2956  bits <5> Vuu32;
2957  let Inst{12-8} = Vuu32{4-0};
2958  bits <5> Rt32;
2959  let Inst{20-16} = Rt32{4-0};
2960  bits <5> Vxx32;
2961  let Inst{7-3} = Vxx32{4-0};
2962}
2963class Enc_44661f : OpcodeHexagon {
2964  bits <1> Mu2;
2965  let Inst{13-13} = Mu2{0-0};
2966  bits <5> Rx32;
2967  let Inst{20-16} = Rx32{4-0};
2968}
2969class Enc_277737 : OpcodeHexagon {
2970  bits <8> Ii;
2971  let Inst{22-21} = Ii{7-6};
2972  let Inst{13-13} = Ii{5-5};
2973  let Inst{7-5} = Ii{4-2};
2974  bits <5> Ru32;
2975  let Inst{4-0} = Ru32{4-0};
2976  bits <5> Rs32;
2977  let Inst{20-16} = Rs32{4-0};
2978  bits <5> Rd32;
2979  let Inst{12-8} = Rd32{4-0};
2980}
2981class Enc_5c124a : OpcodeHexagon {
2982  bits <19> Ii;
2983  let Inst{26-25} = Ii{18-17};
2984  let Inst{20-16} = Ii{16-12};
2985  let Inst{13-13} = Ii{11-11};
2986  let Inst{7-0} = Ii{10-3};
2987  bits <5> Rtt32;
2988  let Inst{12-8} = Rtt32{4-0};
2989}
2990class Enc_928ca1 : OpcodeHexagon {
2991  bits <1> Mu2;
2992  let Inst{13-13} = Mu2{0-0};
2993  bits <5> Rtt32;
2994  let Inst{12-8} = Rtt32{4-0};
2995  bits <5> Rx32;
2996  let Inst{20-16} = Rx32{4-0};
2997}
2998class Enc_da664b : OpcodeHexagon {
2999  bits <2> Ii;
3000  let Inst{13-13} = Ii{1-1};
3001  let Inst{7-7} = Ii{0-0};
3002  bits <5> Rs32;
3003  let Inst{20-16} = Rs32{4-0};
3004  bits <5> Rt32;
3005  let Inst{12-8} = Rt32{4-0};
3006  bits <5> Rd32;
3007  let Inst{4-0} = Rd32{4-0};
3008}
3009class Enc_7b7ba8 : OpcodeHexagon {
3010  bits <2> Qu4;
3011  let Inst{9-8} = Qu4{1-0};
3012  bits <5> Rt32;
3013  let Inst{20-16} = Rt32{4-0};
3014  bits <5> Vd32;
3015  let Inst{4-0} = Vd32{4-0};
3016}
3017class Enc_47ee5e : OpcodeHexagon {
3018  bits <2> Ii;
3019  let Inst{13-13} = Ii{1-1};
3020  let Inst{7-7} = Ii{0-0};
3021  bits <2> Pv4;
3022  let Inst{6-5} = Pv4{1-0};
3023  bits <5> Rs32;
3024  let Inst{20-16} = Rs32{4-0};
3025  bits <5> Ru32;
3026  let Inst{12-8} = Ru32{4-0};
3027  bits <3> Nt8;
3028  let Inst{2-0} = Nt8{2-0};
3029}
3030class Enc_8bcba4 : OpcodeHexagon {
3031  bits <6> II;
3032  let Inst{5-0} = II{5-0};
3033  bits <5> Rt32;
3034  let Inst{12-8} = Rt32{4-0};
3035  bits <5> Re32;
3036  let Inst{20-16} = Re32{4-0};
3037}
3038class Enc_3a2484 : OpcodeHexagon {
3039  bits <11> Ii;
3040  let Inst{21-20} = Ii{10-9};
3041  let Inst{7-1} = Ii{8-2};
3042  bits <4> Rs16;
3043  let Inst{19-16} = Rs16{3-0};
3044  bits <4> n1;
3045  let Inst{28-28} = n1{3-3};
3046  let Inst{24-23} = n1{2-1};
3047  let Inst{13-13} = n1{0-0};
3048}
3049class Enc_a5ed8a : OpcodeHexagon {
3050  bits <5> Rt32;
3051  let Inst{20-16} = Rt32{4-0};
3052  bits <5> Vd32;
3053  let Inst{4-0} = Vd32{4-0};
3054}
3055class Enc_cb9321 : OpcodeHexagon {
3056  bits <16> Ii;
3057  let Inst{27-21} = Ii{15-9};
3058  let Inst{13-5} = Ii{8-0};
3059  bits <5> Rs32;
3060  let Inst{20-16} = Rs32{4-0};
3061  bits <5> Rd32;
3062  let Inst{4-0} = Rd32{4-0};
3063}
3064class Enc_668704 : OpcodeHexagon {
3065  bits <11> Ii;
3066  let Inst{21-20} = Ii{10-9};
3067  let Inst{7-1} = Ii{8-2};
3068  bits <4> Rs16;
3069  let Inst{19-16} = Rs16{3-0};
3070  bits <5> n1;
3071  let Inst{28-28} = n1{4-4};
3072  let Inst{25-22} = n1{3-0};
3073}
3074class Enc_a7341a : OpcodeHexagon {
3075  bits <5> Vu32;
3076  let Inst{12-8} = Vu32{4-0};
3077  bits <5> Vv32;
3078  let Inst{20-16} = Vv32{4-0};
3079  bits <5> Vx32;
3080  let Inst{4-0} = Vx32{4-0};
3081}
3082class Enc_5eac98 : OpcodeHexagon {
3083  bits <6> Ii;
3084  let Inst{13-8} = Ii{5-0};
3085  bits <5> Rss32;
3086  let Inst{20-16} = Rss32{4-0};
3087  bits <5> Rdd32;
3088  let Inst{4-0} = Rdd32{4-0};
3089}
3090class Enc_02553a : OpcodeHexagon {
3091  bits <7> Ii;
3092  let Inst{11-5} = Ii{6-0};
3093  bits <5> Rs32;
3094  let Inst{20-16} = Rs32{4-0};
3095  bits <2> Pd4;
3096  let Inst{1-0} = Pd4{1-0};
3097}
3098class Enc_acd6ed : OpcodeHexagon {
3099  bits <9> Ii;
3100  let Inst{10-5} = Ii{8-3};
3101  bits <2> Pt4;
3102  let Inst{12-11} = Pt4{1-0};
3103  bits <5> Rs32;
3104  let Inst{20-16} = Rs32{4-0};
3105  bits <5> Rdd32;
3106  let Inst{4-0} = Rdd32{4-0};
3107}
3108class Enc_8e583a : OpcodeHexagon {
3109  bits <11> Ii;
3110  let Inst{21-20} = Ii{10-9};
3111  let Inst{7-1} = Ii{8-2};
3112  bits <4> Rs16;
3113  let Inst{19-16} = Rs16{3-0};
3114  bits <5> n1;
3115  let Inst{28-28} = n1{4-4};
3116  let Inst{25-23} = n1{3-1};
3117  let Inst{13-13} = n1{0-0};
3118}
3119class Enc_334c2b : OpcodeHexagon {
3120  bits <5> Vuu32;
3121  let Inst{12-8} = Vuu32{4-0};
3122  bits <5> Rt32;
3123  let Inst{20-16} = Rt32{4-0};
3124  bits <5> Vd32;
3125  let Inst{7-3} = Vd32{4-0};
3126}
3127class Enc_b886fd : OpcodeHexagon {
3128  bits <5> Ii;
3129  let Inst{6-3} = Ii{4-1};
3130  bits <2> Pv4;
3131  let Inst{1-0} = Pv4{1-0};
3132  bits <5> Rt32;
3133  let Inst{12-8} = Rt32{4-0};
3134  bits <5> Rx32;
3135  let Inst{20-16} = Rx32{4-0};
3136}
3137class Enc_24a7dc : OpcodeHexagon {
3138  bits <5> Vu32;
3139  let Inst{12-8} = Vu32{4-0};
3140  bits <5> Vv32;
3141  let Inst{23-19} = Vv32{4-0};
3142  bits <3> Rt8;
3143  let Inst{18-16} = Rt8{2-0};
3144  bits <5> Vdd32;
3145  let Inst{4-0} = Vdd32{4-0};
3146}
3147class Enc_2d829e : OpcodeHexagon {
3148  bits <14> Ii;
3149  let Inst{10-0} = Ii{13-3};
3150  bits <5> Rs32;
3151  let Inst{20-16} = Rs32{4-0};
3152}
3153class Enc_4f4ed7 : OpcodeHexagon {
3154  bits <18> Ii;
3155  let Inst{26-25} = Ii{17-16};
3156  let Inst{20-16} = Ii{15-11};
3157  let Inst{13-5} = Ii{10-2};
3158  bits <5> Rd32;
3159  let Inst{4-0} = Rd32{4-0};
3160}
3161class Enc_84b2cd : OpcodeHexagon {
3162  bits <8> Ii;
3163  let Inst{12-7} = Ii{7-2};
3164  bits <5> II;
3165  let Inst{4-0} = II{4-0};
3166  bits <5> Rs32;
3167  let Inst{20-16} = Rs32{4-0};
3168}
3169class Enc_8dbdfe : OpcodeHexagon {
3170  bits <8> Ii;
3171  let Inst{13-13} = Ii{7-7};
3172  let Inst{7-3} = Ii{6-2};
3173  bits <2> Pv4;
3174  let Inst{1-0} = Pv4{1-0};
3175  bits <5> Rs32;
3176  let Inst{20-16} = Rs32{4-0};
3177  bits <3> Nt8;
3178  let Inst{10-8} = Nt8{2-0};
3179}
3180class Enc_7dc746 : OpcodeHexagon {
3181  bits <3> Quu8;
3182  let Inst{10-8} = Quu8{2-0};
3183  bits <5> Rt32;
3184  let Inst{20-16} = Rt32{4-0};
3185  bits <3> Qdd8;
3186  let Inst{5-3} = Qdd8{2-0};
3187}
3188class Enc_90cd8b : OpcodeHexagon {
3189  bits <5> Rss32;
3190  let Inst{20-16} = Rss32{4-0};
3191  bits <5> Rd32;
3192  let Inst{4-0} = Rd32{4-0};
3193}
3194class Enc_b8513b : OpcodeHexagon {
3195  bits <5> Vuu32;
3196  let Inst{20-16} = Vuu32{4-0};
3197  bits <5> Vvv32;
3198  let Inst{12-8} = Vvv32{4-0};
3199  bits <5> Vdd32;
3200  let Inst{7-3} = Vdd32{4-0};
3201}
3202class Enc_b3bac4 : OpcodeHexagon {
3203  bits <5> Vu32;
3204  let Inst{12-8} = Vu32{4-0};
3205  bits <5> Rtt32;
3206  let Inst{20-16} = Rtt32{4-0};
3207  bits <5> Vd32;
3208  let Inst{7-3} = Vd32{4-0};
3209}
3210class Enc_bd0b33 : OpcodeHexagon {
3211  bits <10> Ii;
3212  let Inst{21-21} = Ii{9-9};
3213  let Inst{13-5} = Ii{8-0};
3214  bits <5> Rs32;
3215  let Inst{20-16} = Rs32{4-0};
3216  bits <2> Pd4;
3217  let Inst{1-0} = Pd4{1-0};
3218}
3219class Enc_843e80 : OpcodeHexagon {
3220  bits <5> Vu32;
3221  let Inst{12-8} = Vu32{4-0};
3222  bits <5> Rt32;
3223  let Inst{20-16} = Rt32{4-0};
3224  bits <5> Vd32;
3225  let Inst{7-3} = Vd32{4-0};
3226  bits <3> Qxx8;
3227  let Inst{2-0} = Qxx8{2-0};
3228}
3229class Enc_8b8927 : OpcodeHexagon {
3230  bits <5> Rt32;
3231  let Inst{20-16} = Rt32{4-0};
3232  bits <1> Mu2;
3233  let Inst{13-13} = Mu2{0-0};
3234  bits <5> Vv32;
3235  let Inst{4-0} = Vv32{4-0};
3236}
3237class Enc_c7cd90 : OpcodeHexagon {
3238  bits <4> Ii;
3239  let Inst{6-3} = Ii{3-0};
3240  bits <3> Nt8;
3241  let Inst{10-8} = Nt8{2-0};
3242  bits <5> Rx32;
3243  let Inst{20-16} = Rx32{4-0};
3244}
3245class Enc_405228 : OpcodeHexagon {
3246  bits <11> Ii;
3247  let Inst{21-20} = Ii{10-9};
3248  let Inst{7-1} = Ii{8-2};
3249  bits <4> Rs16;
3250  let Inst{19-16} = Rs16{3-0};
3251  bits <3> n1;
3252  let Inst{28-28} = n1{2-2};
3253  let Inst{24-23} = n1{1-0};
3254}
3255class Enc_81ac1d : OpcodeHexagon {
3256  bits <24> Ii;
3257  let Inst{24-16} = Ii{23-15};
3258  let Inst{13-1} = Ii{14-2};
3259}
3260class Enc_395cc4 : OpcodeHexagon {
3261  bits <7> Ii;
3262  let Inst{6-3} = Ii{6-3};
3263  bits <1> Mu2;
3264  let Inst{13-13} = Mu2{0-0};
3265  bits <5> Rtt32;
3266  let Inst{12-8} = Rtt32{4-0};
3267  bits <5> Rx32;
3268  let Inst{20-16} = Rx32{4-0};
3269}
3270class Enc_a51a9a : OpcodeHexagon {
3271  bits <8> Ii;
3272  let Inst{12-8} = Ii{7-3};
3273  let Inst{4-2} = Ii{2-0};
3274}
3275class Enc_d44e31 : OpcodeHexagon {
3276  bits <6> Ii;
3277  let Inst{12-7} = Ii{5-0};
3278  bits <5> Rs32;
3279  let Inst{20-16} = Rs32{4-0};
3280  bits <5> Rt32;
3281  let Inst{4-0} = Rt32{4-0};
3282}
3283class Enc_f77fbc : OpcodeHexagon {
3284  bits <4> Ii;
3285  let Inst{13-13} = Ii{3-3};
3286  let Inst{10-8} = Ii{2-0};
3287  bits <5> Rt32;
3288  let Inst{20-16} = Rt32{4-0};
3289  bits <3> Os8;
3290  let Inst{2-0} = Os8{2-0};
3291}
3292class Enc_d2216a : OpcodeHexagon {
3293  bits <5> Rss32;
3294  let Inst{20-16} = Rss32{4-0};
3295  bits <5> Rtt32;
3296  let Inst{12-8} = Rtt32{4-0};
3297  bits <5> Rd32;
3298  let Inst{4-0} = Rd32{4-0};
3299}
3300class Enc_85bf58 : OpcodeHexagon {
3301  bits <7> Ii;
3302  let Inst{6-3} = Ii{6-3};
3303  bits <5> Rtt32;
3304  let Inst{12-8} = Rtt32{4-0};
3305  bits <5> Rx32;
3306  let Inst{20-16} = Rx32{4-0};
3307}
3308class Enc_71bb9b : OpcodeHexagon {
3309  bits <5> Vu32;
3310  let Inst{12-8} = Vu32{4-0};
3311  bits <5> Vv32;
3312  let Inst{20-16} = Vv32{4-0};
3313  bits <5> Vdd32;
3314  let Inst{4-0} = Vdd32{4-0};
3315}
3316class Enc_52a5dd : OpcodeHexagon {
3317  bits <4> Ii;
3318  let Inst{6-3} = Ii{3-0};
3319  bits <2> Pv4;
3320  let Inst{1-0} = Pv4{1-0};
3321  bits <3> Nt8;
3322  let Inst{10-8} = Nt8{2-0};
3323  bits <5> Rx32;
3324  let Inst{20-16} = Rx32{4-0};
3325}
3326class Enc_5e2823 : OpcodeHexagon {
3327  bits <5> Rs32;
3328  let Inst{20-16} = Rs32{4-0};
3329  bits <5> Rd32;
3330  let Inst{4-0} = Rd32{4-0};
3331}
3332class Enc_28a2dc : OpcodeHexagon {
3333  bits <5> Ii;
3334  let Inst{12-8} = Ii{4-0};
3335  bits <5> Rs32;
3336  let Inst{20-16} = Rs32{4-0};
3337  bits <5> Rx32;
3338  let Inst{4-0} = Rx32{4-0};
3339}
3340class Enc_5138b3 : OpcodeHexagon {
3341  bits <5> Vu32;
3342  let Inst{12-8} = Vu32{4-0};
3343  bits <5> Rt32;
3344  let Inst{20-16} = Rt32{4-0};
3345  bits <5> Vx32;
3346  let Inst{4-0} = Vx32{4-0};
3347}
3348class Enc_84d359 : OpcodeHexagon {
3349  bits <4> Ii;
3350  let Inst{3-0} = Ii{3-0};
3351  bits <4> Rs16;
3352  let Inst{7-4} = Rs16{3-0};
3353}
3354class Enc_e07374 : OpcodeHexagon {
3355  bits <5> Rs32;
3356  let Inst{20-16} = Rs32{4-0};
3357  bits <5> Rtt32;
3358  let Inst{12-8} = Rtt32{4-0};
3359  bits <5> Rd32;
3360  let Inst{4-0} = Rd32{4-0};
3361}
3362class Enc_323f2d : OpcodeHexagon {
3363  bits <6> II;
3364  let Inst{11-8} = II{5-2};
3365  let Inst{6-5} = II{1-0};
3366  bits <5> Rd32;
3367  let Inst{4-0} = Rd32{4-0};
3368  bits <5> Re32;
3369  let Inst{20-16} = Re32{4-0};
3370}
3371class Enc_1a9974 : OpcodeHexagon {
3372  bits <2> Ii;
3373  let Inst{13-13} = Ii{1-1};
3374  let Inst{7-7} = Ii{0-0};
3375  bits <2> Pv4;
3376  let Inst{6-5} = Pv4{1-0};
3377  bits <5> Rs32;
3378  let Inst{20-16} = Rs32{4-0};
3379  bits <5> Ru32;
3380  let Inst{12-8} = Ru32{4-0};
3381  bits <5> Rtt32;
3382  let Inst{4-0} = Rtt32{4-0};
3383}
3384class Enc_9ce456 : OpcodeHexagon {
3385  bits <10> Ii;
3386  let Inst{21-21} = Ii{9-9};
3387  let Inst{13-8} = Ii{8-3};
3388  let Inst{2-0} = Ii{2-0};
3389  bits <5> Vss32;
3390  let Inst{7-3} = Vss32{4-0};
3391  bits <5> Rx32;
3392  let Inst{20-16} = Rx32{4-0};
3393}
3394class Enc_5de85f : OpcodeHexagon {
3395  bits <11> Ii;
3396  let Inst{21-20} = Ii{10-9};
3397  let Inst{7-1} = Ii{8-2};
3398  bits <5> Rt32;
3399  let Inst{12-8} = Rt32{4-0};
3400  bits <3> Ns8;
3401  let Inst{18-16} = Ns8{2-0};
3402}
3403class Enc_dd766a : OpcodeHexagon {
3404  bits <5> Vu32;
3405  let Inst{12-8} = Vu32{4-0};
3406  bits <5> Vdd32;
3407  let Inst{4-0} = Vdd32{4-0};
3408}
3409class Enc_0b51ce : OpcodeHexagon {
3410  bits <3> Ii;
3411  let Inst{10-8} = Ii{2-0};
3412  bits <2> Qv4;
3413  let Inst{12-11} = Qv4{1-0};
3414  bits <5> Vs32;
3415  let Inst{4-0} = Vs32{4-0};
3416  bits <5> Rx32;
3417  let Inst{20-16} = Rx32{4-0};
3418}
3419class Enc_b5e54d : OpcodeHexagon {
3420  bits <5> Vu32;
3421  let Inst{12-8} = Vu32{4-0};
3422  bits <5> Rs32;
3423  let Inst{20-16} = Rs32{4-0};
3424  bits <5> Rdd32;
3425  let Inst{4-0} = Rdd32{4-0};
3426}
3427class Enc_b4e6cf : OpcodeHexagon {
3428  bits <10> Ii;
3429  let Inst{21-21} = Ii{9-9};
3430  let Inst{13-5} = Ii{8-0};
3431  bits <5> Ru32;
3432  let Inst{4-0} = Ru32{4-0};
3433  bits <5> Rx32;
3434  let Inst{20-16} = Rx32{4-0};
3435}
3436class Enc_44215c : OpcodeHexagon {
3437  bits <6> Ii;
3438  let Inst{17-16} = Ii{5-4};
3439  let Inst{6-3} = Ii{3-0};
3440  bits <2> Pv4;
3441  let Inst{1-0} = Pv4{1-0};
3442  bits <3> Nt8;
3443  let Inst{10-8} = Nt8{2-0};
3444}
3445class Enc_0aa344 : OpcodeHexagon {
3446  bits <5> Gss32;
3447  let Inst{20-16} = Gss32{4-0};
3448  bits <5> Rdd32;
3449  let Inst{4-0} = Rdd32{4-0};
3450}
3451class Enc_a21d47 : OpcodeHexagon {
3452  bits <6> Ii;
3453  let Inst{10-5} = Ii{5-0};
3454  bits <2> Pt4;
3455  let Inst{12-11} = Pt4{1-0};
3456  bits <5> Rs32;
3457  let Inst{20-16} = Rs32{4-0};
3458  bits <5> Rd32;
3459  let Inst{4-0} = Rd32{4-0};
3460}
3461class Enc_cc449f : OpcodeHexagon {
3462  bits <4> Ii;
3463  let Inst{6-3} = Ii{3-0};
3464  bits <2> Pv4;
3465  let Inst{1-0} = Pv4{1-0};
3466  bits <5> Rt32;
3467  let Inst{12-8} = Rt32{4-0};
3468  bits <5> Rx32;
3469  let Inst{20-16} = Rx32{4-0};
3470}
3471class Enc_645d54 : OpcodeHexagon {
3472  bits <2> Ii;
3473  let Inst{13-13} = Ii{1-1};
3474  let Inst{5-5} = Ii{0-0};
3475  bits <5> Rss32;
3476  let Inst{20-16} = Rss32{4-0};
3477  bits <5> Rt32;
3478  let Inst{12-8} = Rt32{4-0};
3479  bits <5> Rdd32;
3480  let Inst{4-0} = Rdd32{4-0};
3481}
3482class Enc_b5d5a7 : OpcodeHexagon {
3483  bits <16> Ii;
3484  let Inst{21-21} = Ii{15-15};
3485  let Inst{13-8} = Ii{14-9};
3486  let Inst{2-0} = Ii{8-6};
3487  bits <5> Rt32;
3488  let Inst{20-16} = Rt32{4-0};
3489  bits <5> Vs32;
3490  let Inst{7-3} = Vs32{4-0};
3491}
3492class Enc_667b39 : OpcodeHexagon {
3493  bits <5> Css32;
3494  let Inst{20-16} = Css32{4-0};
3495  bits <5> Rdd32;
3496  let Inst{4-0} = Rdd32{4-0};
3497}
3498class Enc_927852 : OpcodeHexagon {
3499  bits <5> Rss32;
3500  let Inst{20-16} = Rss32{4-0};
3501  bits <5> Rt32;
3502  let Inst{12-8} = Rt32{4-0};
3503  bits <5> Rdd32;
3504  let Inst{4-0} = Rdd32{4-0};
3505}
3506class Enc_163a3c : OpcodeHexagon {
3507  bits <7> Ii;
3508  let Inst{12-7} = Ii{6-1};
3509  bits <5> Rs32;
3510  let Inst{20-16} = Rs32{4-0};
3511  bits <5> Rt32;
3512  let Inst{4-0} = Rt32{4-0};
3513}
3514class Enc_b087ac : OpcodeHexagon {
3515  bits <5> Vu32;
3516  let Inst{12-8} = Vu32{4-0};
3517  bits <5> Rt32;
3518  let Inst{20-16} = Rt32{4-0};
3519  bits <5> Vd32;
3520  let Inst{4-0} = Vd32{4-0};
3521}
3522class Enc_b1e1fb : OpcodeHexagon {
3523  bits <11> Ii;
3524  let Inst{21-20} = Ii{10-9};
3525  let Inst{7-1} = Ii{8-2};
3526  bits <4> Rs16;
3527  let Inst{19-16} = Rs16{3-0};
3528  bits <5> n1;
3529  let Inst{28-28} = n1{4-4};
3530  let Inst{25-23} = n1{3-1};
3531  let Inst{8-8} = n1{0-0};
3532}
3533class Enc_1f19b5 : OpcodeHexagon {
3534  bits <5> Ii;
3535  let Inst{9-5} = Ii{4-0};
3536  bits <5> Rss32;
3537  let Inst{20-16} = Rss32{4-0};
3538  bits <2> Pd4;
3539  let Inst{1-0} = Pd4{1-0};
3540}
3541class Enc_b8c967 : OpcodeHexagon {
3542  bits <8> Ii;
3543  let Inst{12-5} = Ii{7-0};
3544  bits <5> Rs32;
3545  let Inst{20-16} = Rs32{4-0};
3546  bits <5> Rd32;
3547  let Inst{4-0} = Rd32{4-0};
3548}
3549class Enc_f106e0 : OpcodeHexagon {
3550  bits <5> Vu32;
3551  let Inst{20-16} = Vu32{4-0};
3552  bits <5> Vv32;
3553  let Inst{8-4} = Vv32{4-0};
3554  bits <5> Vt32;
3555  let Inst{13-9} = Vt32{4-0};
3556  bits <4> Vdd16;
3557  let Inst{3-0} = Vdd16{3-0};
3558}
3559class Enc_fb6577 : OpcodeHexagon {
3560  bits <2> Pu4;
3561  let Inst{9-8} = Pu4{1-0};
3562  bits <5> Rs32;
3563  let Inst{20-16} = Rs32{4-0};
3564  bits <5> Rd32;
3565  let Inst{4-0} = Rd32{4-0};
3566}
3567class Enc_37c406 : OpcodeHexagon {
3568  bits <5> Vu32;
3569  let Inst{20-16} = Vu32{4-0};
3570  bits <5> Vv32;
3571  let Inst{12-8} = Vv32{4-0};
3572  bits <3> Rt8;
3573  let Inst{2-0} = Rt8{2-0};
3574  bits <4> Vdd16;
3575  let Inst{7-4} = Vdd16{3-0};
3576}
3577class Enc_403871 : OpcodeHexagon {
3578  bits <5> Rx32;
3579  let Inst{20-16} = Rx32{4-0};
3580}
3581class Enc_2bae10 : OpcodeHexagon {
3582  bits <4> Ii;
3583  let Inst{10-8} = Ii{3-1};
3584  bits <4> Rs16;
3585  let Inst{7-4} = Rs16{3-0};
3586  bits <4> Rd16;
3587  let Inst{3-0} = Rd16{3-0};
3588}
3589class Enc_f3adb6 : OpcodeHexagon {
3590  bits <16> Ii;
3591  let Inst{21-21} = Ii{15-15};
3592  let Inst{13-8} = Ii{14-9};
3593  let Inst{2-0} = Ii{8-6};
3594  bits <5> Vdd32;
3595  let Inst{7-3} = Vdd32{4-0};
3596  bits <5> Rx32;
3597  let Inst{20-16} = Rx32{4-0};
3598}
3599class Enc_aac08c : OpcodeHexagon {
3600  bits <5> Vu32;
3601  let Inst{20-16} = Vu32{4-0};
3602  bits <5> Vx32;
3603  let Inst{7-3} = Vx32{4-0};
3604}
3605class Enc_c4dc92 : OpcodeHexagon {
3606  bits <2> Qv4;
3607  let Inst{23-22} = Qv4{1-0};
3608  bits <5> Vu32;
3609  let Inst{12-8} = Vu32{4-0};
3610  bits <5> Vd32;
3611  let Inst{4-0} = Vd32{4-0};
3612}
3613class Enc_03833b : OpcodeHexagon {
3614  bits <5> Rss32;
3615  let Inst{20-16} = Rss32{4-0};
3616  bits <5> Rt32;
3617  let Inst{12-8} = Rt32{4-0};
3618  bits <2> Pd4;
3619  let Inst{1-0} = Pd4{1-0};
3620}
3621class Enc_dbd70c : OpcodeHexagon {
3622  bits <5> Rss32;
3623  let Inst{20-16} = Rss32{4-0};
3624  bits <5> Rtt32;
3625  let Inst{12-8} = Rtt32{4-0};
3626  bits <2> Pu4;
3627  let Inst{6-5} = Pu4{1-0};
3628  bits <5> Rdd32;
3629  let Inst{4-0} = Rdd32{4-0};
3630}
3631class Enc_f6fe0b : OpcodeHexagon {
3632  bits <11> Ii;
3633  let Inst{21-20} = Ii{10-9};
3634  let Inst{7-1} = Ii{8-2};
3635  bits <4> Rs16;
3636  let Inst{19-16} = Rs16{3-0};
3637  bits <6> n1;
3638  let Inst{28-28} = n1{5-5};
3639  let Inst{24-22} = n1{4-2};
3640  let Inst{13-13} = n1{1-1};
3641  let Inst{8-8} = n1{0-0};
3642}
3643class Enc_9e2e1c : OpcodeHexagon {
3644  bits <5> Ii;
3645  let Inst{8-5} = Ii{4-1};
3646  bits <1> Mu2;
3647  let Inst{13-13} = Mu2{0-0};
3648  bits <5> Ryy32;
3649  let Inst{4-0} = Ryy32{4-0};
3650  bits <5> Rx32;
3651  let Inst{20-16} = Rx32{4-0};
3652}
3653class Enc_8df4be : OpcodeHexagon {
3654  bits <17> Ii;
3655  let Inst{26-25} = Ii{16-15};
3656  let Inst{20-16} = Ii{14-10};
3657  let Inst{13-5} = Ii{9-1};
3658  bits <5> Rd32;
3659  let Inst{4-0} = Rd32{4-0};
3660}
3661class Enc_66bce1 : OpcodeHexagon {
3662  bits <11> Ii;
3663  let Inst{21-20} = Ii{10-9};
3664  let Inst{7-1} = Ii{8-2};
3665  bits <4> Rs16;
3666  let Inst{19-16} = Rs16{3-0};
3667  bits <4> Rd16;
3668  let Inst{11-8} = Rd16{3-0};
3669}
3670class Enc_b8309d : OpcodeHexagon {
3671  bits <9> Ii;
3672  let Inst{8-3} = Ii{8-3};
3673  bits <3> Rtt8;
3674  let Inst{2-0} = Rtt8{2-0};
3675}
3676class Enc_5e8512 : OpcodeHexagon {
3677  bits <5> Vu32;
3678  let Inst{12-8} = Vu32{4-0};
3679  bits <5> Rt32;
3680  let Inst{20-16} = Rt32{4-0};
3681  bits <5> Vxx32;
3682  let Inst{4-0} = Vxx32{4-0};
3683}
3684class Enc_4f677b : OpcodeHexagon {
3685  bits <2> Ii;
3686  let Inst{13-13} = Ii{1-1};
3687  let Inst{7-7} = Ii{0-0};
3688  bits <6> II;
3689  let Inst{11-8} = II{5-2};
3690  let Inst{6-5} = II{1-0};
3691  bits <5> Rt32;
3692  let Inst{20-16} = Rt32{4-0};
3693  bits <5> Rd32;
3694  let Inst{4-0} = Rd32{4-0};
3695}
3696class Enc_3d920a : OpcodeHexagon {
3697  bits <6> Ii;
3698  let Inst{8-5} = Ii{5-2};
3699  bits <5> Rd32;
3700  let Inst{4-0} = Rd32{4-0};
3701  bits <5> Rx32;
3702  let Inst{20-16} = Rx32{4-0};
3703}
3704class Enc_e83554 : OpcodeHexagon {
3705  bits <5> Ii;
3706  let Inst{8-5} = Ii{4-1};
3707  bits <1> Mu2;
3708  let Inst{13-13} = Mu2{0-0};
3709  bits <5> Rd32;
3710  let Inst{4-0} = Rd32{4-0};
3711  bits <5> Rx32;
3712  let Inst{20-16} = Rx32{4-0};
3713}
3714class Enc_ed48be : OpcodeHexagon {
3715  bits <2> Ii;
3716  let Inst{6-5} = Ii{1-0};
3717  bits <3> Rdd8;
3718  let Inst{2-0} = Rdd8{2-0};
3719}
3720class Enc_f8c1c4 : OpcodeHexagon {
3721  bits <2> Pv4;
3722  let Inst{12-11} = Pv4{1-0};
3723  bits <1> Mu2;
3724  let Inst{13-13} = Mu2{0-0};
3725  bits <5> Vd32;
3726  let Inst{4-0} = Vd32{4-0};
3727  bits <5> Rx32;
3728  let Inst{20-16} = Rx32{4-0};
3729}
3730class Enc_1aa186 : OpcodeHexagon {
3731  bits <5> Rss32;
3732  let Inst{20-16} = Rss32{4-0};
3733  bits <5> Rt32;
3734  let Inst{12-8} = Rt32{4-0};
3735  bits <5> Rxx32;
3736  let Inst{4-0} = Rxx32{4-0};
3737}
3738class Enc_134437 : OpcodeHexagon {
3739  bits <2> Qs4;
3740  let Inst{9-8} = Qs4{1-0};
3741  bits <2> Qt4;
3742  let Inst{23-22} = Qt4{1-0};
3743  bits <2> Qd4;
3744  let Inst{1-0} = Qd4{1-0};
3745}
3746class Enc_33f8ba : OpcodeHexagon {
3747  bits <8> Ii;
3748  let Inst{12-8} = Ii{7-3};
3749  let Inst{4-2} = Ii{2-0};
3750  bits <5> Rx32;
3751  let Inst{20-16} = Rx32{4-0};
3752}
3753class Enc_97d666 : OpcodeHexagon {
3754  bits <4> Rs16;
3755  let Inst{7-4} = Rs16{3-0};
3756  bits <4> Rd16;
3757  let Inst{3-0} = Rd16{3-0};
3758}
3759class Enc_f82eaf : OpcodeHexagon {
3760  bits <8> Ii;
3761  let Inst{10-5} = Ii{7-2};
3762  bits <2> Pt4;
3763  let Inst{12-11} = Pt4{1-0};
3764  bits <5> Rs32;
3765  let Inst{20-16} = Rs32{4-0};
3766  bits <5> Rd32;
3767  let Inst{4-0} = Rd32{4-0};
3768}
3769class Enc_57e245 : OpcodeHexagon {
3770  bits <5> Vu32;
3771  let Inst{20-16} = Vu32{4-0};
3772  bits <3> Rt8;
3773  let Inst{2-0} = Rt8{2-0};
3774  bits <5> Vdd32;
3775  let Inst{7-3} = Vdd32{4-0};
3776  bits <5> Vy32;
3777  let Inst{12-8} = Vy32{4-0};
3778}
3779class Enc_69d63b : OpcodeHexagon {
3780  bits <11> Ii;
3781  let Inst{21-20} = Ii{10-9};
3782  let Inst{7-1} = Ii{8-2};
3783  bits <3> Ns8;
3784  let Inst{18-16} = Ns8{2-0};
3785}
3786class Enc_f79415 : OpcodeHexagon {
3787  bits <2> Ii;
3788  let Inst{13-13} = Ii{1-1};
3789  let Inst{6-6} = Ii{0-0};
3790  bits <6> II;
3791  let Inst{5-0} = II{5-0};
3792  bits <5> Ru32;
3793  let Inst{20-16} = Ru32{4-0};
3794  bits <5> Rtt32;
3795  let Inst{12-8} = Rtt32{4-0};
3796}
3797class Enc_ce6828 : OpcodeHexagon {
3798  bits <14> Ii;
3799  let Inst{26-25} = Ii{13-12};
3800  let Inst{13-13} = Ii{11-11};
3801  let Inst{7-0} = Ii{10-3};
3802  bits <5> Rs32;
3803  let Inst{20-16} = Rs32{4-0};
3804  bits <5> Rtt32;
3805  let Inst{12-8} = Rtt32{4-0};
3806}
3807class Enc_800e04 : OpcodeHexagon {
3808  bits <11> Ii;
3809  let Inst{21-20} = Ii{10-9};
3810  let Inst{7-1} = Ii{8-2};
3811  bits <4> Rs16;
3812  let Inst{19-16} = Rs16{3-0};
3813  bits <6> n1;
3814  let Inst{28-28} = n1{5-5};
3815  let Inst{25-22} = n1{4-1};
3816  let Inst{13-13} = n1{0-0};
3817}
3818class Enc_ad1831 : OpcodeHexagon {
3819  bits <16> Ii;
3820  let Inst{26-25} = Ii{15-14};
3821  let Inst{20-16} = Ii{13-9};
3822  let Inst{13-13} = Ii{8-8};
3823  let Inst{7-0} = Ii{7-0};
3824  bits <3> Nt8;
3825  let Inst{10-8} = Nt8{2-0};
3826}
3827class Enc_0fa531 : OpcodeHexagon {
3828  bits <15> Ii;
3829  let Inst{21-21} = Ii{14-14};
3830  let Inst{13-13} = Ii{13-13};
3831  let Inst{11-1} = Ii{12-2};
3832  bits <5> Rs32;
3833  let Inst{20-16} = Rs32{4-0};
3834}
3835class Enc_7eaeb6 : OpcodeHexagon {
3836  bits <6> Ii;
3837  let Inst{6-3} = Ii{5-2};
3838  bits <2> Pv4;
3839  let Inst{1-0} = Pv4{1-0};
3840  bits <5> Rt32;
3841  let Inst{12-8} = Rt32{4-0};
3842  bits <5> Rx32;
3843  let Inst{20-16} = Rx32{4-0};
3844}
3845class Enc_274a4c : OpcodeHexagon {
3846  bits <5> Vu32;
3847  let Inst{20-16} = Vu32{4-0};
3848  bits <3> Rt8;
3849  let Inst{2-0} = Rt8{2-0};
3850  bits <5> Vx32;
3851  let Inst{7-3} = Vx32{4-0};
3852  bits <5> Vy32;
3853  let Inst{12-8} = Vy32{4-0};
3854}
3855class Enc_aceeef : OpcodeHexagon {
3856  bits <5> Vu32;
3857  let Inst{12-8} = Vu32{4-0};
3858  bits <5> Rt32;
3859  let Inst{20-16} = Rt32{4-0};
3860  bits <5> Vdd32;
3861  let Inst{7-3} = Vdd32{4-0};
3862}
3863class Enc_f55a0c : OpcodeHexagon {
3864  bits <6> Ii;
3865  let Inst{11-8} = Ii{5-2};
3866  bits <4> Rs16;
3867  let Inst{7-4} = Rs16{3-0};
3868  bits <4> Rt16;
3869  let Inst{3-0} = Rt16{3-0};
3870}
3871class Enc_f20719 : OpcodeHexagon {
3872  bits <7> Ii;
3873  let Inst{12-7} = Ii{6-1};
3874  bits <6> II;
3875  let Inst{13-13} = II{5-5};
3876  let Inst{4-0} = II{4-0};
3877  bits <2> Pv4;
3878  let Inst{6-5} = Pv4{1-0};
3879  bits <5> Rs32;
3880  let Inst{20-16} = Rs32{4-0};
3881}
3882class Enc_eafd18 : OpcodeHexagon {
3883  bits <5> II;
3884  let Inst{12-8} = II{4-0};
3885  bits <11> Ii;
3886  let Inst{21-20} = Ii{10-9};
3887  let Inst{7-1} = Ii{8-2};
3888  bits <3> Ns8;
3889  let Inst{18-16} = Ns8{2-0};
3890}
3891class Enc_7b523d : OpcodeHexagon {
3892  bits <5> Vu32;
3893  let Inst{12-8} = Vu32{4-0};
3894  bits <5> Vv32;
3895  let Inst{23-19} = Vv32{4-0};
3896  bits <3> Rt8;
3897  let Inst{18-16} = Rt8{2-0};
3898  bits <5> Vxx32;
3899  let Inst{4-0} = Vxx32{4-0};
3900}
3901class Enc_c39a8b : OpcodeHexagon {
3902  bits <16> Ii;
3903  let Inst{21-21} = Ii{15-15};
3904  let Inst{13-8} = Ii{14-9};
3905  let Inst{2-0} = Ii{8-6};
3906  bits <5> Rt32;
3907  let Inst{20-16} = Rt32{4-0};
3908  bits <5> Vss32;
3909  let Inst{7-3} = Vss32{4-0};
3910}
3911class Enc_47ef61 : OpcodeHexagon {
3912  bits <3> Ii;
3913  let Inst{7-5} = Ii{2-0};
3914  bits <5> Rt32;
3915  let Inst{12-8} = Rt32{4-0};
3916  bits <5> Rs32;
3917  let Inst{20-16} = Rs32{4-0};
3918  bits <5> Rd32;
3919  let Inst{4-0} = Rd32{4-0};
3920}
3921class Enc_cc857d : OpcodeHexagon {
3922  bits <5> Vuu32;
3923  let Inst{12-8} = Vuu32{4-0};
3924  bits <5> Rt32;
3925  let Inst{20-16} = Rt32{4-0};
3926  bits <5> Vx32;
3927  let Inst{4-0} = Vx32{4-0};
3928}
3929class Enc_7fa7f6 : OpcodeHexagon {
3930  bits <6> II;
3931  let Inst{11-8} = II{5-2};
3932  let Inst{6-5} = II{1-0};
3933  bits <5> Rdd32;
3934  let Inst{4-0} = Rdd32{4-0};
3935  bits <5> Re32;
3936  let Inst{20-16} = Re32{4-0};
3937}
3938class Enc_0f8bab : OpcodeHexagon {
3939  bits <5> Vu32;
3940  let Inst{12-8} = Vu32{4-0};
3941  bits <5> Rt32;
3942  let Inst{20-16} = Rt32{4-0};
3943  bits <2> Qd4;
3944  let Inst{1-0} = Qd4{1-0};
3945}
3946class Enc_7eb485 : OpcodeHexagon {
3947  bits <2> Ii;
3948  let Inst{13-13} = Ii{1-1};
3949  let Inst{6-6} = Ii{0-0};
3950  bits <6> II;
3951  let Inst{5-0} = II{5-0};
3952  bits <5> Ru32;
3953  let Inst{20-16} = Ru32{4-0};
3954  bits <3> Nt8;
3955  let Inst{10-8} = Nt8{2-0};
3956}
3957class Enc_864a5a : OpcodeHexagon {
3958  bits <9> Ii;
3959  let Inst{12-8} = Ii{8-4};
3960  let Inst{4-3} = Ii{3-2};
3961  bits <5> Rs32;
3962  let Inst{20-16} = Rs32{4-0};
3963}
3964class Enc_c2b48e : OpcodeHexagon {
3965  bits <5> Rs32;
3966  let Inst{20-16} = Rs32{4-0};
3967  bits <5> Rt32;
3968  let Inst{12-8} = Rt32{4-0};
3969  bits <2> Pd4;
3970  let Inst{1-0} = Pd4{1-0};
3971}
3972class Enc_8c6530 : OpcodeHexagon {
3973  bits <5> Rtt32;
3974  let Inst{12-8} = Rtt32{4-0};
3975  bits <5> Rss32;
3976  let Inst{20-16} = Rss32{4-0};
3977  bits <2> Pu4;
3978  let Inst{6-5} = Pu4{1-0};
3979  bits <5> Rdd32;
3980  let Inst{4-0} = Rdd32{4-0};
3981}
3982class Enc_448f7f : OpcodeHexagon {
3983  bits <11> Ii;
3984  let Inst{26-25} = Ii{10-9};
3985  let Inst{13-13} = Ii{8-8};
3986  let Inst{7-0} = Ii{7-0};
3987  bits <5> Rs32;
3988  let Inst{20-16} = Rs32{4-0};
3989  bits <5> Rt32;
3990  let Inst{12-8} = Rt32{4-0};
3991}
3992class Enc_da8d43 : OpcodeHexagon {
3993  bits <6> Ii;
3994  let Inst{13-13} = Ii{5-5};
3995  let Inst{7-3} = Ii{4-0};
3996  bits <2> Pv4;
3997  let Inst{1-0} = Pv4{1-0};
3998  bits <5> Rs32;
3999  let Inst{20-16} = Rs32{4-0};
4000  bits <5> Rt32;
4001  let Inst{12-8} = Rt32{4-0};
4002}
4003class Enc_a6ce9c : OpcodeHexagon {
4004  bits <6> Ii;
4005  let Inst{3-0} = Ii{5-2};
4006  bits <4> Rs16;
4007  let Inst{7-4} = Rs16{3-0};
4008}
4009class Enc_eca7c8 : OpcodeHexagon {
4010  bits <2> Ii;
4011  let Inst{13-13} = Ii{1-1};
4012  let Inst{7-7} = Ii{0-0};
4013  bits <5> Rs32;
4014  let Inst{20-16} = Rs32{4-0};
4015  bits <5> Ru32;
4016  let Inst{12-8} = Ru32{4-0};
4017  bits <5> Rt32;
4018  let Inst{4-0} = Rt32{4-0};
4019}
4020class Enc_598f6c : OpcodeHexagon {
4021  bits <5> Rtt32;
4022  let Inst{12-8} = Rtt32{4-0};
4023}
4024class Enc_41dcc3 : OpcodeHexagon {
4025  bits <5> Rt32;
4026  let Inst{20-16} = Rt32{4-0};
4027  bits <5> Vdd32;
4028  let Inst{7-3} = Vdd32{4-0};
4029}
4030class Enc_4b39e4 : OpcodeHexagon {
4031  bits <3> Ii;
4032  let Inst{7-5} = Ii{2-0};
4033  bits <5> Vu32;
4034  let Inst{12-8} = Vu32{4-0};
4035  bits <5> Vv32;
4036  let Inst{20-16} = Vv32{4-0};
4037  bits <5> Vdd32;
4038  let Inst{4-0} = Vdd32{4-0};
4039}
4040