1 //===-- HexagonHazardRecognizer.cpp - Hexagon Post RA Hazard Recognizer ---===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the hazard recognizer for scheduling on Hexagon.
11 // Use a DFA based hazard recognizer.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "HexagonHazardRecognizer.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineOperand.h"
19 #include "llvm/CodeGen/ScheduleDAG.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include <cassert>
23
24 using namespace llvm;
25
26 #define DEBUG_TYPE "post-RA-sched"
27
Reset()28 void HexagonHazardRecognizer::Reset() {
29 LLVM_DEBUG(dbgs() << "Reset hazard recognizer\n");
30 Resources->clearResources();
31 PacketNum = 0;
32 UsesDotCur = nullptr;
33 DotCurPNum = -1;
34 UsesLoad = false;
35 PrefVectorStoreNew = nullptr;
36 RegDefs.clear();
37 }
38
39 ScheduleHazardRecognizer::HazardType
getHazardType(SUnit * SU,int stalls)40 HexagonHazardRecognizer::getHazardType(SUnit *SU, int stalls) {
41 MachineInstr *MI = SU->getInstr();
42 if (!MI || TII->isZeroCost(MI->getOpcode()))
43 return NoHazard;
44
45 if (!Resources->canReserveResources(*MI)) {
46 LLVM_DEBUG(dbgs() << "*** Hazard in cycle " << PacketNum << ", " << *MI);
47 HazardType RetVal = Hazard;
48 if (TII->mayBeNewStore(*MI)) {
49 // Make sure the register to be stored is defined by an instruction in the
50 // packet.
51 MachineOperand &MO = MI->getOperand(MI->getNumOperands() - 1);
52 if (!MO.isReg() || RegDefs.count(MO.getReg()) == 0)
53 return Hazard;
54 // The .new store version uses different resources so check if it
55 // causes a hazard.
56 MachineFunction *MF = MI->getParent()->getParent();
57 MachineInstr *NewMI =
58 MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)),
59 MI->getDebugLoc());
60 if (Resources->canReserveResources(*NewMI))
61 RetVal = NoHazard;
62 LLVM_DEBUG(dbgs() << "*** Try .new version? " << (RetVal == NoHazard)
63 << "\n");
64 MF->DeleteMachineInstr(NewMI);
65 }
66 return RetVal;
67 }
68
69 if (SU == UsesDotCur && DotCurPNum != (int)PacketNum) {
70 LLVM_DEBUG(dbgs() << "*** .cur Hazard in cycle " << PacketNum << ", "
71 << *MI);
72 return Hazard;
73 }
74
75 return NoHazard;
76 }
77
AdvanceCycle()78 void HexagonHazardRecognizer::AdvanceCycle() {
79 LLVM_DEBUG(dbgs() << "Advance cycle, clear state\n");
80 Resources->clearResources();
81 if (DotCurPNum != -1 && DotCurPNum != (int)PacketNum) {
82 UsesDotCur = nullptr;
83 DotCurPNum = -1;
84 }
85 UsesLoad = false;
86 PrefVectorStoreNew = nullptr;
87 PacketNum++;
88 RegDefs.clear();
89 }
90
91 /// Handle the cases when we prefer one instruction over another. Case 1 - we
92 /// prefer not to generate multiple loads in the packet to avoid a potential
93 /// bank conflict. Case 2 - if a packet contains a dot cur instruction, then we
94 /// prefer the instruction that can use the dot cur result. However, if the use
95 /// is not scheduled in the same packet, then prefer other instructions in the
96 /// subsequent packet. Case 3 - we prefer a vector store that can be converted
97 /// to a .new store. The packetizer will not generate the .new store if the
98 /// store doesn't have resources to fit in the packet (but the .new store may
99 /// have resources). We attempt to schedule the store as soon as possible to
100 /// help packetize the two instructions together.
ShouldPreferAnother(SUnit * SU)101 bool HexagonHazardRecognizer::ShouldPreferAnother(SUnit *SU) {
102 if (PrefVectorStoreNew != nullptr && PrefVectorStoreNew != SU)
103 return true;
104 if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad())
105 return true;
106 return UsesDotCur && ((SU == UsesDotCur) ^ (DotCurPNum == (int)PacketNum));
107 }
108
EmitInstruction(SUnit * SU)109 void HexagonHazardRecognizer::EmitInstruction(SUnit *SU) {
110 MachineInstr *MI = SU->getInstr();
111 if (!MI)
112 return;
113
114 // Keep the set of definitions for each packet, which is used to determine
115 // if a .new can be used.
116 for (const MachineOperand &MO : MI->operands())
117 if (MO.isReg() && MO.isDef() && !MO.isImplicit())
118 RegDefs.insert(MO.getReg());
119
120 if (TII->isZeroCost(MI->getOpcode()))
121 return;
122
123 if (!Resources->canReserveResources(*MI)) {
124 // It must be a .new store since other instructions must be able to be
125 // reserved at this point.
126 assert(TII->mayBeNewStore(*MI) && "Expecting .new store");
127 MachineFunction *MF = MI->getParent()->getParent();
128 MachineInstr *NewMI =
129 MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)),
130 MI->getDebugLoc());
131 assert(Resources->canReserveResources(*NewMI));
132 Resources->reserveResources(*NewMI);
133 MF->DeleteMachineInstr(NewMI);
134 }
135 else
136 Resources->reserveResources(*MI);
137 LLVM_DEBUG(dbgs() << " Add instruction " << *MI);
138
139 // When scheduling a dot cur instruction, check if there is an instruction
140 // that can use the dot cur in the same packet. If so, we'll attempt to
141 // schedule it before other instructions. We only do this if the load has a
142 // single zero-latency use.
143 if (TII->mayBeCurLoad(*MI))
144 for (auto &S : SU->Succs)
145 if (S.isAssignedRegDep() && S.getLatency() == 0 &&
146 S.getSUnit()->NumPredsLeft == 1) {
147 UsesDotCur = S.getSUnit();
148 DotCurPNum = PacketNum;
149 break;
150 }
151 if (SU == UsesDotCur) {
152 UsesDotCur = nullptr;
153 DotCurPNum = -1;
154 }
155
156 UsesLoad = MI->mayLoad();
157
158 if (TII->isHVXVec(*MI) && !MI->mayLoad() && !MI->mayStore())
159 for (auto &S : SU->Succs)
160 if (S.isAssignedRegDep() && S.getLatency() == 0 &&
161 TII->mayBeNewStore(*S.getSUnit()->getInstr()) &&
162 Resources->canReserveResources(*S.getSUnit()->getInstr())) {
163 PrefVectorStoreNew = S.getSUnit();
164 break;
165 }
166 }
167