1//=-HexagonScheduleV60.td - HexagonV60 Scheduling Definitions *- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10 11// There are four SLOTS (four parallel pipelines) in Hexagon V60 machine. 12// This file describes that machine information. 13// 14// |===========|==================================================| 15// | PIPELINE | Instruction Classes | 16// |===========|==================================================| 17// | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM | 18// |-----------|--------------------------------------------------| 19// | SLOT1 | LD ST ALU32 | 20// |-----------|--------------------------------------------------| 21// | SLOT2 | XTYPE ALU32 J JR | 22// |-----------|--------------------------------------------------| 23// | SLOT3 | XTYPE ALU32 J CR | 24// |===========|==================================================| 25// 26// 27// In addition to using the above SLOTS, there are also six vector pipelines 28// in the CVI co-processor in the Hexagon V60 machine. 29// 30// |=========| |=========| |=========| |=========| |=========| |=========| 31// SLOT | CVI_LD | |CVI_MPY3 | |CVI_MPY2 | |CVI_SHIFT| |CVI_XLANE| | CVI_ST | 32// ==== |=========| |=========| |=========| |=========| |=========| |=========| 33// S0-3 | | | CVI_VA | | CVI_VA | | CVI_VA | | CVI_VA | | | 34// S2-3 | | | CVI_VX | | CVI_VX | | | | | | | 35// S0-3 | | | | | | | | | CVI_VP | | | 36// S0-3 | | | | | | | CVI_VS | | | | | 37// S0-1 |(CVI_LD) | | CVI_LD | | CVI_LD | | CVI_LD | | CVI_LD | | | 38// S0-1 |(C*TMP_LD) | | | | | | | | | | 39// S01 |(C*_LDU) | | | | | | | | C*_LDU | | | 40// S0 | | | CVI_ST | | CVI_ST | | CVI_ST | | CVI_ST | |(CVI_ST) | 41// S0 | | | | | | | | | | |(C*TMP_ST) 42// S01 | | | | | | | | | VSTU | |(C*_STU) | 43// |=========| |=========| |=========| |=========| |=========| |=========| 44// |=====================| |=====================| 45// | CVI_MPY2 & CVI_MPY3 | |CVI_XLANE & CVI_SHIFT| 46// |=====================| |=====================| 47// S0-3 | CVI_VA_DV | | CVI_VA_DV | 48// S0-3 | | | CVI_VP_DV | 49// S2-3 | CVI_VX_DV | | | 50// |=====================| |=====================| 51// |=====================================================================| 52// S0-3 | CVI_HIST Histogram | 53// S0123| CVI_VA_EXT Extract | 54// |=====================================================================| 55 56def HexagonV60ItinList : DepScalarItinV60, ScalarItin, 57 DepHVXItinV60, 58 HVXItin, PseudoItin { 59 list<InstrItinData> ItinList = 60 !listconcat(DepScalarItinV60_list, ScalarItin_list, 61 DepHVXItinV60_list, HVXItin_list, PseudoItin_list); 62} 63 64def HexagonItinerariesV60 : 65 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP, 66 CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1, 67 CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL, 68 CVI_ALL_NOMEM], 69 [Hex_FWD, HVX_FWD], HexagonV60ItinList.ItinList>; 70 71def HexagonModelV60 : SchedMachineModel { 72 // Max issue per cycle == bundle width. 73 let IssueWidth = 4; 74 let Itineraries = HexagonItinerariesV60; 75 let LoadLatency = 1; 76 let CompleteModel = 0; 77} 78 79//===----------------------------------------------------------------------===// 80// Hexagon V60 Resource Definitions - 81//===----------------------------------------------------------------------===// 82