1//=-HexagonScheduleV65.td - HexagonV65 Scheduling Definitions *- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10// 11// ScalarItin and HVXItin contain some old itineraries 12// still used by a handful of instructions. Hopefully, we will be able 13// to get rid of them soon. 14 15def HexagonV65ItinList : DepScalarItinV65, ScalarItin, 16 DepHVXItinV65, HVXItin, PseudoItin { 17 list<InstrItinData> ItinList = 18 !listconcat(DepScalarItinV65_list, ScalarItin_list, 19 DepHVXItinV65_list, HVXItin_list, PseudoItin_list); 20} 21 22def HexagonItinerariesV65 : 23 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP, 24 CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1, 25 CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL, 26 CVI_ALL_NOMEM], 27 [Hex_FWD, HVX_FWD], 28 HexagonV65ItinList.ItinList>; 29 30def HexagonModelV65 : SchedMachineModel { 31 // Max issue per cycle == bundle width. 32 let IssueWidth = 4; 33 let Itineraries = HexagonItinerariesV65; 34 let LoadLatency = 1; 35 let CompleteModel = 0; 36} 37 38//===----------------------------------------------------------------------===// 39// Hexagon V65 Resource Definitions - 40//===----------------------------------------------------------------------===// 41