1 //===-- MSP430InstrInfo.h - MSP430 Instruction Information ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the MSP430 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H 15 #define LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H 16 17 #include "MSP430RegisterInfo.h" 18 #include "llvm/CodeGen/TargetInstrInfo.h" 19 20 #define GET_INSTRINFO_HEADER 21 #include "MSP430GenInstrInfo.inc" 22 23 namespace llvm { 24 25 class MSP430Subtarget; 26 27 /// MSP430II - This namespace holds all of the target specific flags that 28 /// instruction info tracks. 29 /// 30 namespace MSP430II { 31 enum { 32 SizeShift = 2, 33 SizeMask = 7 << SizeShift, 34 35 SizeUnknown = 0 << SizeShift, 36 SizeSpecial = 1 << SizeShift, 37 Size2Bytes = 2 << SizeShift, 38 Size4Bytes = 3 << SizeShift, 39 Size6Bytes = 4 << SizeShift 40 }; 41 } 42 43 class MSP430InstrInfo : public MSP430GenInstrInfo { 44 const MSP430RegisterInfo RI; 45 virtual void anchor(); 46 public: 47 explicit MSP430InstrInfo(MSP430Subtarget &STI); 48 49 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 50 /// such, whenever a client has an instance of instruction info, it should 51 /// always be able to get register info as well (through this method). 52 /// getRegisterInfo()53 const TargetRegisterInfo &getRegisterInfo() const { return RI; } 54 55 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 56 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, 57 bool KillSrc) const override; 58 59 void storeRegToStackSlot(MachineBasicBlock &MBB, 60 MachineBasicBlock::iterator MI, 61 unsigned SrcReg, bool isKill, 62 int FrameIndex, 63 const TargetRegisterClass *RC, 64 const TargetRegisterInfo *TRI) const override; 65 void loadRegFromStackSlot(MachineBasicBlock &MBB, 66 MachineBasicBlock::iterator MI, 67 unsigned DestReg, int FrameIdx, 68 const TargetRegisterClass *RC, 69 const TargetRegisterInfo *TRI) const override; 70 71 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 72 73 // Branch folding goodness 74 bool 75 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 76 bool isUnpredicatedTerminator(const MachineInstr &MI) const override; 77 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 78 MachineBasicBlock *&FBB, 79 SmallVectorImpl<MachineOperand> &Cond, 80 bool AllowModify) const override; 81 82 unsigned removeBranch(MachineBasicBlock &MBB, 83 int *BytesRemoved = nullptr) const override; 84 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 85 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 86 const DebugLoc &DL, 87 int *BytesAdded = nullptr) const override; 88 getFramePoppedByCallee(const MachineInstr & I)89 int64_t getFramePoppedByCallee(const MachineInstr &I) const { 90 assert(isFrameInstr(I) && "Not a frame instruction"); 91 assert(I.getOperand(1).getImm() >= 0 && "Size must not be negative"); 92 return I.getOperand(1).getImm(); 93 } 94 }; 95 96 } 97 98 #endif 99