1 //===-- SparcAsmBackend.cpp - Sparc Assembler Backend ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 #include "MCTargetDesc/SparcFixupKinds.h"
11 #include "MCTargetDesc/SparcMCTargetDesc.h"
12 #include "llvm/MC/MCAsmBackend.h"
13 #include "llvm/MC/MCELFObjectWriter.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCFixupKindInfo.h"
16 #include "llvm/MC/MCObjectWriter.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCValue.h"
19 #include "llvm/Support/TargetRegistry.h"
20
21 using namespace llvm;
22
adjustFixupValue(unsigned Kind,uint64_t Value)23 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
24 switch (Kind) {
25 default:
26 llvm_unreachable("Unknown fixup kind!");
27 case FK_Data_1:
28 case FK_Data_2:
29 case FK_Data_4:
30 case FK_Data_8:
31 return Value;
32
33 case Sparc::fixup_sparc_wplt30:
34 case Sparc::fixup_sparc_call30:
35 return (Value >> 2) & 0x3fffffff;
36
37 case Sparc::fixup_sparc_br22:
38 return (Value >> 2) & 0x3fffff;
39
40 case Sparc::fixup_sparc_br19:
41 return (Value >> 2) & 0x7ffff;
42
43 case Sparc::fixup_sparc_br16_2:
44 return (Value >> 2) & 0xc000;
45
46 case Sparc::fixup_sparc_br16_14:
47 return (Value >> 2) & 0x3fff;
48
49 case Sparc::fixup_sparc_pc22:
50 case Sparc::fixup_sparc_got22:
51 case Sparc::fixup_sparc_tls_gd_hi22:
52 case Sparc::fixup_sparc_tls_ldm_hi22:
53 case Sparc::fixup_sparc_tls_ie_hi22:
54 case Sparc::fixup_sparc_hi22:
55 return (Value >> 10) & 0x3fffff;
56
57 case Sparc::fixup_sparc_got13:
58 case Sparc::fixup_sparc_13:
59 return Value & 0x1fff;
60
61 case Sparc::fixup_sparc_pc10:
62 case Sparc::fixup_sparc_got10:
63 case Sparc::fixup_sparc_tls_gd_lo10:
64 case Sparc::fixup_sparc_tls_ldm_lo10:
65 case Sparc::fixup_sparc_tls_ie_lo10:
66 case Sparc::fixup_sparc_lo10:
67 return Value & 0x3ff;
68
69 case Sparc::fixup_sparc_h44:
70 return (Value >> 22) & 0x3fffff;
71
72 case Sparc::fixup_sparc_m44:
73 return (Value >> 12) & 0x3ff;
74
75 case Sparc::fixup_sparc_l44:
76 return Value & 0xfff;
77
78 case Sparc::fixup_sparc_hh:
79 return (Value >> 42) & 0x3fffff;
80
81 case Sparc::fixup_sparc_hm:
82 return (Value >> 32) & 0x3ff;
83
84 case Sparc::fixup_sparc_tls_ldo_hix22:
85 case Sparc::fixup_sparc_tls_le_hix22:
86 case Sparc::fixup_sparc_tls_ldo_lox10:
87 case Sparc::fixup_sparc_tls_le_lox10:
88 assert(Value == 0 && "Sparc TLS relocs expect zero Value");
89 return 0;
90
91 case Sparc::fixup_sparc_tls_gd_add:
92 case Sparc::fixup_sparc_tls_gd_call:
93 case Sparc::fixup_sparc_tls_ldm_add:
94 case Sparc::fixup_sparc_tls_ldm_call:
95 case Sparc::fixup_sparc_tls_ldo_add:
96 case Sparc::fixup_sparc_tls_ie_ld:
97 case Sparc::fixup_sparc_tls_ie_ldx:
98 case Sparc::fixup_sparc_tls_ie_add:
99 return 0;
100 }
101 }
102
103 namespace {
104 class SparcAsmBackend : public MCAsmBackend {
105 protected:
106 const Target &TheTarget;
107 bool Is64Bit;
108
109 public:
SparcAsmBackend(const Target & T)110 SparcAsmBackend(const Target &T)
111 : MCAsmBackend(StringRef(T.getName()) == "sparcel" ? support::little
112 : support::big),
113 TheTarget(T), Is64Bit(StringRef(TheTarget.getName()) == "sparcv9") {}
114
getNumFixupKinds() const115 unsigned getNumFixupKinds() const override {
116 return Sparc::NumTargetFixupKinds;
117 }
118
getFixupKindInfo(MCFixupKind Kind) const119 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
120 const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = {
121 // name offset bits flags
122 { "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
123 { "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
124 { "fixup_sparc_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
125 { "fixup_sparc_br16_2", 10, 2, MCFixupKindInfo::FKF_IsPCRel },
126 { "fixup_sparc_br16_14", 18, 14, MCFixupKindInfo::FKF_IsPCRel },
127 { "fixup_sparc_13", 19, 13, 0 },
128 { "fixup_sparc_hi22", 10, 22, 0 },
129 { "fixup_sparc_lo10", 22, 10, 0 },
130 { "fixup_sparc_h44", 10, 22, 0 },
131 { "fixup_sparc_m44", 22, 10, 0 },
132 { "fixup_sparc_l44", 20, 12, 0 },
133 { "fixup_sparc_hh", 10, 22, 0 },
134 { "fixup_sparc_hm", 22, 10, 0 },
135 { "fixup_sparc_pc22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
136 { "fixup_sparc_pc10", 22, 10, MCFixupKindInfo::FKF_IsPCRel },
137 { "fixup_sparc_got22", 10, 22, 0 },
138 { "fixup_sparc_got10", 22, 10, 0 },
139 { "fixup_sparc_got13", 19, 13, 0 },
140 { "fixup_sparc_wplt30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
141 { "fixup_sparc_tls_gd_hi22", 10, 22, 0 },
142 { "fixup_sparc_tls_gd_lo10", 22, 10, 0 },
143 { "fixup_sparc_tls_gd_add", 0, 0, 0 },
144 { "fixup_sparc_tls_gd_call", 0, 0, 0 },
145 { "fixup_sparc_tls_ldm_hi22", 10, 22, 0 },
146 { "fixup_sparc_tls_ldm_lo10", 22, 10, 0 },
147 { "fixup_sparc_tls_ldm_add", 0, 0, 0 },
148 { "fixup_sparc_tls_ldm_call", 0, 0, 0 },
149 { "fixup_sparc_tls_ldo_hix22", 10, 22, 0 },
150 { "fixup_sparc_tls_ldo_lox10", 22, 10, 0 },
151 { "fixup_sparc_tls_ldo_add", 0, 0, 0 },
152 { "fixup_sparc_tls_ie_hi22", 10, 22, 0 },
153 { "fixup_sparc_tls_ie_lo10", 22, 10, 0 },
154 { "fixup_sparc_tls_ie_ld", 0, 0, 0 },
155 { "fixup_sparc_tls_ie_ldx", 0, 0, 0 },
156 { "fixup_sparc_tls_ie_add", 0, 0, 0 },
157 { "fixup_sparc_tls_le_hix22", 0, 0, 0 },
158 { "fixup_sparc_tls_le_lox10", 0, 0, 0 }
159 };
160
161 const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = {
162 // name offset bits flags
163 { "fixup_sparc_call30", 0, 30, MCFixupKindInfo::FKF_IsPCRel },
164 { "fixup_sparc_br22", 0, 22, MCFixupKindInfo::FKF_IsPCRel },
165 { "fixup_sparc_br19", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
166 { "fixup_sparc_br16_2", 20, 2, MCFixupKindInfo::FKF_IsPCRel },
167 { "fixup_sparc_br16_14", 0, 14, MCFixupKindInfo::FKF_IsPCRel },
168 { "fixup_sparc_13", 0, 13, 0 },
169 { "fixup_sparc_hi22", 0, 22, 0 },
170 { "fixup_sparc_lo10", 0, 10, 0 },
171 { "fixup_sparc_h44", 0, 22, 0 },
172 { "fixup_sparc_m44", 0, 10, 0 },
173 { "fixup_sparc_l44", 0, 12, 0 },
174 { "fixup_sparc_hh", 0, 22, 0 },
175 { "fixup_sparc_hm", 0, 10, 0 },
176 { "fixup_sparc_pc22", 0, 22, MCFixupKindInfo::FKF_IsPCRel },
177 { "fixup_sparc_pc10", 0, 10, MCFixupKindInfo::FKF_IsPCRel },
178 { "fixup_sparc_got22", 0, 22, 0 },
179 { "fixup_sparc_got10", 0, 10, 0 },
180 { "fixup_sparc_got13", 0, 13, 0 },
181 { "fixup_sparc_wplt30", 0, 30, MCFixupKindInfo::FKF_IsPCRel },
182 { "fixup_sparc_tls_gd_hi22", 0, 22, 0 },
183 { "fixup_sparc_tls_gd_lo10", 0, 10, 0 },
184 { "fixup_sparc_tls_gd_add", 0, 0, 0 },
185 { "fixup_sparc_tls_gd_call", 0, 0, 0 },
186 { "fixup_sparc_tls_ldm_hi22", 0, 22, 0 },
187 { "fixup_sparc_tls_ldm_lo10", 0, 10, 0 },
188 { "fixup_sparc_tls_ldm_add", 0, 0, 0 },
189 { "fixup_sparc_tls_ldm_call", 0, 0, 0 },
190 { "fixup_sparc_tls_ldo_hix22", 0, 22, 0 },
191 { "fixup_sparc_tls_ldo_lox10", 0, 10, 0 },
192 { "fixup_sparc_tls_ldo_add", 0, 0, 0 },
193 { "fixup_sparc_tls_ie_hi22", 0, 22, 0 },
194 { "fixup_sparc_tls_ie_lo10", 0, 10, 0 },
195 { "fixup_sparc_tls_ie_ld", 0, 0, 0 },
196 { "fixup_sparc_tls_ie_ldx", 0, 0, 0 },
197 { "fixup_sparc_tls_ie_add", 0, 0, 0 },
198 { "fixup_sparc_tls_le_hix22", 0, 0, 0 },
199 { "fixup_sparc_tls_le_lox10", 0, 0, 0 }
200 };
201
202 if (Kind < FirstTargetFixupKind)
203 return MCAsmBackend::getFixupKindInfo(Kind);
204
205 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
206 "Invalid kind!");
207 if (Endian == support::little)
208 return InfosLE[Kind - FirstTargetFixupKind];
209
210 return InfosBE[Kind - FirstTargetFixupKind];
211 }
212
shouldForceRelocation(const MCAssembler & Asm,const MCFixup & Fixup,const MCValue & Target)213 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
214 const MCValue &Target) override {
215 switch ((Sparc::Fixups)Fixup.getKind()) {
216 default:
217 return false;
218 case Sparc::fixup_sparc_wplt30:
219 if (Target.getSymA()->getSymbol().isTemporary())
220 return false;
221 LLVM_FALLTHROUGH;
222 case Sparc::fixup_sparc_tls_gd_hi22:
223 case Sparc::fixup_sparc_tls_gd_lo10:
224 case Sparc::fixup_sparc_tls_gd_add:
225 case Sparc::fixup_sparc_tls_gd_call:
226 case Sparc::fixup_sparc_tls_ldm_hi22:
227 case Sparc::fixup_sparc_tls_ldm_lo10:
228 case Sparc::fixup_sparc_tls_ldm_add:
229 case Sparc::fixup_sparc_tls_ldm_call:
230 case Sparc::fixup_sparc_tls_ldo_hix22:
231 case Sparc::fixup_sparc_tls_ldo_lox10:
232 case Sparc::fixup_sparc_tls_ldo_add:
233 case Sparc::fixup_sparc_tls_ie_hi22:
234 case Sparc::fixup_sparc_tls_ie_lo10:
235 case Sparc::fixup_sparc_tls_ie_ld:
236 case Sparc::fixup_sparc_tls_ie_ldx:
237 case Sparc::fixup_sparc_tls_ie_add:
238 case Sparc::fixup_sparc_tls_le_hix22:
239 case Sparc::fixup_sparc_tls_le_lox10:
240 return true;
241 }
242 }
243
mayNeedRelaxation(const MCInst & Inst,const MCSubtargetInfo & STI) const244 bool mayNeedRelaxation(const MCInst &Inst,
245 const MCSubtargetInfo &STI) const override {
246 // FIXME.
247 return false;
248 }
249
250 /// fixupNeedsRelaxation - Target specific predicate for whether a given
251 /// fixup requires the associated instruction to be relaxed.
fixupNeedsRelaxation(const MCFixup & Fixup,uint64_t Value,const MCRelaxableFragment * DF,const MCAsmLayout & Layout) const252 bool fixupNeedsRelaxation(const MCFixup &Fixup,
253 uint64_t Value,
254 const MCRelaxableFragment *DF,
255 const MCAsmLayout &Layout) const override {
256 // FIXME.
257 llvm_unreachable("fixupNeedsRelaxation() unimplemented");
258 return false;
259 }
relaxInstruction(const MCInst & Inst,const MCSubtargetInfo & STI,MCInst & Res) const260 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
261 MCInst &Res) const override {
262 // FIXME.
263 llvm_unreachable("relaxInstruction() unimplemented");
264 }
265
writeNopData(raw_ostream & OS,uint64_t Count) const266 bool writeNopData(raw_ostream &OS, uint64_t Count) const override {
267 // Cannot emit NOP with size not multiple of 32 bits.
268 if (Count % 4 != 0)
269 return false;
270
271 uint64_t NumNops = Count / 4;
272 for (uint64_t i = 0; i != NumNops; ++i)
273 support::endian::write<uint32_t>(OS, 0x01000000, Endian);
274
275 return true;
276 }
277 };
278
279 class ELFSparcAsmBackend : public SparcAsmBackend {
280 Triple::OSType OSType;
281 public:
ELFSparcAsmBackend(const Target & T,Triple::OSType OSType)282 ELFSparcAsmBackend(const Target &T, Triple::OSType OSType) :
283 SparcAsmBackend(T), OSType(OSType) { }
284
applyFixup(const MCAssembler & Asm,const MCFixup & Fixup,const MCValue & Target,MutableArrayRef<char> Data,uint64_t Value,bool IsResolved,const MCSubtargetInfo * STI) const285 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
286 const MCValue &Target, MutableArrayRef<char> Data,
287 uint64_t Value, bool IsResolved,
288 const MCSubtargetInfo *STI) const override {
289
290 Value = adjustFixupValue(Fixup.getKind(), Value);
291 if (!Value) return; // Doesn't change encoding.
292
293 unsigned Offset = Fixup.getOffset();
294
295 // For each byte of the fragment that the fixup touches, mask in the bits
296 // from the fixup value. The Value has been "split up" into the
297 // appropriate bitfields above.
298 for (unsigned i = 0; i != 4; ++i) {
299 unsigned Idx = Endian == support::little ? i : 3 - i;
300 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
301 }
302 }
303
304 std::unique_ptr<MCObjectTargetWriter>
createObjectTargetWriter() const305 createObjectTargetWriter() const override {
306 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
307 return createSparcELFObjectWriter(Is64Bit, OSABI);
308 }
309 };
310
311 } // end anonymous namespace
312
createSparcAsmBackend(const Target & T,const MCSubtargetInfo & STI,const MCRegisterInfo & MRI,const MCTargetOptions & Options)313 MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
314 const MCSubtargetInfo &STI,
315 const MCRegisterInfo &MRI,
316 const MCTargetOptions &Options) {
317 return new ELFSparcAsmBackend(T, STI.getTargetTriple().getOS());
318 }
319