1//WebAssemblyRegisterInfo.td-Describe the WebAssembly Registers -*- tablegen -*- 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9/// 10/// \file 11/// This file describes the WebAssembly register classes and some nominal 12/// physical registers. 13/// 14//===----------------------------------------------------------------------===// 15 16class WebAssemblyReg<string n> : Register<n> { 17 let Namespace = "WebAssembly"; 18} 19 20class WebAssemblyRegClass<list<ValueType> regTypes, int alignment, dag regList> 21 : RegisterClass<"WebAssembly", regTypes, alignment, regList>; 22 23//===----------------------------------------------------------------------===// 24// Registers 25//===----------------------------------------------------------------------===// 26 27// Special registers used as the frame and stack pointer. 28// 29// WebAssembly may someday supports mixed 32-bit and 64-bit heaps in the same 30// application, which requires separate width FP and SP. 31def FP32 : WebAssemblyReg<"%FP32">; 32def FP64 : WebAssemblyReg<"%FP64">; 33def SP32 : WebAssemblyReg<"%SP32">; 34def SP64 : WebAssemblyReg<"%SP64">; 35 36// The register allocation framework requires register classes have at least 37// one register, so we define a few for the integer / floating point register 38// classes since we otherwise don't need a physical register in those classes. 39// These are also used a "types" in the generated assembly matcher. 40def I32_0 : WebAssemblyReg<"%i32.0">; 41def I64_0 : WebAssemblyReg<"%i64.0">; 42def F32_0 : WebAssemblyReg<"%f32.0">; 43def F64_0 : WebAssemblyReg<"%f64.0">; 44 45def V128_0: WebAssemblyReg<"%v128">; 46 47def EXCEPT_REF_0 : WebAssemblyReg<"%except_ref.0">; 48 49// The value stack "register". This is an opaque entity which serves to order 50// uses and defs that must remain in LIFO order. 51def VALUE_STACK : WebAssemblyReg<"STACK">; 52 53// The incoming arguments "register". This is an opaque entity which serves to 54// order the ARGUMENT instructions that are emulating live-in registers and 55// must not be scheduled below other instructions. 56def ARGUMENTS : WebAssemblyReg<"ARGUMENTS">; 57 58//===----------------------------------------------------------------------===// 59// Register classes 60//===----------------------------------------------------------------------===// 61 62def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32, I32_0)>; 63def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64, I64_0)>; 64def F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>; 65def F64 : WebAssemblyRegClass<[f64], 64, (add F64_0)>; 66def V128 : WebAssemblyRegClass<[v4f32, v4i32, v16i8, v8i16], 128, (add V128_0)>; 67def EXCEPT_REF : WebAssemblyRegClass<[ExceptRef], 0, (add EXCEPT_REF_0)>; 68 69