1//=- X86ScheduleSLM.td - X86 Silvermont Scheduling -----------*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the machine model for Intel Silvermont to support 11// instruction scheduling and other instruction cost heuristics. 12// 13//===----------------------------------------------------------------------===// 14 15def SLMModel : SchedMachineModel { 16 // All x86 instructions are modeled as a single micro-op, and SLM can decode 2 17 // instructions per cycle. 18 let IssueWidth = 2; 19 let MicroOpBufferSize = 32; // Based on the reorder buffer. 20 let LoadLatency = 3; 21 let MispredictPenalty = 10; 22 let PostRAScheduler = 1; 23 24 // For small loops, expand by a small factor to hide the backedge cost. 25 let LoopMicroOpBufferSize = 10; 26 27 // FIXME: SSE4 is unimplemented. This flag is set to allow 28 // the scheduler to assign a default model to unrecognized opcodes. 29 let CompleteModel = 0; 30} 31 32let SchedModel = SLMModel in { 33 34// Silvermont has 5 reservation stations for micro-ops 35def SLM_IEC_RSV0 : ProcResource<1>; 36def SLM_IEC_RSV1 : ProcResource<1>; 37def SLM_FPC_RSV0 : ProcResource<1> { let BufferSize = 1; } 38def SLM_FPC_RSV1 : ProcResource<1> { let BufferSize = 1; } 39def SLM_MEC_RSV : ProcResource<1>; 40 41// Many micro-ops are capable of issuing on multiple ports. 42def SLM_IEC_RSV01 : ProcResGroup<[SLM_IEC_RSV0, SLM_IEC_RSV1]>; 43def SLM_FPC_RSV01 : ProcResGroup<[SLM_FPC_RSV0, SLM_FPC_RSV1]>; 44 45def SLMDivider : ProcResource<1>; 46def SLMFPMultiplier : ProcResource<1>; 47def SLMFPDivider : ProcResource<1>; 48 49// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3 50// cycles after the memory operand. 51def : ReadAdvance<ReadAfterLd, 3>; 52 53// Many SchedWrites are defined in pairs with and without a folded load. 54// Instructions with folded loads are usually micro-fused, so they only appear 55// as two micro-ops when queued in the reservation station. 56// This multiclass defines the resource usage for variants with and without 57// folded loads. 58multiclass SLMWriteResPair<X86FoldableSchedWrite SchedRW, 59 list<ProcResourceKind> ExePorts, 60 int Lat, list<int> Res = [1], int UOps = 1, 61 int LoadLat = 3> { 62 // Register variant is using a single cycle on ExePort. 63 def : WriteRes<SchedRW, ExePorts> { 64 let Latency = Lat; 65 let ResourceCycles = Res; 66 let NumMicroOps = UOps; 67 } 68 69 // Memory variant also uses a cycle on MEC_RSV and adds LoadLat cycles to 70 // the latency (default = 3). 71 def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> { 72 let Latency = !add(Lat, LoadLat); 73 let ResourceCycles = !listconcat([1], Res); 74 let NumMicroOps = UOps; 75 } 76} 77 78// A folded store needs a cycle on MEC_RSV for the store data, but it does not 79// need an extra port cycle to recompute the address. 80def : WriteRes<WriteRMW, [SLM_MEC_RSV]>; 81 82def : WriteRes<WriteStore, [SLM_IEC_RSV01, SLM_MEC_RSV]>; 83def : WriteRes<WriteStoreNT, [SLM_IEC_RSV01, SLM_MEC_RSV]>; 84def : WriteRes<WriteLoad, [SLM_MEC_RSV]> { let Latency = 3; } 85def : WriteRes<WriteMove, [SLM_IEC_RSV01]>; 86def : WriteRes<WriteZero, []>; 87 88// Load/store MXCSR. 89// FIXME: These are probably wrong. They are copy pasted from WriteStore/Load. 90def : WriteRes<WriteSTMXCSR, [SLM_IEC_RSV01, SLM_MEC_RSV]>; 91def : WriteRes<WriteLDMXCSR, [SLM_MEC_RSV]> { let Latency = 3; } 92 93// Treat misc copies as a move. 94def : InstRW<[WriteMove], (instrs COPY)>; 95 96defm : SLMWriteResPair<WriteALU, [SLM_IEC_RSV01], 1>; 97defm : SLMWriteResPair<WriteADC, [SLM_IEC_RSV01], 1>; 98defm : SLMWriteResPair<WriteIMul, [SLM_IEC_RSV1], 3>; 99defm : SLMWriteResPair<WriteIMul64, [SLM_IEC_RSV1], 3>; 100 101defm : X86WriteRes<WriteBSWAP32, [SLM_IEC_RSV01], 1, [1], 1>; 102defm : X86WriteRes<WriteBSWAP64, [SLM_IEC_RSV01], 1, [1], 1>; 103 104defm : SLMWriteResPair<WriteShift, [SLM_IEC_RSV0], 1>; 105 106defm : X86WriteRes<WriteSHDrri, [SLM_IEC_RSV0], 1, [1], 1>; 107defm : X86WriteRes<WriteSHDrrcl,[SLM_IEC_RSV0], 1, [1], 1>; 108defm : X86WriteRes<WriteSHDmri, [SLM_MEC_RSV, SLM_IEC_RSV0], 4, [2, 1], 2>; 109defm : X86WriteRes<WriteSHDmrcl,[SLM_MEC_RSV, SLM_IEC_RSV0], 4, [2, 1], 2>; 110 111defm : SLMWriteResPair<WriteJump, [SLM_IEC_RSV1], 1>; 112defm : SLMWriteResPair<WriteCRC32, [SLM_IEC_RSV1], 3>; 113 114defm : SLMWriteResPair<WriteCMOV, [SLM_IEC_RSV01], 2, [2]>; 115defm : SLMWriteResPair<WriteCMOV2, [SLM_IEC_RSV01], 2, [2]>; 116defm : X86WriteRes<WriteFCMOV, [SLM_FPC_RSV1], 3, [1], 1>; // x87 conditional move. 117def : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>; 118def : WriteRes<WriteSETCCStore, [SLM_IEC_RSV01, SLM_MEC_RSV]> { 119 // FIXME Latency and NumMicrOps? 120 let ResourceCycles = [2,1]; 121} 122def : WriteRes<WriteLAHFSAHF, [SLM_IEC_RSV01]>; 123def : WriteRes<WriteBitTest,[SLM_IEC_RSV01]>; 124 125// This is for simple LEAs with one or two input operands. 126// The complex ones can only execute on port 1, and they require two cycles on 127// the port to read all inputs. We don't model that. 128def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>; 129 130// Bit counts. 131defm : SLMWriteResPair<WriteBSF, [SLM_IEC_RSV01], 10, [20], 10>; 132defm : SLMWriteResPair<WriteBSR, [SLM_IEC_RSV01], 10, [20], 10>; 133defm : SLMWriteResPair<WriteLZCNT, [SLM_IEC_RSV0], 3>; 134defm : SLMWriteResPair<WriteTZCNT, [SLM_IEC_RSV0], 3>; 135defm : SLMWriteResPair<WritePOPCNT, [SLM_IEC_RSV0], 3>; 136 137// BMI1 BEXTR, BMI2 BZHI 138defm : X86WriteResPairUnsupported<WriteBEXTR>; 139defm : X86WriteResPairUnsupported<WriteBZHI>; 140 141defm : SLMWriteResPair<WriteDiv8, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 142defm : SLMWriteResPair<WriteDiv16, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 143defm : SLMWriteResPair<WriteDiv32, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 144defm : SLMWriteResPair<WriteDiv64, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 145defm : SLMWriteResPair<WriteIDiv8, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 146defm : SLMWriteResPair<WriteIDiv16, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 147defm : SLMWriteResPair<WriteIDiv32, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 148defm : SLMWriteResPair<WriteIDiv64, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 149 150// Scalar and vector floating point. 151defm : X86WriteRes<WriteFLD0, [SLM_FPC_RSV01], 1, [1], 1>; 152defm : X86WriteRes<WriteFLD1, [SLM_FPC_RSV01], 1, [1], 1>; 153defm : X86WriteRes<WriteFLDC, [SLM_FPC_RSV01], 1, [2], 2>; 154def : WriteRes<WriteFLoad, [SLM_MEC_RSV]> { let Latency = 3; } 155def : WriteRes<WriteFLoadX, [SLM_MEC_RSV]> { let Latency = 3; } 156def : WriteRes<WriteFLoadY, [SLM_MEC_RSV]> { let Latency = 3; } 157def : WriteRes<WriteFMaskedLoad, [SLM_MEC_RSV]> { let Latency = 3; } 158def : WriteRes<WriteFMaskedLoadY, [SLM_MEC_RSV]> { let Latency = 3; } 159def : WriteRes<WriteFStore, [SLM_MEC_RSV]>; 160def : WriteRes<WriteFStoreX, [SLM_MEC_RSV]>; 161def : WriteRes<WriteFStoreY, [SLM_MEC_RSV]>; 162def : WriteRes<WriteFStoreNT, [SLM_MEC_RSV]>; 163def : WriteRes<WriteFStoreNTX, [SLM_MEC_RSV]>; 164def : WriteRes<WriteFStoreNTY, [SLM_MEC_RSV]>; 165def : WriteRes<WriteFMaskedStore, [SLM_MEC_RSV]>; 166def : WriteRes<WriteFMaskedStoreY, [SLM_MEC_RSV]>; 167def : WriteRes<WriteFMove, [SLM_FPC_RSV01]>; 168def : WriteRes<WriteFMoveX, [SLM_FPC_RSV01]>; 169def : WriteRes<WriteFMoveY, [SLM_FPC_RSV01]>; 170defm : X86WriteRes<WriteEMMS, [SLM_FPC_RSV01], 10, [10], 9>; 171 172defm : SLMWriteResPair<WriteFAdd, [SLM_FPC_RSV1], 3>; 173defm : SLMWriteResPair<WriteFAddX, [SLM_FPC_RSV1], 3>; 174defm : SLMWriteResPair<WriteFAddY, [SLM_FPC_RSV1], 3>; 175defm : X86WriteResPairUnsupported<WriteFAddZ>; 176defm : SLMWriteResPair<WriteFAdd64, [SLM_FPC_RSV1], 3>; 177defm : SLMWriteResPair<WriteFAdd64X, [SLM_FPC_RSV1], 3>; 178defm : SLMWriteResPair<WriteFAdd64Y, [SLM_FPC_RSV1], 3>; 179defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 180defm : SLMWriteResPair<WriteFCmp, [SLM_FPC_RSV1], 3>; 181defm : SLMWriteResPair<WriteFCmpX, [SLM_FPC_RSV1], 3>; 182defm : SLMWriteResPair<WriteFCmpY, [SLM_FPC_RSV1], 3>; 183defm : X86WriteResPairUnsupported<WriteFCmpZ>; 184defm : SLMWriteResPair<WriteFCmp64, [SLM_FPC_RSV1], 3>; 185defm : SLMWriteResPair<WriteFCmp64X, [SLM_FPC_RSV1], 3>; 186defm : SLMWriteResPair<WriteFCmp64Y, [SLM_FPC_RSV1], 3>; 187defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 188defm : SLMWriteResPair<WriteFCom, [SLM_FPC_RSV1], 3>; 189defm : SLMWriteResPair<WriteFMul, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 190defm : SLMWriteResPair<WriteFMulX, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 191defm : SLMWriteResPair<WriteFMulY, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 192defm : X86WriteResPairUnsupported<WriteFMulZ>; 193defm : SLMWriteResPair<WriteFMul64, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 194defm : SLMWriteResPair<WriteFMul64X, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 195defm : SLMWriteResPair<WriteFMul64Y, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 196defm : X86WriteResPairUnsupported<WriteFMul64Z>; 197defm : SLMWriteResPair<WriteFDiv, [SLM_FPC_RSV0, SLMFPDivider], 19, [1,17]>; 198defm : SLMWriteResPair<WriteFDivX, [SLM_FPC_RSV0, SLMFPDivider], 39, [1,39]>; 199defm : SLMWriteResPair<WriteFDivY, [SLM_FPC_RSV0, SLMFPDivider], 39, [1,39]>; 200defm : X86WriteResPairUnsupported<WriteFDivZ>; 201defm : SLMWriteResPair<WriteFDiv64, [SLM_FPC_RSV0, SLMFPDivider], 34, [1,32]>; 202defm : SLMWriteResPair<WriteFDiv64X, [SLM_FPC_RSV0, SLMFPDivider], 69, [1,69]>; 203defm : SLMWriteResPair<WriteFDiv64Y, [SLM_FPC_RSV0, SLMFPDivider], 69, [1,69]>; 204defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 205defm : SLMWriteResPair<WriteFRcp, [SLM_FPC_RSV0], 5>; 206defm : SLMWriteResPair<WriteFRcpX, [SLM_FPC_RSV0], 5>; 207defm : SLMWriteResPair<WriteFRcpY, [SLM_FPC_RSV0], 5>; 208defm : X86WriteResPairUnsupported<WriteFRcpZ>; 209defm : SLMWriteResPair<WriteFRsqrt, [SLM_FPC_RSV0], 5>; 210defm : SLMWriteResPair<WriteFRsqrtX, [SLM_FPC_RSV0], 5>; 211defm : SLMWriteResPair<WriteFRsqrtY, [SLM_FPC_RSV0], 5>; 212defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 213defm : SLMWriteResPair<WriteFSqrt, [SLM_FPC_RSV0,SLMFPDivider], 20, [1,20], 1, 3>; 214defm : SLMWriteResPair<WriteFSqrtX, [SLM_FPC_RSV0,SLMFPDivider], 41, [1,40], 1, 3>; 215defm : SLMWriteResPair<WriteFSqrtY, [SLM_FPC_RSV0,SLMFPDivider], 41, [1,40], 1, 3>; 216defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 217defm : SLMWriteResPair<WriteFSqrt64, [SLM_FPC_RSV0,SLMFPDivider], 35, [1,35], 1, 3>; 218defm : SLMWriteResPair<WriteFSqrt64X, [SLM_FPC_RSV0,SLMFPDivider], 71, [1,70], 1, 3>; 219defm : SLMWriteResPair<WriteFSqrt64Y, [SLM_FPC_RSV0,SLMFPDivider], 71, [1,70], 1, 3>; 220defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 221defm : SLMWriteResPair<WriteFSqrt80, [SLM_FPC_RSV0,SLMFPDivider], 40, [1,40]>; 222defm : SLMWriteResPair<WriteDPPD, [SLM_FPC_RSV1], 3>; 223defm : SLMWriteResPair<WriteDPPS, [SLM_FPC_RSV1], 3>; 224defm : SLMWriteResPair<WriteDPPSY, [SLM_FPC_RSV1], 3>; 225defm : X86WriteResPairUnsupported<WriteDPPSZ>; 226defm : SLMWriteResPair<WriteFSign, [SLM_FPC_RSV01], 1>; 227defm : SLMWriteResPair<WriteFRnd, [SLM_FPC_RSV1], 3>; 228defm : SLMWriteResPair<WriteFRndY, [SLM_FPC_RSV1], 3>; 229defm : X86WriteResPairUnsupported<WriteFRndZ>; 230defm : SLMWriteResPair<WriteFLogic, [SLM_FPC_RSV01], 1>; 231defm : SLMWriteResPair<WriteFLogicY, [SLM_FPC_RSV01], 1>; 232defm : X86WriteResPairUnsupported<WriteFLogicZ>; 233defm : SLMWriteResPair<WriteFTest, [SLM_FPC_RSV01], 1>; 234defm : SLMWriteResPair<WriteFTestY, [SLM_FPC_RSV01], 1>; 235defm : X86WriteResPairUnsupported<WriteFTestZ>; 236defm : SLMWriteResPair<WriteFShuffle, [SLM_FPC_RSV0], 1>; 237defm : SLMWriteResPair<WriteFShuffleY, [SLM_FPC_RSV0], 1>; 238defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 239defm : SLMWriteResPair<WriteFVarShuffle, [SLM_FPC_RSV0], 1>; 240defm : SLMWriteResPair<WriteFVarShuffleY,[SLM_FPC_RSV0], 1>; 241defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 242defm : SLMWriteResPair<WriteFBlend, [SLM_FPC_RSV0], 1>; 243 244// Conversion between integer and float. 245defm : SLMWriteResPair<WriteCvtSS2I, [SLM_FPC_RSV01], 4>; 246defm : SLMWriteResPair<WriteCvtPS2I, [SLM_FPC_RSV01], 4>; 247defm : SLMWriteResPair<WriteCvtPS2IY, [SLM_FPC_RSV01], 4>; 248defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 249defm : SLMWriteResPair<WriteCvtSD2I, [SLM_FPC_RSV01], 4>; 250defm : SLMWriteResPair<WriteCvtPD2I, [SLM_FPC_RSV01], 4>; 251defm : SLMWriteResPair<WriteCvtPD2IY, [SLM_FPC_RSV01], 4>; 252defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 253 254defm : SLMWriteResPair<WriteCvtI2SS, [SLM_FPC_RSV01], 4>; 255defm : SLMWriteResPair<WriteCvtI2PS, [SLM_FPC_RSV01], 4>; 256defm : SLMWriteResPair<WriteCvtI2PSY, [SLM_FPC_RSV01], 4>; 257defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 258defm : SLMWriteResPair<WriteCvtI2SD, [SLM_FPC_RSV01], 4>; 259defm : SLMWriteResPair<WriteCvtI2PD, [SLM_FPC_RSV01], 4>; 260defm : SLMWriteResPair<WriteCvtI2PDY, [SLM_FPC_RSV01], 4>; 261defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 262 263defm : SLMWriteResPair<WriteCvtSS2SD, [SLM_FPC_RSV01], 4>; 264defm : SLMWriteResPair<WriteCvtPS2PD, [SLM_FPC_RSV01], 4>; 265defm : SLMWriteResPair<WriteCvtPS2PDY, [SLM_FPC_RSV01], 4>; 266defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 267defm : SLMWriteResPair<WriteCvtSD2SS, [SLM_FPC_RSV01], 4>; 268defm : SLMWriteResPair<WriteCvtPD2PS, [SLM_FPC_RSV01], 4>; 269defm : SLMWriteResPair<WriteCvtPD2PSY, [SLM_FPC_RSV01], 4>; 270defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 271 272// Vector integer operations. 273def : WriteRes<WriteVecLoad, [SLM_MEC_RSV]> { let Latency = 3; } 274def : WriteRes<WriteVecLoadX, [SLM_MEC_RSV]> { let Latency = 3; } 275def : WriteRes<WriteVecLoadY, [SLM_MEC_RSV]> { let Latency = 3; } 276def : WriteRes<WriteVecLoadNT, [SLM_MEC_RSV]> { let Latency = 3; } 277def : WriteRes<WriteVecLoadNTY, [SLM_MEC_RSV]> { let Latency = 3; } 278def : WriteRes<WriteVecMaskedLoad, [SLM_MEC_RSV]> { let Latency = 3; } 279def : WriteRes<WriteVecMaskedLoadY, [SLM_MEC_RSV]> { let Latency = 3; } 280def : WriteRes<WriteVecStore, [SLM_MEC_RSV]>; 281def : WriteRes<WriteVecStoreX, [SLM_MEC_RSV]>; 282def : WriteRes<WriteVecStoreY, [SLM_MEC_RSV]>; 283def : WriteRes<WriteVecStoreNT, [SLM_MEC_RSV]>; 284def : WriteRes<WriteVecStoreNTY, [SLM_MEC_RSV]>; 285def : WriteRes<WriteVecMaskedStore, [SLM_MEC_RSV]>; 286def : WriteRes<WriteVecMaskedStoreY, [SLM_MEC_RSV]>; 287def : WriteRes<WriteVecMove, [SLM_FPC_RSV01]>; 288def : WriteRes<WriteVecMoveX, [SLM_FPC_RSV01]>; 289def : WriteRes<WriteVecMoveY, [SLM_FPC_RSV01]>; 290def : WriteRes<WriteVecMoveToGpr, [SLM_IEC_RSV01]>; 291def : WriteRes<WriteVecMoveFromGpr, [SLM_IEC_RSV01]>; 292 293defm : SLMWriteResPair<WriteVecShift, [SLM_FPC_RSV0], 1>; 294defm : SLMWriteResPair<WriteVecShiftX, [SLM_FPC_RSV0], 1>; 295defm : SLMWriteResPair<WriteVecShiftY, [SLM_FPC_RSV0], 1>; 296defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 297defm : SLMWriteResPair<WriteVecShiftImm, [SLM_FPC_RSV0], 1>; 298defm : SLMWriteResPair<WriteVecShiftImmX,[SLM_FPC_RSV0], 1>; 299defm : SLMWriteResPair<WriteVecShiftImmY,[SLM_FPC_RSV0], 1>; 300defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 301defm : SLMWriteResPair<WriteVecLogic, [SLM_FPC_RSV01], 1>; 302defm : SLMWriteResPair<WriteVecLogicX,[SLM_FPC_RSV01], 1>; 303defm : SLMWriteResPair<WriteVecLogicY,[SLM_FPC_RSV01], 1>; 304defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 305defm : SLMWriteResPair<WriteVecTest, [SLM_FPC_RSV01], 1>; 306defm : SLMWriteResPair<WriteVecTestY, [SLM_FPC_RSV01], 1>; 307defm : X86WriteResPairUnsupported<WriteVecTestZ>; 308defm : SLMWriteResPair<WriteVecALU, [SLM_FPC_RSV01], 1>; 309defm : SLMWriteResPair<WriteVecALUX, [SLM_FPC_RSV01], 1>; 310defm : SLMWriteResPair<WriteVecALUY, [SLM_FPC_RSV01], 1>; 311defm : X86WriteResPairUnsupported<WriteVecALUZ>; 312defm : SLMWriteResPair<WriteVecIMul, [SLM_FPC_RSV0], 4>; 313defm : SLMWriteResPair<WriteVecIMulX, [SLM_FPC_RSV0], 4>; 314defm : SLMWriteResPair<WriteVecIMulY, [SLM_FPC_RSV0], 4>; 315defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 316// FIXME: The below is closer to correct, but caused some perf regressions. 317//defm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 11, [11], 7>; 318defm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 4>; 319defm : SLMWriteResPair<WritePMULLDY, [SLM_FPC_RSV0], 4>; 320defm : X86WriteResPairUnsupported<WritePMULLDZ>; 321defm : SLMWriteResPair<WriteShuffle, [SLM_FPC_RSV0], 1>; 322defm : SLMWriteResPair<WriteShuffleY, [SLM_FPC_RSV0], 1>; 323defm : X86WriteResPairUnsupported<WriteShuffleZ>; 324defm : SLMWriteResPair<WriteShuffleX, [SLM_FPC_RSV0], 1>; 325defm : SLMWriteResPair<WriteVarShuffle, [SLM_FPC_RSV0], 1>; 326defm : SLMWriteResPair<WriteVarShuffleX, [SLM_FPC_RSV0], 1>; 327defm : SLMWriteResPair<WriteVarShuffleY, [SLM_FPC_RSV0], 1>; 328defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 329defm : SLMWriteResPair<WriteBlend, [SLM_FPC_RSV0], 1>; 330defm : SLMWriteResPair<WriteBlendY, [SLM_FPC_RSV0], 1>; 331defm : X86WriteResPairUnsupported<WriteBlendZ>; 332defm : SLMWriteResPair<WriteMPSAD, [SLM_FPC_RSV0], 7>; 333defm : SLMWriteResPair<WriteMPSADY, [SLM_FPC_RSV0], 7>; 334defm : X86WriteResPairUnsupported<WriteMPSADZ>; 335defm : SLMWriteResPair<WritePSADBW, [SLM_FPC_RSV0], 4>; 336defm : SLMWriteResPair<WritePSADBWX, [SLM_FPC_RSV0], 4>; 337defm : SLMWriteResPair<WritePSADBWY, [SLM_FPC_RSV0], 4>; 338defm : X86WriteResPairUnsupported<WritePSADBWZ>; 339defm : SLMWriteResPair<WritePHMINPOS, [SLM_FPC_RSV0], 4>; 340 341// Vector insert/extract operations. 342defm : SLMWriteResPair<WriteVecInsert, [SLM_FPC_RSV0], 1>; 343 344def : WriteRes<WriteVecExtract, [SLM_FPC_RSV0]>; 345def : WriteRes<WriteVecExtractSt, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 346 let Latency = 4; 347 let NumMicroOps = 2; 348 let ResourceCycles = [1, 2]; 349} 350 351//////////////////////////////////////////////////////////////////////////////// 352// Horizontal add/sub instructions. 353//////////////////////////////////////////////////////////////////////////////// 354 355defm : SLMWriteResPair<WriteFHAdd, [SLM_FPC_RSV01], 3, [2]>; 356defm : SLMWriteResPair<WriteFHAddY, [SLM_FPC_RSV01], 3, [2]>; 357defm : X86WriteResPairUnsupported<WriteFHAddZ>; 358defm : SLMWriteResPair<WritePHAdd, [SLM_FPC_RSV01], 1>; 359defm : SLMWriteResPair<WritePHAddX, [SLM_FPC_RSV01], 1>; 360defm : SLMWriteResPair<WritePHAddY, [SLM_FPC_RSV01], 1>; 361defm : X86WriteResPairUnsupported<WritePHAddZ>; 362 363// String instructions. 364// Packed Compare Implicit Length Strings, Return Mask 365def : WriteRes<WritePCmpIStrM, [SLM_FPC_RSV0]> { 366 let Latency = 13; 367 let ResourceCycles = [13]; 368} 369def : WriteRes<WritePCmpIStrMLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 370 let Latency = 13; 371 let ResourceCycles = [13, 1]; 372} 373 374// Packed Compare Explicit Length Strings, Return Mask 375def : WriteRes<WritePCmpEStrM, [SLM_FPC_RSV0]> { 376 let Latency = 17; 377 let ResourceCycles = [17]; 378} 379def : WriteRes<WritePCmpEStrMLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 380 let Latency = 17; 381 let ResourceCycles = [17, 1]; 382} 383 384// Packed Compare Implicit Length Strings, Return Index 385def : WriteRes<WritePCmpIStrI, [SLM_FPC_RSV0]> { 386 let Latency = 17; 387 let ResourceCycles = [17]; 388} 389def : WriteRes<WritePCmpIStrILd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 390 let Latency = 17; 391 let ResourceCycles = [17, 1]; 392} 393 394// Packed Compare Explicit Length Strings, Return Index 395def : WriteRes<WritePCmpEStrI, [SLM_FPC_RSV0]> { 396 let Latency = 21; 397 let ResourceCycles = [21]; 398} 399def : WriteRes<WritePCmpEStrILd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 400 let Latency = 21; 401 let ResourceCycles = [21, 1]; 402} 403 404// MOVMSK Instructions. 405def : WriteRes<WriteFMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; } 406def : WriteRes<WriteVecMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; } 407def : WriteRes<WriteVecMOVMSKY, [SLM_FPC_RSV1]> { let Latency = 4; } 408def : WriteRes<WriteMMXMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; } 409 410// AES Instructions. 411def : WriteRes<WriteAESDecEnc, [SLM_FPC_RSV0]> { 412 let Latency = 8; 413 let ResourceCycles = [5]; 414} 415def : WriteRes<WriteAESDecEncLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 416 let Latency = 8; 417 let ResourceCycles = [5, 1]; 418} 419 420def : WriteRes<WriteAESIMC, [SLM_FPC_RSV0]> { 421 let Latency = 8; 422 let ResourceCycles = [5]; 423} 424def : WriteRes<WriteAESIMCLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 425 let Latency = 8; 426 let ResourceCycles = [5, 1]; 427} 428 429def : WriteRes<WriteAESKeyGen, [SLM_FPC_RSV0]> { 430 let Latency = 8; 431 let ResourceCycles = [5]; 432} 433def : WriteRes<WriteAESKeyGenLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 434 let Latency = 8; 435 let ResourceCycles = [5, 1]; 436} 437 438// Carry-less multiplication instructions. 439def : WriteRes<WriteCLMul, [SLM_FPC_RSV0]> { 440 let Latency = 10; 441 let ResourceCycles = [10]; 442} 443def : WriteRes<WriteCLMulLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 444 let Latency = 10; 445 let ResourceCycles = [10, 1]; 446} 447 448def : WriteRes<WriteSystem, [SLM_FPC_RSV0]> { let Latency = 100; } 449def : WriteRes<WriteMicrocoded, [SLM_FPC_RSV0]> { let Latency = 100; } 450def : WriteRes<WriteFence, [SLM_MEC_RSV]>; 451def : WriteRes<WriteNop, []>; 452 453// AVX/FMA is not supported on that architecture, but we should define the basic 454// scheduling resources anyway. 455def : WriteRes<WriteIMulH, [SLM_FPC_RSV0]>; 456defm : X86WriteResPairUnsupported<WriteFBlendY>; 457defm : X86WriteResPairUnsupported<WriteFBlendZ>; 458defm : SLMWriteResPair<WriteVarBlend, [SLM_FPC_RSV0], 1>; 459defm : X86WriteResPairUnsupported<WriteVarBlendY>; 460defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 461defm : SLMWriteResPair<WriteFVarBlend, [SLM_FPC_RSV0], 1>; 462defm : X86WriteResPairUnsupported<WriteFVarBlendY>; 463defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 464defm : X86WriteResPairUnsupported<WriteFShuffle256>; 465defm : X86WriteResPairUnsupported<WriteFVarShuffle256>; 466defm : X86WriteResPairUnsupported<WriteShuffle256>; 467defm : X86WriteResPairUnsupported<WriteVarShuffle256>; 468defm : SLMWriteResPair<WriteVarVecShift, [SLM_FPC_RSV0], 1>; 469defm : X86WriteResPairUnsupported<WriteVarVecShiftY>; 470defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 471defm : X86WriteResPairUnsupported<WriteFMA>; 472defm : X86WriteResPairUnsupported<WriteFMAX>; 473defm : X86WriteResPairUnsupported<WriteFMAY>; 474defm : X86WriteResPairUnsupported<WriteFMAZ>; 475 476defm : X86WriteResPairUnsupported<WriteCvtPH2PS>; 477defm : X86WriteResPairUnsupported<WriteCvtPH2PSY>; 478defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>; 479defm : X86WriteResUnsupported<WriteCvtPS2PH>; 480defm : X86WriteResUnsupported<WriteCvtPS2PHY>; 481defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 482defm : X86WriteResUnsupported<WriteCvtPS2PHSt>; 483defm : X86WriteResUnsupported<WriteCvtPS2PHYSt>; 484defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 485 486} // SchedModel 487