1# RUN: llc -run-pass machine-cse -verify-machineinstrs -mtriple aarch64-apple-ios %s -o - | FileCheck %s 2--- 3name: irtranslated 4legalized: false 5regBankSelected: false 6selected: false 7body: | 8 ; CHECK-LABEL: name: irtranslated 9 ; CHECK: %[[ONE:[0-9]+]]:_(s32) = G_CONSTANT i32 1 10 ; CHECK-NEXT: %[[TWO:[0-9]+]]:_(s32) = G_ADD %[[ONE]], %[[ONE]] 11 ; CHECK-NEXT: %[[SUM:[0-9]+]]:_(s32) = G_ADD %[[TWO]], %[[TWO]] 12 ; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32) 13 ; CHECK-NEXT: RET_ReallyLR implicit $[[RET]] 14 bb.0: 15 %0:_(s32) = G_CONSTANT i32 1 16 %1:_(s32) = G_ADD %0, %0 17 %2:_(s32) = G_ADD %0, %0 18 %3:_(s32) = G_ADD %1, %2 19 $w0 = COPY %3(s32) 20 RET_ReallyLR implicit $w0 21... 22--- 23name: regbankselected 24legalized: true 25regBankSelected: true 26selected: false 27body: | 28 ; CHECK-LABEL: name: regbankselected 29 ; CHECK: %[[ONE:[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 30 ; CHECK-NEXT: %[[TWO:[0-9]+]]:gpr(s32) = G_ADD %[[ONE]], %[[ONE]] 31 ; CHECK-NEXT: %[[SUM:[0-9]+]]:gpr(s32) = G_ADD %[[TWO]], %[[TWO]] 32 ; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32) 33 ; CHECK-NEXT: RET_ReallyLR implicit $[[RET]] 34 bb.0: 35 %0:gpr(s32) = G_CONSTANT i32 1 36 %1:gpr(s32) = G_ADD %0, %0 37 %2:gpr(s32) = G_ADD %0, %0 38 %3:gpr(s32) = G_ADD %1, %2 39 $w0 = COPY %3(s32) 40 RET_ReallyLR implicit $w0 41... 42--- 43name: legalized 44legalized: true 45regBankSelected: false 46selected: false 47body: | 48 ; CHECK-LABEL: name: legalized 49 ; CHECK: %[[ONE:[0-9]+]]:_(s32) = G_CONSTANT i32 1 50 ; CHECK-NEXT: %[[TWO:[0-9]+]]:gpr(s32) = G_ADD %[[ONE]], %[[ONE]] 51 ; CHECK-NEXT: %[[SUM:[0-9]+]]:_(s32) = G_ADD %[[TWO]], %[[TWO]] 52 ; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32) 53 ; CHECK-NEXT: RET_ReallyLR implicit $[[RET]] 54 bb.0: 55 %0:_(s32) = G_CONSTANT i32 1 56 %1:_(s32) = G_ADD %0, %0 57 %2:gpr(s32) = G_ADD %0, %0 58 %3:_(s32) = G_ADD %1, %2 59 $w0 = COPY %3(s32) 60 RET_ReallyLR implicit $w0 61... 62--- 63name: legalized_sym 64legalized: true 65regBankSelected: false 66selected: false 67body: | 68 ; CHECK-LABEL: name: legalized_sym 69 ; CHECK: %[[ONE:[0-9]+]]:_(s32) = G_CONSTANT i32 1 70 ; CHECK-NEXT: %[[TWO:[0-9]+]]:gpr(s32) = G_ADD %[[ONE]], %[[ONE]] 71 ; CHECK-NEXT: %[[SUM:[0-9]+]]:_(s32) = G_ADD %[[TWO]], %[[TWO]] 72 ; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32) 73 ; CHECK-NEXT: RET_ReallyLR implicit $[[RET]] 74 bb.0: 75 %0:_(s32) = G_CONSTANT i32 1 76 %1:gpr(s32) = G_ADD %0, %0 77 %2:_(s32) = G_ADD %0, %0 78 %3:_(s32) = G_ADD %1, %2 79 $w0 = COPY %3(s32) 80 RET_ReallyLR implicit $w0 81... 82--- 83name: int_extensions 84alignment: 2 85legalized: false 86regBankSelected: false 87selected: false 88body: | 89 ; CHECK-LABEL: name: int_extensions 90 ; CHECK: %[[ONE:[0-9]+]]:_(s8) = G_CONSTANT i8 1 91 ; CHECK-NEXT: %[[S16:[0-9]+]]:_(s16) = G_SEXT %[[ONE]](s8) 92 ; CHECK-NEXT: %[[S32:[0-9]+]]:_(s32) = G_SEXT %[[ONE]](s8) 93 ; CHECK-NEXT: %[[S16_Z64:[0-9]+]]:_(s64) = G_ZEXT %[[S16]](s16) 94 ; CHECK-NEXT: %[[S32_Z64:[0-9]+]]:_(s64) = G_ZEXT %[[S32]](s32) 95 ; CHECK-NEXT: %[[SUM:[0-9]+]]:_(s64) = G_ADD %[[S16_Z64]], %[[S32_Z64]] 96 ; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s64) 97 ; CHECK-NEXT: RET_ReallyLR implicit $[[RET]] 98 bb.0.entry: 99 %0:_(s8) = G_CONSTANT i8 1 100 %1:_(s16) = G_SEXT %0(s8) 101 %2:_(s32) = G_SEXT %0(s8) 102 %3:_(s64) = G_ZEXT %1(s16) 103 %4:_(s64) = G_ZEXT %2(s32) 104 %5:_(s64) = G_ADD %3, %4 105 $x0 = COPY %5(s64) 106 RET_ReallyLR implicit $x0 107... 108--- 109name: generic 110legalized: true 111regBankSelected: false 112selected: false 113body: | 114 ; CHECK-LABEL: name: generic 115 ; CHECK: %[[SG:[0-9]+]]:_(s32) = G_ADD %{{[0-9]+}}, %{{[0-9]+}} 116 ; CHECK-NEXT: %{{[0-9]+}}:_(s32) = G_ADD %[[SG]], %[[SG]] 117 bb.0: 118 %0:_(s32) = COPY $w0 119 %1:_(s32) = COPY $w1 120 %2:_(s32) = G_ADD %0, %1 121 %3:_(s32) = COPY %2(s32) 122 %4:_(s32) = G_ADD %3, %3 123 $w0 = COPY %4(s32) 124 RET_ReallyLR implicit $w0 125... 126--- 127name: generic_to_concrete_copy 128legalized: true 129regBankSelected: false 130selected: false 131body: | 132 ; CHECK-LABEL: name: generic_to_concrete_copy 133 ; CHECK: %[[S1:[0-9]+]]:_(s32) = G_ADD %{{[0-9]+}}, %{{[0-9]+}} 134 ; CHECK-NEXT: %[[S2:[0-9]+]]:gpr32 = COPY %[[S1]](s32) 135 ; CHECK-NEXT: %{{[0-9]+}}:gpr32 = ADDWrr %[[S2]], %[[S2]] 136 bb.0: 137 %0:_(s32) = COPY $w0 138 %1:_(s32) = COPY $w1 139 %2:_(s32) = G_ADD %0, %1 140 %3:gpr32 = COPY %2(s32) 141 %4:gpr32 = ADDWrr %3, %3 142 $w0 = COPY %4 143 RET_ReallyLR implicit $w0 144... 145--- 146name: concrete_to_generic_copy 147legalized: true 148regBankSelected: false 149selected: false 150body: | 151 ; CHECK-LABEL: name: concrete_to_generic_copy 152 ; CHECK: %[[S1:[0-9]+]]:gpr32 = ADDWrr %{{[0-9]+}}, %{{[0-9]+}} 153 ; CHECK-NEXT: %[[S2:[0-9]+]]:_(s32) = COPY %[[S1]] 154 ; CHECK-NEXT: %{{[0-9]+}}:_(s32) = G_ADD %[[S2]], %[[S2]] 155 bb.0: 156 %0:gpr32 = COPY $w0 157 %1:gpr32 = COPY $w1 158 %2:gpr32 = ADDWrr %0, %1 159 %3:_(s32) = COPY %2 160 %4:_(s32) = G_ADD %3, %3 161 $w0 = COPY %4(s32) 162 RET_ReallyLR implicit $w0 163... 164--- 165name: concrete 166legalized: true 167regBankSelected: false 168selected: false 169body: | 170 ; CHECK-LABEL: name: concrete 171 ; CHECK: %[[SC:[0-9]+]]:gpr32 = ADDWrr %{{[0-9]+}}, %{{[0-9]+}} 172 ; CHECK-NEXT: %{{[0-9]+}}:gpr32 = ADDWrr %[[SC]], %[[SC]] 173 bb.0: 174 %0:gpr32 = COPY $w0 175 %1:gpr32 = COPY $w1 176 %2:gpr32 = ADDWrr %0, %1 177 %3:gpr32 = COPY %2 178 %4:gpr32 = ADDWrr %3, %3 179 $w0 = COPY %4 180 RET_ReallyLR implicit $w0 181... 182--- 183name: variadic_defs_unmerge_vector 184legalized: true 185regBankSelected: false 186selected: false 187body: | 188 ; CHECK-LABEL: name: variadic_defs_unmerge_vector 189 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 190 ; CHECK-NEXT: [[UV0:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>) 191 ; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s32) = G_ANYEXT [[UV0]](s16) 192 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16) 193 ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16) 194 ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16) 195 ; CHECK-NEXT: [[ADD0:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT0]], [[ANYEXT1]] 196 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT2]], [[ANYEXT3]] 197 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD0]], [[ADD1]] 198 ; CHECK-NEXT: $w0 = COPY [[ADD2]](s32) 199 ; CHECK-NEXT: RET_ReallyLR implicit $w0 200 bb.0: 201 %0 :_(<4 x s16>) = COPY $d0 202 %1 :_(s16), %2 :_(s16), %3 :_(s16), %4 :_(s16) = G_UNMERGE_VALUES %0(<4 x s16>) 203 %5 :_(s16), %6 :_(s16), %7 :_(s16), %8 :_(s16) = G_UNMERGE_VALUES %0(<4 x s16>) 204 %9 :_(s16), %10:_(s16), %11:_(s16), %12:_(s16) = G_UNMERGE_VALUES %0(<4 x s16>) 205 %13:_(s16), %14:_(s16), %15:_(s16), %16:_(s16) = G_UNMERGE_VALUES %0(<4 x s16>) 206 %17:_(s32) = G_ANYEXT %1 (s16) 207 %18:_(s32) = G_ANYEXT %6 (s16) 208 %19:_(s32) = G_ANYEXT %11(s16) 209 %20:_(s32) = G_ANYEXT %16(s16) 210 %21:_(s32) = G_ADD %17, %18 211 %22:_(s32) = G_ADD %19, %20 212 %23:_(s32) = G_ADD %21, %22 213 $w0 = COPY %23(s32) 214 RET_ReallyLR implicit $w0 215... 216--- 217name: variadic_defs_unmerge_scalar 218legalized: true 219regBankSelected: false 220selected: false 221body: | 222 ; CHECK-LABEL: name: variadic_defs_unmerge_scalar 223 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0 224 ; CHECK-NEXT: [[UV0:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](s64) 225 ; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s32) = G_ANYEXT [[UV0]](s16) 226 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16) 227 ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16) 228 ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16) 229 ; CHECK-NEXT: [[ADD0:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT0]], [[ANYEXT1]] 230 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT2]], [[ANYEXT3]] 231 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD0]], [[ADD1]] 232 ; CHECK-NEXT: $w0 = COPY [[ADD2]](s32) 233 ; CHECK-NEXT: RET_ReallyLR implicit $w0 234 bb.0: 235 %0 :_(s64) = COPY $d0 236 %1 :_(s16), %2 :_(s16), %3 :_(s16), %4 :_(s16) = G_UNMERGE_VALUES %0(s64) 237 %5 :_(s16), %6 :_(s16), %7 :_(s16), %8 :_(s16) = G_UNMERGE_VALUES %0(s64) 238 %9 :_(s16), %10:_(s16), %11:_(s16), %12:_(s16) = G_UNMERGE_VALUES %0(s64) 239 %13:_(s16), %14:_(s16), %15:_(s16), %16:_(s16) = G_UNMERGE_VALUES %0(s64) 240 %17:_(s32) = G_ANYEXT %1 (s16) 241 %18:_(s32) = G_ANYEXT %6 (s16) 242 %19:_(s32) = G_ANYEXT %11(s16) 243 %20:_(s32) = G_ANYEXT %16(s16) 244 %21:_(s32) = G_ADD %17, %18 245 %22:_(s32) = G_ADD %19, %20 246 %23:_(s32) = G_ADD %21, %22 247 $w0 = COPY %23(s32) 248 RET_ReallyLR implicit $w0 249... 250--- 251name: variadic_defs_unmerge_scalar_asym 252legalized: true 253regBankSelected: false 254selected: false 255body: | 256 ; CHECK-LABEL: name: variadic_defs_unmerge_scalar_asym 257 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0 258 ; CHECK-NEXT: [[UV0:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](s64) 259 ; CHECK-NEXT: [[UV01:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) 260 ; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s32) = G_ANYEXT [[UV0]](s16) 261 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16) 262 ; CHECK-NEXT: [[ADD0:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT0]], [[ANYEXT1]] 263 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV01]], [[UV23]] 264 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD0]], [[ADD1]] 265 ; CHECK-NEXT: $w0 = COPY [[ADD2]](s32) 266 ; CHECK-NEXT: RET_ReallyLR implicit $w0 267 bb.0: 268 %0 :_(s64) = COPY $d0 269 %1 :_(s16), %2 :_(s16), %3 :_(s16), %4 :_(s16) = G_UNMERGE_VALUES %0(s64) 270 %9 :_(s32), %10:_(s32) = G_UNMERGE_VALUES %0(s64) 271 %5 :_(s16), %6 :_(s16), %7 :_(s16), %8 :_(s16) = G_UNMERGE_VALUES %0(s64) 272 %11:_(s32), %12:_(s32) = G_UNMERGE_VALUES %0(s64) 273 %17:_(s32) = G_ANYEXT %1 (s16) 274 %18:_(s32) = G_ANYEXT %6 (s16) 275 %21:_(s32) = G_ADD %17, %18 276 %22:_(s32) = G_ADD %9, %12 277 %23:_(s32) = G_ADD %21, %22 278 $w0 = COPY %23(s32) 279 RET_ReallyLR implicit $w0 280... 281