1; RUN: llc < %s -mtriple=arm64-apple-ios -aarch64-neon-syntax=apple -no-integrated-as -disable-post-ra | FileCheck %s 2 3; rdar://9167275 4 5define i32 @t1() nounwind ssp { 6entry: 7; CHECK-LABEL: t1: 8; CHECK: mov {{w[0-9]+}}, 7 9 %0 = tail call i32 asm "mov ${0:w}, 7", "=r"() nounwind 10 ret i32 %0 11} 12 13define i64 @t2() nounwind ssp { 14entry: 15; CHECK-LABEL: t2: 16; CHECK: mov {{x[0-9]+}}, 7 17 %0 = tail call i64 asm "mov $0, 7", "=r"() nounwind 18 ret i64 %0 19} 20 21define i64 @t3() nounwind ssp { 22entry: 23; CHECK-LABEL: t3: 24; CHECK: mov {{w[0-9]+}}, 7 25 %0 = tail call i64 asm "mov ${0:w}, 7", "=r"() nounwind 26 ret i64 %0 27} 28 29; rdar://9281206 30 31define void @t4(i64 %op) nounwind { 32entry: 33; CHECK-LABEL: t4: 34; CHECK: mov x0, {{x[0-9]+}}; svc #0 35 %0 = tail call i64 asm sideeffect "mov x0, $1; svc #0;", "=r,r,r,~{x0}"(i64 %op, i64 undef) nounwind 36 ret void 37} 38 39; rdar://9394290 40 41define float @t5(float %x) nounwind { 42entry: 43; CHECK-LABEL: t5: 44; CHECK: fadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} 45 %0 = tail call float asm "fadd ${0:s}, ${0:s}, ${0:s}", "=w,0"(float %x) nounwind 46 ret float %0 47} 48 49; rdar://9553599 50 51define zeroext i8 @t6(i8* %src) nounwind { 52entry: 53; CHECK-LABEL: t6: 54; CHECK: ldtrb {{w[0-9]+}}, [{{x[0-9]+}}] 55 %0 = tail call i8 asm "ldtrb ${0:w}, [$1]", "=r,r"(i8* %src) nounwind 56 ret i8 %0 57} 58 59define void @t7(i8* %f, i32 %g) nounwind { 60entry: 61 %f.addr = alloca i8*, align 8 62 store i8* %f, i8** %f.addr, align 8 63 ; CHECK-LABEL: t7: 64 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}] 65 call void asm "str ${1:w}, $0", "=*Q,r"(i8** %f.addr, i32 %g) nounwind 66 ret void 67} 68 69; rdar://10258229 70; ARM64TargetLowering::getRegForInlineAsmConstraint() should recognize 'v' 71; registers. 72define void @t8() nounwind ssp { 73entry: 74; CHECK-LABEL: t8: 75; CHECK: stp {{d[0-9]+}}, {{d[0-9]+}}, [sp, #-16] 76 tail call void asm sideeffect "nop", "~{v8}"() nounwind 77 ret void 78} 79 80define i32 @constraint_I(i32 %i, i32 %j) nounwind { 81entry: 82 ; CHECK-LABEL: constraint_I: 83 %0 = tail call i32 asm sideeffect "add ${0:w}, ${1:w}, $2", "=r,r,I"(i32 %i, i32 16773120) nounwind 84 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #16773120 85 %1 = tail call i32 asm sideeffect "add ${0:w}, ${1:w}, $2", "=r,r,I"(i32 %i, i32 4096) nounwind 86 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #4096 87 ret i32 %1 88} 89 90define i32 @constraint_J(i32 %i, i32 %j, i64 %k) nounwind { 91entry: 92 ; CHECK-LABEL: constraint_J: 93 %0 = tail call i32 asm sideeffect "sub ${0:w}, ${1:w}, $2", "=r,r,J"(i32 %i, i32 -16773120) nounwind 94 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #-16773120 95 %1 = tail call i32 asm sideeffect "sub ${0:w}, ${1:w}, $2", "=r,r,J"(i32 %i, i32 -1) nounwind 96 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #-1 97 %2 = tail call i64 asm sideeffect "sub ${0:x}, ${1:x}, $2", "=r,r,J"(i64 %k, i32 -1) nounwind 98 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, #-1 99 %3 = tail call i64 asm sideeffect "sub ${0:x}, ${1:x}, $2", "=r,r,J"(i64 %k, i64 -1) nounwind 100 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, #-1 101 ret i32 %1 102} 103 104define i32 @constraint_KL(i32 %i, i32 %j) nounwind { 105entry: 106 ; CHECK-LABEL: constraint_KL: 107 %0 = tail call i32 asm sideeffect "eor ${0:w}, ${1:w}, $2", "=r,r,K"(i32 %i, i32 255) nounwind 108 ; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, #255 109 %1 = tail call i32 asm sideeffect "eor ${0:w}, ${1:w}, $2", "=r,r,L"(i32 %i, i64 16711680) nounwind 110 ; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, #16711680 111 ret i32 %1 112} 113 114define i32 @constraint_MN(i32 %i, i32 %j) nounwind { 115entry: 116 ; CHECK-LABEL: constraint_MN: 117 %0 = tail call i32 asm sideeffect "movk ${0:w}, $1", "=r,M"(i32 65535) nounwind 118 ; CHECK: movk {{w[0-9]+}}, #65535 119 %1 = tail call i32 asm sideeffect "movz ${0:w}, $1", "=r,N"(i64 0) nounwind 120 ; CHECK: movz {{w[0-9]+}}, #0 121 ret i32 %1 122} 123 124define void @t9() nounwind { 125entry: 126 ; CHECK-LABEL: t9: 127 %data = alloca <2 x double>, align 16 128 %0 = load <2 x double>, <2 x double>* %data, align 16 129 call void asm sideeffect "mov.2d v4, $0\0A", "w,~{v4}"(<2 x double> %0) nounwind 130 ; CHECK: mov.2d v4, {{v[0-9]+}} 131 ret void 132} 133 134define void @t10() nounwind { 135entry: 136 ; CHECK-LABEL: t10: 137 %data = alloca <2 x float>, align 8 138 %a = alloca [2 x float], align 4 139 %arraydecay = getelementptr inbounds [2 x float], [2 x float]* %a, i32 0, i32 0 140 %0 = load <2 x float>, <2 x float>* %data, align 8 141 call void asm sideeffect "ldr ${1:q}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind 142 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}] 143 call void asm sideeffect "ldr ${1:d}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind 144 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}] 145 call void asm sideeffect "ldr ${1:s}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind 146 ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}] 147 call void asm sideeffect "ldr ${1:h}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind 148 ; CHECK: ldr {{h[0-9]+}}, [{{x[0-9]+}}] 149 call void asm sideeffect "ldr ${1:b}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind 150 ; CHECK: ldr {{b[0-9]+}}, [{{x[0-9]+}}] 151 ret void 152} 153 154define void @t11() nounwind { 155entry: 156 ; CHECK-LABEL: t11: 157 %a = alloca i32, align 4 158 %0 = load i32, i32* %a, align 4 159 call void asm sideeffect "mov ${1:x}, ${0:x}\0A", "r,i"(i32 %0, i32 0) nounwind 160 ; CHECK: mov xzr, {{x[0-9]+}} 161 %1 = load i32, i32* %a, align 4 162 call void asm sideeffect "mov ${1:w}, ${0:w}\0A", "r,i"(i32 %1, i32 0) nounwind 163 ; CHECK: mov wzr, {{w[0-9]+}} 164 ret void 165} 166 167define void @t12() nounwind { 168entry: 169 ; CHECK-LABEL: t12: 170 %data = alloca <4 x float>, align 16 171 %0 = load <4 x float>, <4 x float>* %data, align 16 172 call void asm sideeffect "mov.2d v4, $0\0A", "x,~{v4}"(<4 x float> %0) nounwind 173 ; CHECK: mov.2d v4, {{v([0-9])|(1[0-5])}} 174 ret void 175} 176 177define void @t13() nounwind { 178entry: 179 ; CHECK-LABEL: t13: 180 tail call void asm sideeffect "mov x4, $0\0A", "N"(i64 1311673391471656960) nounwind 181 ; CHECK: mov x4, #1311673391471656960 182 tail call void asm sideeffect "mov x4, $0\0A", "N"(i64 -4662) nounwind 183 ; CHECK: mov x4, #-4662 184 tail call void asm sideeffect "mov x4, $0\0A", "N"(i64 4660) nounwind 185 ; CHECK: mov x4, #4660 186 call void asm sideeffect "mov x4, $0\0A", "N"(i64 -71777214294589696) nounwind 187 ; CHECK: mov x4, #-71777214294589696 188 ret void 189} 190 191define void @t14() nounwind { 192entry: 193 ; CHECK-LABEL: t14: 194 tail call void asm sideeffect "mov w4, $0\0A", "M"(i32 305397760) nounwind 195 ; CHECK: mov w4, #305397760 196 tail call void asm sideeffect "mov w4, $0\0A", "M"(i32 -4662) nounwind 197 ; CHECK: mov w4, #4294962634 198 tail call void asm sideeffect "mov w4, $0\0A", "M"(i32 4660) nounwind 199 ; CHECK: mov w4, #4660 200 call void asm sideeffect "mov w4, $0\0A", "M"(i32 -16711936) nounwind 201 ; CHECK: mov w4, #4278255360 202 ret void 203} 204 205define void @t15() nounwind { 206entry: 207 %0 = tail call double asm sideeffect "fmov $0, d8", "=r"() nounwind 208 ; CHECK: fmov {{x[0-9]+}}, d8 209 ret void 210} 211 212; rdar://problem/14285178 213 214define void @test_zero_reg(i32* %addr) { 215; CHECK-LABEL: test_zero_reg: 216 217 tail call void asm sideeffect "USE($0)", "z"(i32 0) nounwind 218; CHECK: USE(xzr) 219 220 tail call void asm sideeffect "USE(${0:w})", "zr"(i32 0) 221; CHECK: USE(wzr) 222 223 tail call void asm sideeffect "USE(${0:w})", "zr"(i32 1) 224; CHECK: orr [[VAL1:w[0-9]+]], wzr, #0x1 225; CHECK: USE([[VAL1]]) 226 227 tail call void asm sideeffect "USE($0), USE($1)", "z,z"(i32 0, i32 0) nounwind 228; CHECK: USE(xzr), USE(xzr) 229 230 tail call void asm sideeffect "USE($0), USE(${1:w})", "z,z"(i32 0, i32 0) nounwind 231; CHECK: USE(xzr), USE(wzr) 232 233 ret void 234} 235 236define <2 x float> @test_vreg_64bit(<2 x float> %in) nounwind { 237 ; CHECK-LABEL: test_vreg_64bit: 238 %1 = tail call <2 x float> asm sideeffect "fadd ${0}.2s, ${1}.2s, ${1}.2s", "={v14},w"(<2 x float> %in) nounwind 239 ; CHECK: fadd v14.2s, v0.2s, v0.2s 240 ret <2 x float> %1 241} 242 243define <4 x float> @test_vreg_128bit(<4 x float> %in) nounwind { 244 ; CHECK-LABEL: test_vreg_128bit: 245 %1 = tail call <4 x float> asm sideeffect "fadd ${0}.4s, ${1}.4s, ${1}.4s", "={v14},w"(<4 x float> %in) nounwind 246 ; CHECK: fadd v14.4s, v0.4s, v0.4s 247 ret <4 x float> %1 248} 249 250define void @test_constraint_w(i32 %a) { 251 ; CHECK: fmov [[SREG:s[0-9]+]], {{w[0-9]+}} 252 ; CHECK: sqxtn h0, [[SREG]] 253 254 tail call void asm sideeffect "sqxtn h0, ${0:s}\0A", "w"(i32 %a) 255 ret void 256} 257 258define void @test_inline_modifier_a(i8* %ptr) nounwind { 259 ; CHECK-LABEL: test_inline_modifier_a: 260 tail call void asm sideeffect "prfm pldl1keep, ${0:a}\0A", "r"(i8* %ptr) 261 ; CHECK: prfm pldl1keep, [x0] 262 ret void 263} 264 265; PR33134 266define void @test_zero_address() { 267entry: 268; CHECK-LABEL: test_zero_address 269; CHECK: mov {{x[0-9]+}}, xzr 270; CHECK: ldr {{x[0-9]+}}, {{[x[0-9]+]}} 271 tail call i32 asm sideeffect "ldr $0, $1 \0A", "=r,*Q"(i32* null) 272 ret void 273} 274