1; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=aarch64-apple-darwin < %s | FileCheck %s 2; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=aarch64-apple-darwin -mcpu=cortex-a53 -enable-misched=false < %s | FileCheck %s 3; RUN: llc -verify-machineinstrs -enable-machine-outliner -enable-linkonceodr-outlining -mtriple=aarch64-apple-darwin < %s | FileCheck %s -check-prefix=ODR 4 5define linkonce_odr void @fish() #0 { 6 ; CHECK-LABEL: _fish: 7 ; CHECK-NOT: OUTLINED 8 ; ODR: [[OUTLINED:OUTLINED_FUNCTION_[0-9]+]] 9 %1 = alloca i32, align 4 10 %2 = alloca i32, align 4 11 %3 = alloca i32, align 4 12 %4 = alloca i32, align 4 13 %5 = alloca i32, align 4 14 %6 = alloca i32, align 4 15 store i32 1, i32* %1, align 4 16 store i32 2, i32* %2, align 4 17 store i32 3, i32* %3, align 4 18 store i32 4, i32* %4, align 4 19 store i32 5, i32* %5, align 4 20 store i32 6, i32* %6, align 4 21 ret void 22} 23 24define void @turtle() section "TURTLE,turtle" { 25 ; CHECK-LABEL: _turtle: 26 ; ODR-LABEL: _turtle: 27 ; CHECK-NOT: OUTLINED 28 %1 = alloca i32, align 4 29 %2 = alloca i32, align 4 30 %3 = alloca i32, align 4 31 %4 = alloca i32, align 4 32 %5 = alloca i32, align 4 33 %6 = alloca i32, align 4 34 store i32 1, i32* %1, align 4 35 store i32 2, i32* %2, align 4 36 store i32 3, i32* %3, align 4 37 store i32 4, i32* %4, align 4 38 store i32 5, i32* %5, align 4 39 store i32 6, i32* %6, align 4 40 ret void 41} 42 43define void @cat() #0 { 44 ; CHECK-LABEL: _cat: 45 ; CHECK: [[OUTLINED:OUTLINED_FUNCTION_[0-9]+]] 46 ; ODR: [[OUTLINED]] 47 %1 = alloca i32, align 4 48 %2 = alloca i32, align 4 49 %3 = alloca i32, align 4 50 %4 = alloca i32, align 4 51 %5 = alloca i32, align 4 52 %6 = alloca i32, align 4 53 store i32 1, i32* %1, align 4 54 store i32 2, i32* %2, align 4 55 store i32 3, i32* %3, align 4 56 store i32 4, i32* %4, align 4 57 store i32 5, i32* %5, align 4 58 store i32 6, i32* %6, align 4 59 ret void 60} 61 62define void @dog() #0 { 63 ; CHECK-LABEL: _dog: 64 ; CHECK: [[OUTLINED]] 65 ; ODR: [[OUTLINED]] 66 %1 = alloca i32, align 4 67 %2 = alloca i32, align 4 68 %3 = alloca i32, align 4 69 %4 = alloca i32, align 4 70 %5 = alloca i32, align 4 71 %6 = alloca i32, align 4 72 store i32 1, i32* %1, align 4 73 store i32 2, i32* %2, align 4 74 store i32 3, i32* %3, align 4 75 store i32 4, i32* %4, align 4 76 store i32 5, i32* %5, align 4 77 store i32 6, i32* %6, align 4 78 ret void 79} 80 81; ODR: [[OUTLINED]]: 82; CHECK: .p2align 2 83; CHECK-NEXT: [[OUTLINED]]: 84; CHECK: orr w8, wzr, #0x1 85; CHECK-NEXT: str w8, [sp, #28] 86; CHECK-NEXT: orr w8, wzr, #0x2 87; CHECK-NEXT: str w8, [sp, #24] 88; CHECK-NEXT: orr w8, wzr, #0x3 89; CHECK-NEXT: str w8, [sp, #20] 90; CHECK-NEXT: orr w8, wzr, #0x4 91; CHECK-NEXT: str w8, [sp, #16] 92; CHECK-NEXT: mov w8, #5 93; CHECK-NEXT: str w8, [sp, #12] 94; CHECK-NEXT: orr w8, wzr, #0x6 95; CHECK-NEXT: str w8, [sp, #8] 96; CHECK-NEXT: ret 97 98attributes #0 = { noredzone "target-cpu"="cyclone" } 99