1; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -asm-verbose=false < %s | FileCheck %s 2 3define float @test_dup_sv2S(<2 x float> %v) #0 { 4 ; CHECK-LABEL: test_dup_sv2S: 5 ; CHECK-NEXT: mov s{{[0-9]+}}, {{v[0-9]+}}.s[1] 6 ; CHECK-NEXT: ret 7 %tmp1 = extractelement <2 x float> %v, i32 1 8 ret float %tmp1 9} 10 11define float @test_dup_sv2S_0(<2 x float> %v) #0 { 12 ; CHECK-LABEL: test_dup_sv2S_0: 13 ; CHECK-NOT: dup {{[vsd][0-9]+}} 14 ; CHECK-NOT: ins {{[vsd][0-9]+}} 15 ; CHECK-NEXT: ret 16 %tmp1 = extractelement <2 x float> %v, i32 0 17 ret float %tmp1 18} 19 20define float @test_dup_sv4S(<4 x float> %v) #0 { 21 ; CHECK-LABEL: test_dup_sv4S: 22 ; CHECK-NEXT: mov s{{[0-9]+}}, {{v[0-9]+}}.s[1] 23 ; CHECK-NEXT: ret 24 %tmp1 = extractelement <4 x float> %v, i32 1 25 ret float %tmp1 26} 27 28define float @test_dup_sv4S_0(<4 x float> %v) #0 { 29 ; CHECK-LABEL: test_dup_sv4S_0: 30 ; CHECK-NOT: dup {{[vsd][0-9]+}} 31 ; CHECK-NOT: ins {{[vsd][0-9]+}} 32 ; CHECK-NEXT: ret 33 %tmp1 = extractelement <4 x float> %v, i32 0 34 ret float %tmp1 35} 36 37define double @test_dup_dvD(<1 x double> %v) #0 { 38 ; CHECK-LABEL: test_dup_dvD: 39 ; CHECK-NOT: dup {{[vsd][0-9]+}} 40 ; CHECK-NOT: ins {{[vsd][0-9]+}} 41 ; CHECK-NEXT: ret 42 %tmp1 = extractelement <1 x double> %v, i32 0 43 ret double %tmp1 44} 45 46define double @test_dup_dv2D(<2 x double> %v) #0 { 47 ; CHECK-LABEL: test_dup_dv2D: 48 ; CHECK-NEXT: mov d{{[0-9]+}}, {{v[0-9]+}}.d[1] 49 ; CHECK-NEXT: ret 50 %tmp1 = extractelement <2 x double> %v, i32 1 51 ret double %tmp1 52} 53 54define double @test_dup_dv2D_0(<2 x double> %v) #0 { 55 ; CHECK-LABEL: test_dup_dv2D_0: 56 ; CHECK-NOT: dup {{[vsd][0-9]+}} 57 ; CHECK-NOT: ins {{[vsd][0-9]+}} 58 ; CHECK-NEXT: ret 59 %tmp1 = extractelement <2 x double> %v, i32 0 60 ret double %tmp1 61} 62 63define half @test_dup_hv8H(<8 x half> %v) #0 { 64 ; CHECK-LABEL: test_dup_hv8H: 65 ; CHECK-NEXT: mov h{{[0-9]+}}, {{v[0-9]+}}.h[1] 66 ; CHECK-NEXT: ret 67 %tmp1 = extractelement <8 x half> %v, i32 1 68 ret half %tmp1 69} 70 71define half @test_dup_hv8H_0(<8 x half> %v) #0 { 72 ; CHECK-LABEL: test_dup_hv8H_0: 73 ; CHECK-NOT: dup {{[vsdh][0-9]+}} 74 ; CHECK-NOT: ins {{[vsdh][0-9]+}} 75 ; CHECK-NEXT: ret 76 %tmp1 = extractelement <8 x half> %v, i32 0 77 ret half %tmp1 78} 79 80define <1 x i8> @test_vector_dup_bv16B(<16 x i8> %v1) #0 { 81 ; CHECK-LABEL: test_vector_dup_bv16B: 82 ; CHECK-NEXT: dup v0.8b, v0.b[14] 83 ; CHECK-NEXT: ret 84 %shuffle.i = shufflevector <16 x i8> %v1, <16 x i8> undef, <1 x i32> <i32 14> 85 ret <1 x i8> %shuffle.i 86} 87 88define <1 x i8> @test_vector_dup_bv8B(<8 x i8> %v1) #0 { 89 ; CHECK-LABEL: test_vector_dup_bv8B: 90 ; CHECK-NEXT: dup v0.8b, v0.b[7] 91 ; CHECK-NEXT: ret 92 %shuffle.i = shufflevector <8 x i8> %v1, <8 x i8> undef, <1 x i32> <i32 7> 93 ret <1 x i8> %shuffle.i 94} 95 96define <1 x i16> @test_vector_dup_hv8H(<8 x i16> %v1) #0 { 97 ; CHECK-LABEL: test_vector_dup_hv8H: 98 ; CHECK-NEXT: dup v0.4h, v0.h[7] 99 ; CHECK-NEXT: ret 100 %shuffle.i = shufflevector <8 x i16> %v1, <8 x i16> undef, <1 x i32> <i32 7> 101 ret <1 x i16> %shuffle.i 102} 103 104define <1 x i16> @test_vector_dup_hv4H(<4 x i16> %v1) #0 { 105 ; CHECK-LABEL: test_vector_dup_hv4H: 106 ; CHECK-NEXT: dup v0.4h, v0.h[3] 107 ; CHECK-NEXT: ret 108 %shuffle.i = shufflevector <4 x i16> %v1, <4 x i16> undef, <1 x i32> <i32 3> 109 ret <1 x i16> %shuffle.i 110} 111 112define <1 x i32> @test_vector_dup_sv4S(<4 x i32> %v1) #0 { 113 ; CHECK-LABEL: test_vector_dup_sv4S: 114 ; CHECK-NEXT: dup v0.2s, v0.s[3] 115 ; CHECK-NEXT: ret 116 %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <1 x i32> <i32 3> 117 ret <1 x i32> %shuffle 118} 119 120define <1 x i32> @test_vector_dup_sv2S(<2 x i32> %v1) #0 { 121 ; CHECK-LABEL: test_vector_dup_sv2S: 122 ; CHECK-NEXT: dup v0.2s, v0.s[1] 123 ; CHECK-NEXT: ret 124 %shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <1 x i32> <i32 1> 125 ret <1 x i32> %shuffle 126} 127 128define <1 x i64> @test_vector_dup_dv2D(<2 x i64> %v1) #0 { 129 ; CHECK-LABEL: test_vector_dup_dv2D: 130 ; CHECK-NEXT: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #8 131 ; CHECK-NEXT: ret 132 %shuffle.i = shufflevector <2 x i64> %v1, <2 x i64> undef, <1 x i32> <i32 1> 133 ret <1 x i64> %shuffle.i 134} 135 136define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) #0 { 137 ; CHECK-LABEL: test_vector_copy_dup_dv2D: 138 ; CHECK-NEXT: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #8 139 ; CHECK-NEXT: ret 140 %vget_lane = extractelement <2 x i64> %c, i32 1 141 %vset_lane = insertelement <1 x i64> undef, i64 %vget_lane, i32 0 142 ret <1 x i64> %vset_lane 143} 144 145; Undefined behaviour, so we really don't care what actually gets emitted, just 146; as long as we don't crash (since it could be dynamically unreachable). 147define i32 @test_out_of_range_extract(<4 x i32> %vec) { 148; CHECK-LABEL: test_out_of_range_extract: 149; CHECK: ret 150 %elt = extractelement <4 x i32> %vec, i32 4 151 ret i32 %elt 152} 153 154; Undefined behaviour, so we really don't care what actually gets emitted, just 155; as long as we don't crash (since it could be dynamically unreachable). 156define void @test_out_of_range_insert(<4 x i32> %vec, i32 %elt) { 157; CHECK-LABEL: test_out_of_range_insert: 158; CHECK: ret 159 insertelement <4 x i32> %vec, i32 %elt, i32 4 160 ret void 161} 162 163attributes #0 = { nounwind } 164