1; RUN: llc -verify-machineinstrs -o - %s | FileCheck %s 2target triple = "arm64--" 3 4; AArch64InstrInfo::optimizeCondBranch() optimizes the 5; "x = and y, 256; cmp x, 0; br" from an "and; cbnz" to a tbnz instruction. 6; It forgot to clear the a flag resulting in a MachineVerifier complaint. 7; 8; Writing a stable/simple test is tricky since most tbz instructions are already 9; formed in SelectionDAG, optimizeCondBranch() only triggers if the and 10; instruction is in a different block than the conditional jump. 11; 12; CHECK-LABEL: func 13; CHECK-NOT: and 14; CHECK: tbz 15define void @func() { 16 %c0 = icmp sgt i64 0, 0 17 br i1 %c0, label %b1, label %b6 18 19b1: 20 br i1 undef, label %b3, label %b2 21 22b2: 23 %v0 = tail call i32 @extfunc() 24 br label %b5 25 26b3: 27 %v1 = load i32, i32* undef, align 4 28 %v2 = and i32 %v1, 256 29 br label %b5 30 31b5: 32 %v3 = phi i32 [ %v2, %b3 ], [ %v0, %b2 ] 33 %c1 = icmp eq i32 %v3, 0 34 br i1 %c1, label %b8, label %b7 35 36b6: 37 tail call i32 @extfunc() 38 ret void 39 40b7: 41 tail call i32 @extfunc() 42 ret void 43 44b8: 45 ret void 46} 47 48declare i32 @extfunc() 49