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1; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tahiti -mattr=-promote-alloca < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI %s
2; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tahiti -mattr=+promote-alloca < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s
3
4declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
5declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1
6declare void @llvm.amdgcn.s.barrier() #2
7
8; The required pointer calculations for the alloca'd actually requires
9; an add and won't be folded into the addressing, which fails with a
10; 64-bit pointer add. This should work since private pointers should
11; be 32-bits.
12
13; SI-LABEL: {{^}}test_private_array_ptr_calc:
14
15; SI-ALLOCA: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 16, v{{[0-9]+}}
16; SI-ALLOCA: buffer_store_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:64
17; SI-ALLOCA: s_barrier
18; SI-ALLOCA: buffer_load_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:64
19;
20; FIXME: The AMDGPUPromoteAlloca pass should be able to convert this
21; alloca to a vector.  It currently fails because it does not know how
22; to interpret:
23; getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 1, i32 %b
24
25; SI-PROMOTE: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 64
26; SI-PROMOTE: ds_write_b32 [[PTRREG]]
27define amdgpu_kernel void @test_private_array_ptr_calc(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) #0 {
28  %alloca = alloca [16 x i32], align 16, addrspace(5)
29  %mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0);
30  %tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo)
31  %a_ptr = getelementptr inbounds i32, i32 addrspace(1)* %inA, i32 %tid
32  %b_ptr = getelementptr inbounds i32, i32 addrspace(1)* %inB, i32 %tid
33  %a = load i32, i32 addrspace(1)* %a_ptr, !range !0
34  %b = load i32, i32 addrspace(1)* %b_ptr, !range !0
35  %result = add i32 %a, %b
36  %alloca_ptr = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 1, i32 %b
37  store i32 %result, i32 addrspace(5)* %alloca_ptr, align 4
38  ; Dummy call
39  call void @llvm.amdgcn.s.barrier()
40  %reload = load i32, i32 addrspace(5)* %alloca_ptr, align 4, !range !0
41  %out_ptr = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid
42  store i32 %reload, i32 addrspace(1)* %out_ptr, align 4
43  ret void
44}
45
46attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,1" }
47attributes #1 = { nounwind readnone }
48attributes #2 = { nounwind convergent }
49
50!0 = !{i32 0, i32 65536 }
51