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1; RUN: llc -march=r600 -mcpu=redwood -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
2; RUN: FileCheck --check-prefix=BUG64 %s < %t
3
4; RUN: llc -march=r600 -mcpu=sumo -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
5; RUN: FileCheck --check-prefix=BUG64 %s < %t
6
7; RUN: llc -march=r600 -mcpu=barts -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
8; RUN: FileCheck --check-prefix=BUG64 %s < %t
9
10; RUN: llc -march=r600 -mcpu=turks -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
11; RUN: FileCheck --check-prefix=BUG64 %s < %t
12
13; RUN: llc -march=r600 -mcpu=caicos -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
14; RUN: FileCheck --check-prefix=BUG64 %s < %t
15
16; RUN: llc -march=r600 -mcpu=cedar -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
17; RUN: FileCheck --check-prefix=BUG32 %s < %t
18
19; RUN: llc -march=r600 -mcpu=juniper -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
20; RUN: FileCheck --check-prefix=NOBUG %s < %t
21
22; RUN: llc -march=r600 -mcpu=cypress -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
23; RUN: FileCheck --check-prefix=NOBUG %s < %t
24
25; RUN: llc -march=r600 -mcpu=cayman -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
26; RUN: FileCheck --check-prefix=NOBUG %s < %t
27
28; REQUIRES: asserts
29
30; We are currently allocating 2 extra sub-entries on Evergreen / NI for
31; non-WQM push instructions if we change this to 1, then we will need to
32; add one level of depth to each of these tests.
33
34; BUG64-NOT: Applying bug work-around
35; BUG32-NOT: Applying bug work-around
36; NOBUG-NOT: Applying bug work-around
37; FUNC-LABEL: {{^}}nested3:
38define amdgpu_kernel void @nested3(i32 addrspace(1)* %out, i32 %cond) {
39entry:
40  %0 = icmp sgt i32 %cond, 0
41  br i1 %0, label %if.1, label %end
42
43if.1:
44  %1 = icmp sgt i32 %cond, 10
45  br i1 %1, label %if.2, label %if.store.1
46
47if.store.1:
48  store i32 1, i32 addrspace(1)* %out
49  br label %end
50
51if.2:
52  %2 = icmp sgt i32 %cond, 20
53  br i1 %2, label %if.3, label %if.2.store
54
55if.2.store:
56  store i32 2, i32 addrspace(1)* %out
57  br label %end
58
59if.3:
60  store i32 3, i32 addrspace(1)* %out
61  br label %end
62
63end:
64  ret void
65}
66
67; BUG64: Applying bug work-around
68; BUG32-NOT: Applying bug work-around
69; NOBUG-NOT: Applying bug work-around
70; FUNC-LABEL: {{^}}nested4:
71define amdgpu_kernel void @nested4(i32 addrspace(1)* %out, i32 %cond) {
72entry:
73  %0 = icmp sgt i32 %cond, 0
74  br i1 %0, label %if.1, label %end
75
76if.1:
77  %1 = icmp sgt i32 %cond, 10
78  br i1 %1, label %if.2, label %if.1.store
79
80if.1.store:
81  store i32 1, i32 addrspace(1)* %out
82  br label %end
83
84if.2:
85  %2 = icmp sgt i32 %cond, 20
86  br i1 %2, label %if.3, label %if.2.store
87
88if.2.store:
89  store i32 2, i32 addrspace(1)* %out
90  br label %end
91
92if.3:
93  %3 = icmp sgt i32 %cond, 30
94  br i1 %3, label %if.4, label %if.3.store
95
96if.3.store:
97  store i32 3, i32 addrspace(1)* %out
98  br label %end
99
100if.4:
101  store i32 4, i32 addrspace(1)* %out
102  br label %end
103
104end:
105  ret void
106}
107
108; BUG64: Applying bug work-around
109; BUG32-NOT: Applying bug work-around
110; NOBUG-NOT: Applying bug work-around
111; FUNC-LABEL: {{^}}nested7:
112define amdgpu_kernel void @nested7(i32 addrspace(1)* %out, i32 %cond) {
113entry:
114  %0 = icmp sgt i32 %cond, 0
115  br i1 %0, label %if.1, label %end
116
117if.1:
118  %1 = icmp sgt i32 %cond, 10
119  br i1 %1, label %if.2, label %if.1.store
120
121if.1.store:
122  store i32 1, i32 addrspace(1)* %out
123  br label %end
124
125if.2:
126  %2 = icmp sgt i32 %cond, 20
127  br i1 %2, label %if.3, label %if.2.store
128
129if.2.store:
130  store i32 2, i32 addrspace(1)* %out
131  br label %end
132
133if.3:
134  %3 = icmp sgt i32 %cond, 30
135  br i1 %3, label %if.4, label %if.3.store
136
137if.3.store:
138  store i32 3, i32 addrspace(1)* %out
139  br label %end
140
141if.4:
142  %4 = icmp sgt i32 %cond, 40
143  br i1 %4, label %if.5, label %if.4.store
144
145if.4.store:
146  store i32 4, i32 addrspace(1)* %out
147  br label %end
148
149if.5:
150  %5 = icmp sgt i32 %cond, 50
151  br i1 %5, label %if.6, label %if.5.store
152
153if.5.store:
154  store i32 5, i32 addrspace(1)* %out
155  br label %end
156
157if.6:
158  %6 = icmp sgt i32 %cond, 60
159  br i1 %6, label %if.7, label %if.6.store
160
161if.6.store:
162  store i32 6, i32 addrspace(1)* %out
163  br label %end
164
165if.7:
166  store i32 7, i32 addrspace(1)* %out
167  br label %end
168
169end:
170  ret void
171}
172
173; BUG64: Applying bug work-around
174; BUG32: Applying bug work-around
175; NOBUG-NOT: Applying bug work-around
176; FUNC-LABEL: {{^}}nested8:
177define amdgpu_kernel void @nested8(i32 addrspace(1)* %out, i32 %cond) {
178entry:
179  %0 = icmp sgt i32 %cond, 0
180  br i1 %0, label %if.1, label %end
181
182if.1:
183  %1 = icmp sgt i32 %cond, 10
184  br i1 %1, label %if.2, label %if.1.store
185
186if.1.store:
187  store i32 1, i32 addrspace(1)* %out
188  br label %end
189
190if.2:
191  %2 = icmp sgt i32 %cond, 20
192  br i1 %2, label %if.3, label %if.2.store
193
194if.2.store:
195  store i32 2, i32 addrspace(1)* %out
196  br label %end
197
198if.3:
199  %3 = icmp sgt i32 %cond, 30
200  br i1 %3, label %if.4, label %if.3.store
201
202if.3.store:
203  store i32 3, i32 addrspace(1)* %out
204  br label %end
205
206if.4:
207  %4 = icmp sgt i32 %cond, 40
208  br i1 %4, label %if.5, label %if.4.store
209
210if.4.store:
211  store i32 4, i32 addrspace(1)* %out
212  br label %end
213
214if.5:
215  %5 = icmp sgt i32 %cond, 50
216  br i1 %5, label %if.6, label %if.5.store
217
218if.5.store:
219  store i32 5, i32 addrspace(1)* %out
220  br label %end
221
222if.6:
223  %6 = icmp sgt i32 %cond, 60
224  br i1 %6, label %if.7, label %if.6.store
225
226if.6.store:
227  store i32 6, i32 addrspace(1)* %out
228  br label %end
229
230if.7:
231  %7 = icmp sgt i32 %cond, 70
232  br i1 %7, label %if.8, label %if.7.store
233
234if.7.store:
235  store i32 7, i32 addrspace(1)* %out
236  br label %end
237
238if.8:
239  store i32 8, i32 addrspace(1)* %out
240  br label %end
241
242end:
243  ret void
244}
245