1; RUN: llc -march=amdgcn -mcpu=bonaire -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s 2; RUN: llc -march=amdgcn -mcpu=carrizo --show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s 3; RUN: llc -march=amdgcn -mcpu=gfx900 --show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=ALL %s 4; RUN: llc -march=amdgcn -mcpu=bonaire -mtriple=amdgcn-unknown-amdhsa < %s -mattr=-flat-for-global | FileCheck -check-prefix=GCNHSA -check-prefix=CIHSA -check-prefix=ALL %s 5; RUN: llc -march=amdgcn -mcpu=carrizo -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCNHSA -check-prefix=VIHSA -check-prefix=ALL %s 6 7; FIXME: align on alloca seems to be ignored for private_segment_alignment 8 9; ALL-LABEL: {{^}}large_alloca_compute_shader: 10 11; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0 12; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0 13; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1 14; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD1 15; GCN-DAG: s_mov_b32 s{{[0-9]+}}, -1 16; CI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe8f000 17; VI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe80000 18; GFX9-DAG: s_mov_b32 s{{[0-9]+}}, 0xe00000 19 20 21; GCNHSA: .amd_kernel_code_t 22 23; GCNHSA: enable_sgpr_private_segment_wave_byte_offset = 1 24; GCNHSA: user_sgpr_count = 8 25; GCNHSA: enable_sgpr_workgroup_id_x = 1 26; GCNHSA: enable_sgpr_workgroup_id_y = 0 27; GCNHSA: enable_sgpr_workgroup_id_z = 0 28; GCNHSA: enable_sgpr_workgroup_info = 0 29; GCNHSA: enable_vgpr_workitem_id = 0 30 31; GCNHSA: enable_sgpr_private_segment_buffer = 1 32; GCNHSA: enable_sgpr_dispatch_ptr = 0 33; GCNHSA: enable_sgpr_queue_ptr = 0 34; GCNHSA: enable_sgpr_kernarg_segment_ptr = 1 35; GCNHSA: enable_sgpr_dispatch_id = 0 36; GCNHSA: enable_sgpr_flat_scratch_init = 1 37; GCNHSA: enable_sgpr_private_segment_size = 0 38; GCNHSA: enable_sgpr_grid_workgroup_count_x = 0 39; GCNHSA: enable_sgpr_grid_workgroup_count_y = 0 40; GCNHSA: enable_sgpr_grid_workgroup_count_z = 0 41; GCNHSA: workitem_private_segment_byte_size = 32772 42; GCNHSA: private_segment_alignment = 4 43; GCNHSA: .end_amd_kernel_code_t 44 45 46; GCNHSA: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], s9 offen 47; GCNHSA: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], s9 offen 48 49; Scratch size = alloca size + emergency stack slot, align {{.*}}, addrspace(5) 50; ALL: ; ScratchSize: 32772 51define amdgpu_kernel void @large_alloca_compute_shader(i32 %x, i32 %y) #0 { 52 %large = alloca [8192 x i32], align 4, addrspace(5) 53 %gep = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 8191 54 store volatile i32 %x, i32 addrspace(5)* %gep 55 %gep1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 %y 56 %val = load volatile i32, i32 addrspace(5)* %gep1 57 store volatile i32 %val, i32 addrspace(1)* undef 58 ret void 59} 60 61attributes #0 = { nounwind } 62