1; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -strict-whitespace -check-prefixes=GCN,SI %s 2; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -strict-whitespace -check-prefixes=GCN,VI %s 3 4; FIXME: Enable for VI. 5 6declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 7declare float @llvm.amdgcn.div.fmas.f32(float, float, float, i1) nounwind readnone 8declare double @llvm.amdgcn.div.fmas.f64(double, double, double, i1) nounwind readnone 9 10; GCN-LABEL: {{^}}test_div_fmas_f32: 11; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x13 12; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c 13; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x25 14 15; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x4c 16; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x70 17; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x94 18 19; GCN-DAG: s_and_b32 [[AND_I1:s[0-9]+]], 1, s{{[0-9]+}} 20; GCN: v_cmp_eq_u32_e64 vcc, [[AND_I1]], 1 21 22; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] 23; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] 24; GCN-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]] 25; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], [[VC]] 26; GCN: buffer_store_dword [[RESULT]], 27define amdgpu_kernel void @test_div_fmas_f32(float addrspace(1)* %out, [8 x i32], float %a, [8 x i32], float %b, [8 x i32], float %c, [8 x i32], i1 %d) nounwind { 28 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %d) nounwind readnone 29 store float %result, float addrspace(1)* %out, align 4 30 ret void 31} 32 33; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_0: 34; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c 35; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x25 36; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] 37; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] 38; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VB]], [[VC]] 39; SI: buffer_store_dword [[RESULT]], 40define amdgpu_kernel void @test_div_fmas_f32_inline_imm_0(float addrspace(1)* %out, [8 x i32], float %a, [8 x i32], float %b, [8 x i32], float %c, [8 x i32], i1 %d) nounwind { 41 %result = call float @llvm.amdgcn.div.fmas.f32(float 1.0, float %b, float %c, i1 %d) nounwind readnone 42 store float %result, float addrspace(1)* %out, align 4 43 ret void 44} 45 46; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_1: 47; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb 48; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd 49 50; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x4c 51; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x94 52 53; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] 54; GCN-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]] 55; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], 1.0, [[VC]] 56; GCN: buffer_store_dword [[RESULT]], 57define amdgpu_kernel void @test_div_fmas_f32_inline_imm_1(float addrspace(1)* %out, float %a, float %b, float %c, [8 x i32], i1 %d) nounwind { 58 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float 1.0, float %c, i1 %d) nounwind readnone 59 store float %result, float addrspace(1)* %out, align 4 60 ret void 61} 62 63; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_2: 64; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x13 65; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c 66 67; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x4c 68; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x70 69 70; GCN-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]] 71; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] 72; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], 1.0 73; GCN: buffer_store_dword [[RESULT]], 74define amdgpu_kernel void @test_div_fmas_f32_inline_imm_2(float addrspace(1)* %out, [8 x i32], float %a, [8 x i32], float %b, [8 x i32], float %c, [8 x i32], i1 %d) nounwind { 75 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float 1.0, i1 %d) nounwind readnone 76 store float %result, float addrspace(1)* %out, align 4 77 ret void 78} 79 80; GCN-LABEL: {{^}}test_div_fmas_f64: 81; GCN: v_div_fmas_f64 82define amdgpu_kernel void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c, i1 %d) nounwind { 83 %result = call double @llvm.amdgcn.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone 84 store double %result, double addrspace(1)* %out, align 8 85 ret void 86} 87 88; GCN-LABEL: {{^}}test_div_fmas_f32_cond_to_vcc: 89; GCN: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0{{$}} 90; GCN: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} 91define amdgpu_kernel void @test_div_fmas_f32_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c, i32 %i) nounwind { 92 %cmp = icmp eq i32 %i, 0 93 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %cmp) nounwind readnone 94 store float %result, float addrspace(1)* %out, align 4 95 ret void 96} 97 98; GCN-LABEL: {{^}}test_div_fmas_f32_imm_false_cond_to_vcc: 99; GCN: s_mov_b64 vcc, 0 100; GCN: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} 101define amdgpu_kernel void @test_div_fmas_f32_imm_false_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind { 102 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 false) nounwind readnone 103 store float %result, float addrspace(1)* %out, align 4 104 ret void 105} 106 107; GCN-LABEL: {{^}}test_div_fmas_f32_imm_true_cond_to_vcc: 108; GCN: s_mov_b64 vcc, -1 109; GCN: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} 110define amdgpu_kernel void @test_div_fmas_f32_imm_true_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind { 111 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 true) nounwind readnone 112 store float %result, float addrspace(1)* %out, align 4 113 ret void 114} 115 116; GCN-LABEL: {{^}}test_div_fmas_f32_logical_cond_to_vcc: 117; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 118; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} 119; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} 120 121; SI-DAG: v_cmp_eq_u32_e32 [[CMP0:vcc]], 0, v{{[0-9]+}} 122; SI-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}} 123; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]] 124; SI: v_div_fmas_f32 {{v[0-9]+}}, [[A]], [[B]], [[C]] 125; SI: s_endpgm 126define amdgpu_kernel void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 %d) nounwind { 127 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 128 %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid 129 %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1 130 %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2 131 %gep.out = getelementptr float, float addrspace(1)* %out, i32 2 132 133 %a = load volatile float, float addrspace(1)* %gep.a 134 %b = load volatile float, float addrspace(1)* %gep.b 135 %c = load volatile float, float addrspace(1)* %gep.c 136 137 %cmp0 = icmp eq i32 %tid, 0 138 %cmp1 = icmp ne i32 %d, 0 139 %and = and i1 %cmp0, %cmp1 140 141 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %and) nounwind readnone 142 store float %result, float addrspace(1)* %gep.out, align 4 143 ret void 144} 145 146; GCN-LABEL: {{^}}test_div_fmas_f32_i1_phi_vcc: 147; SI: v_cmp_eq_u32_e32 vcc, 0, v{{[0-9]+}} 148; SI: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], vcc 149 150; SI: buffer_load_dword [[LOAD:v[0-9]+]] 151; SI: v_cmp_ne_u32_e32 vcc, 0, [[LOAD]] 152; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc 153 154 155; SI: BB9_2: 156; SI: s_or_b64 exec, exec, [[SAVE]] 157; SI: v_cmp_ne_u32_e32 vcc, 0, v{{[0-9]+}} 158; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} 159; SI: buffer_store_dword 160; SI: s_endpgm 161define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 addrspace(1)* %dummy) nounwind { 162entry: 163 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 164 %gep.out = getelementptr float, float addrspace(1)* %out, i32 2 165 %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid 166 %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1 167 %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2 168 169 %a = load float, float addrspace(1)* %gep.a 170 %b = load float, float addrspace(1)* %gep.b 171 %c = load float, float addrspace(1)* %gep.c 172 173 %cmp0 = icmp eq i32 %tid, 0 174 br i1 %cmp0, label %bb, label %exit 175 176bb: 177 %val = load i32, i32 addrspace(1)* %dummy 178 %cmp1 = icmp ne i32 %val, 0 179 br label %exit 180 181exit: 182 %cond = phi i1 [false, %entry], [%cmp1, %bb] 183 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %cond) nounwind readnone 184 store float %result, float addrspace(1)* %gep.out, align 4 185 ret void 186} 187