1; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-OPT %s 2; RUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOOPT %s 3 4; VI-LABEL: {{^}}dpp_test: 5; VI: v_mov_b32_e32 v0, s{{[0-9]+}} 6; VI: v_mov_b32_e32 v1, s{{[0-9]+}} 7; VI-OPT: s_nop 1 8; VI-NOOPT: s_nop 0 9; VI-NOOPT: s_nop 0 10; VI: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x01,0x01,0x08,0x11] 11define amdgpu_kernel void @dpp_test(i32 addrspace(1)* %out, i32 %in1, i32 %in2) { 12 %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 1) #0 13 store i32 %tmp0, i32 addrspace(1)* %out 14 ret void 15} 16 17; VI-LABEL: {{^}}dpp_test1: 18; VI-OPT: v_add_u32_e32 [[REG:v[0-9]+]], vcc, v{{[0-9]+}}, v{{[0-9]+}} 19; VI-NOOPT: v_mov_b32_e32 v{{[0-9]+}}, 0 20; VI-NOOPT: v_mov_b32_e32 [[REG:v[0-9]+]], v{{[0-9]+}} 21; VI-NEXT: s_nop 0 22; VI-NEXT: s_nop 0 23; VI-NEXT: v_mov_b32_dpp v2, [[REG]] quad_perm:[1,0,3,2] row_mask:0xf bank_mask:0xf 24@0 = internal unnamed_addr addrspace(3) global [448 x i32] undef, align 4 25define weak_odr amdgpu_kernel void @dpp_test1(i32* %arg) local_unnamed_addr { 26bb: 27 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() 28 %tmp1 = zext i32 %tmp to i64 29 %tmp2 = getelementptr inbounds [448 x i32], [448 x i32] addrspace(3)* @0, i32 0, i32 %tmp 30 %tmp3 = load i32, i32 addrspace(3)* %tmp2, align 4 31 fence syncscope("workgroup") release 32 tail call void @llvm.amdgcn.s.barrier() 33 fence syncscope("workgroup") acquire 34 %tmp4 = add nsw i32 %tmp3, %tmp3 35 %tmp5 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp4, i32 177, i32 15, i32 15, i1 zeroext false) 36 %tmp6 = add nsw i32 %tmp5, %tmp4 37 %tmp7 = getelementptr inbounds i32, i32* %arg, i64 %tmp1 38 store i32 %tmp6, i32* %tmp7, align 4 39 ret void 40} 41 42declare i32 @llvm.amdgcn.workitem.id.x() 43declare void @llvm.amdgcn.s.barrier() 44declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) #0 45 46attributes #0 = { nounwind readnone convergent } 47