1; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s 2; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s 3 4declare half @llvm.sin.f16(half %a) 5declare <2 x half> @llvm.sin.v2f16(<2 x half> %a) 6 7; GCN-LABEL: {{^}}sin_f16: 8; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] 9; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] 10; GCN: v_mul_f32_e32 v[[M_F32:[0-9]+]], {{0.15915494|0x3e22f983}}, v[[A_F32]] 11; GCN: v_fract_f32_e32 v[[F_F32:[0-9]+]], v[[M_F32]] 12; GCN: v_sin_f32_e32 v[[R_F32:[0-9]+]], v[[F_F32]] 13; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] 14; GCN: buffer_store_short v[[R_F16]] 15; GCN: s_endpgm 16define amdgpu_kernel void @sin_f16( 17 half addrspace(1)* %r, 18 half addrspace(1)* %a) { 19entry: 20 %a.val = load half, half addrspace(1)* %a 21 %r.val = call half @llvm.sin.f16(half %a.val) 22 store half %r.val, half addrspace(1)* %r 23 ret void 24} 25 26; GCN-LABEL: {{^}}sin_v2f16: 27; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]] 28; SI: v_mov_b32_e32 v[[HALF_PI:[0-9]+]], 0x3e22f983{{$}} 29 30; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] 31; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] 32; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] 33; SI: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], v[[A_F32_0]], v[[HALF_PI]] 34; SI: v_fract_f32_e32 v[[F_F32_0:[0-9]+]], v[[M_F32_0]] 35; SI: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], v[[A_F32_1]], v[[HALF_PI]] 36; SI: v_fract_f32_e32 v[[F_F32_1:[0-9]+]], v[[M_F32_1]] 37; SI: v_sin_f32_e32 v[[R_F32_1:[0-9]+]], v[[F_F32_1]] 38; SI: v_sin_f32_e32 v[[R_F32_0:[0-9]+]], v[[F_F32_0]] 39; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] 40 41; VI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] 42; VI-DAG: v_cvt_f32_f16_sdwa v[[A_F32_1:[0-9]+]], v[[A_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 43; VI-DAG: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], 0.15915494, v[[A_F32_0]] 44; VI-DAG: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], 0.15915494, v[[A_F32_1]] 45; VI-DAG: v_fract_f32_e32 v[[F_F32_0:[0-9]+]], v[[M_F32_0]] 46; VI-DAG: v_fract_f32_e32 v[[F_F32_1:[0-9]+]], v[[M_F32_1]] 47; VI: v_sin_f32_e32 v[[R_F32_1:[0-9]+]], v[[F_F32_1]] 48; VI: v_sin_f32_e32 v[[R_F32_0:[0-9]+]], v[[F_F32_0]] 49 50; GCN-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] 51 52; SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] 53; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]] 54 55; VI-DAG: v_cvt_f16_f32_sdwa v[[R_F16_1:[0-9]+]], v[[R_F32_1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 56; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_1]] 57 58; GCN: buffer_store_dword v[[R_V2_F16]] 59; GCN: s_endpgm 60define amdgpu_kernel void @sin_v2f16( 61 <2 x half> addrspace(1)* %r, 62 <2 x half> addrspace(1)* %a) { 63entry: 64 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a 65 %r.val = call <2 x half> @llvm.sin.v2f16(<2 x half> %a.val) 66 store <2 x half> %r.val, <2 x half> addrspace(1)* %r 67 ret void 68} 69