1; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s 2 3; This test just checks that the compiler doesn't crash. 4 5 6; FUNC-LABEL: {{^}}i8ptr_v16i8ptr: 7; EG: MEM_RAT_CACHELESS STORE_RAW [[DATA:T[0-9]+\.XYZW]], [[ST_PTR:T[0-9]+\.[XYZW]]] 8; EG: VTX_READ_128 [[DATA]], [[LD_PTR:T[0-9]+\.[XYZW]]] 9; EG-DAG: MOV {{[\* ]*}}[[LD_PTR]], KC0[2].Z 10; EG-DAG: LSHR {{[\* ]*}}[[ST_PTR]], KC0[2].Y, literal 11define amdgpu_kernel void @i8ptr_v16i8ptr(<16 x i8> addrspace(1)* %out, i8 addrspace(1)* %in) { 12entry: 13 %0 = bitcast i8 addrspace(1)* %in to <16 x i8> addrspace(1)* 14 %1 = load <16 x i8>, <16 x i8> addrspace(1)* %0 15 store <16 x i8> %1, <16 x i8> addrspace(1)* %out 16 ret void 17} 18 19; FUNC-LABEL: {{^}}f32_to_v2i16: 20; EG: MEM_RAT_CACHELESS STORE_RAW [[DATA:T[0-9]+\.[XYZW]]], [[ST_PTR:T[0-9]+\.[XYZW]]] 21; EG: VTX_READ_32 [[DATA]], [[LD_PTR:T[0-9]+\.[XYZW]]] 22; EG-DAG: MOV {{[\* ]*}}[[LD_PTR]], KC0[2].Z 23; EG-DAG: LSHR {{[\* ]*}}[[ST_PTR]], KC0[2].Y, literal 24define amdgpu_kernel void @f32_to_v2i16(<2 x i16> addrspace(1)* %out, float addrspace(1)* %in) nounwind { 25 %load = load float, float addrspace(1)* %in, align 4 26 %bc = bitcast float %load to <2 x i16> 27 store <2 x i16> %bc, <2 x i16> addrspace(1)* %out, align 4 28 ret void 29} 30 31; FUNC-LABEL: {{^}}v2i16_to_f32: 32; EG: MEM_RAT_CACHELESS STORE_RAW [[DATA:T[0-9]+\.[XYZW]]], [[ST_PTR:T[0-9]+\.[XYZW]]] 33; EG: VTX_READ_32 [[DATA]], [[LD_PTR:T[0-9]+\.[XYZW]]] 34; EG-DAG: MOV {{[\* ]*}}[[LD_PTR]], KC0[2].Z 35; EG-DAG: LSHR {{[\* ]*}}[[ST_PTR]], KC0[2].Y, literal 36define amdgpu_kernel void @v2i16_to_f32(float addrspace(1)* %out, <2 x i16> addrspace(1)* %in) nounwind { 37 %load = load <2 x i16>, <2 x i16> addrspace(1)* %in, align 4 38 %bc = bitcast <2 x i16> %load to float 39 store float %bc, float addrspace(1)* %out, align 4 40 ret void 41} 42 43; FUNC-LABEL: {{^}}v4i8_to_i32: 44; EG: MEM_RAT_CACHELESS STORE_RAW [[DATA:T[0-9]+\.[XYZW]]], [[ST_PTR:T[0-9]+\.[XYZW]]] 45; EG: VTX_READ_32 [[DATA]], [[LD_PTR:T[0-9]+\.[XYZW]]] 46; EG-DAG: MOV {{[\* ]*}}[[LD_PTR]], KC0[2].Z 47; EG-DAG: LSHR {{[\* ]*}}[[ST_PTR]], KC0[2].Y, literal 48define amdgpu_kernel void @v4i8_to_i32(i32 addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind { 49 %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4 50 %bc = bitcast <4 x i8> %load to i32 51 store i32 %bc, i32 addrspace(1)* %out, align 4 52 ret void 53} 54 55; FUNC-LABEL: {{^}}i32_to_v4i8: 56; EG: MEM_RAT_CACHELESS STORE_RAW [[DATA:T[0-9]+\.[XYZW]]], [[ST_PTR:T[0-9]+\.[XYZW]]] 57; EG: VTX_READ_32 [[DATA]], [[LD_PTR:T[0-9]+\.[XYZW]]] 58; EG-DAG: MOV {{[\* ]*}}[[LD_PTR]], KC0[2].Z 59; EG-DAG: LSHR {{[\* ]*}}[[ST_PTR]], KC0[2].Y, literal 60define amdgpu_kernel void @i32_to_v4i8(<4 x i8> addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 61 %load = load i32, i32 addrspace(1)* %in, align 4 62 %bc = bitcast i32 %load to <4 x i8> 63 store <4 x i8> %bc, <4 x i8> addrspace(1)* %out, align 4 64 ret void 65} 66 67; FUNC-LABEL: {{^}}v2i16_to_v4i8: 68; EG: MEM_RAT_CACHELESS STORE_RAW [[DATA:T[0-9]+\.[XYZW]]], [[ST_PTR:T[0-9]+\.[XYZW]]] 69; EG: VTX_READ_32 [[DATA]], [[LD_PTR:T[0-9]+\.[XYZW]]] 70; EG-DAG: MOV {{[\* ]*}}[[LD_PTR]], KC0[2].Z 71; EG-DAG: LSHR {{[\* ]*}}[[ST_PTR]], KC0[2].Y, literal 72define amdgpu_kernel void @v2i16_to_v4i8(<4 x i8> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) nounwind { 73 %load = load <2 x i16>, <2 x i16> addrspace(1)* %in, align 4 74 %bc = bitcast <2 x i16> %load to <4 x i8> 75 store <4 x i8> %bc, <4 x i8> addrspace(1)* %out, align 4 76 ret void 77} 78 79; This just checks for crash in BUILD_VECTOR/EXTRACT_ELEMENT combine 80; the stack manipulation is tricky to follow 81; TODO: This should only use one load 82; FUNC-LABEL: {{^}}v4i16_extract_i8: 83; EG: MEM_RAT MSKOR {{T[0-9]+\.XW}}, [[ST_PTR:T[0-9]+\.[XYZW]]] 84; EG: VTX_READ_16 85; EG: VTX_READ_16 86; EG-DAG: BFE_UINT 87; EG-DAG: LSHR {{[\* ]*}}[[ST_PTR]], KC0[2].Y, literal 88define amdgpu_kernel void @v4i16_extract_i8(i8 addrspace(1)* %out, <4 x i16> addrspace(1)* %in) nounwind { 89 %load = load <4 x i16>, <4 x i16> addrspace(1)* %in, align 2 90 %bc = bitcast <4 x i16> %load to <8 x i8> 91 %element = extractelement <8 x i8> %bc, i32 5 92 store i8 %element, i8 addrspace(1)* %out 93 ret void 94} 95 96; FUNC-LABEL: {{^}}bitcast_v2i32_to_f64: 97; EG: MEM_RAT_CACHELESS STORE_RAW [[DATA:T[0-9]+\.XY]], [[ST_PTR:T[0-9]+\.[XYZW]]] 98; EG: VTX_READ_64 [[DATA]], [[LD_PTR:T[0-9]+\.[XYZW]]] 99; EG-DAG: MOV {{[\* ]*}}[[LD_PTR]], KC0[2].Z 100; EG-DAG: LSHR {{[\* ]*}}[[ST_PTR]], KC0[2].Y, literal 101define amdgpu_kernel void @bitcast_v2i32_to_f64(double addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { 102 %val = load <2 x i32>, <2 x i32> addrspace(1)* %in, align 8 103 %bc = bitcast <2 x i32> %val to double 104 store double %bc, double addrspace(1)* %out, align 8 105 ret void 106} 107 108