1; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s 2; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s 3; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=EG -check-prefix=FUNC %s 4 5declare i32 @llvm.r600.read.tidig.x() #0 6 7; FUNC-LABEL: {{^}}lshr_i32: 8; SI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 9; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 10; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 11define amdgpu_kernel void @lshr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { 12 %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 13 %a = load i32, i32 addrspace(1)* %in 14 %b = load i32, i32 addrspace(1)* %b_ptr 15 %result = lshr i32 %a, %b 16 store i32 %result, i32 addrspace(1)* %out 17 ret void 18} 19 20; FUNC-LABEL: {{^}}lshr_v2i32: 21; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 22; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 23 24; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 25; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 26 27; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 28; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 29define amdgpu_kernel void @lshr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { 30 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1 31 %a = load <2 x i32>, <2 x i32> addrspace(1)* %in 32 %b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr 33 %result = lshr <2 x i32> %a, %b 34 store <2 x i32> %result, <2 x i32> addrspace(1)* %out 35 ret void 36} 37 38; FUNC-LABEL: {{^}}lshr_v4i32: 39; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 40; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 41; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 42; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 43 44; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 45; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 46; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 47; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 48 49; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 50; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 51; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 52; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 53define amdgpu_kernel void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { 54 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1 55 %a = load <4 x i32>, <4 x i32> addrspace(1)* %in 56 %b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr 57 %result = lshr <4 x i32> %a, %b 58 store <4 x i32> %result, <4 x i32> addrspace(1)* %out 59 ret void 60} 61 62; FUNC-LABEL: {{^}}lshr_i64: 63; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 64; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 65 66; EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]] 67; EG: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}} 68; EG-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal 69; EG-DAG: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1 70; EG-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]] 71; EG-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]|PS}}, {{[[OVERF]]|PV.[XYZW]}} 72; EG-DAG: LSHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]|PV\.[XYZW]}} 73; EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal 74; EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]|PS}} 75; EG-DAG: LSHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], [[SHIFT]] 76; EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0 77define amdgpu_kernel void @lshr_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { 78 %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1 79 %a = load i64, i64 addrspace(1)* %in 80 %b = load i64, i64 addrspace(1)* %b_ptr 81 %result = lshr i64 %a, %b 82 store i64 %result, i64 addrspace(1)* %out 83 ret void 84} 85 86; FUNC-LABEL: {{^}}lshr_v2i64: 87; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 88; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 89 90; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 91; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 92 93; EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] 94; EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] 95; EG-DAG: LSHL {{\*? *}}[[COMPSHA]] 96; EG-DAG: LSHL {{\*? *}}[[COMPSHB]] 97; EG-DAG: LSHL {{.*}}, 1 98; EG-DAG: LSHL {{.*}}, 1 99; EG-DAG: LSHR {{.*}}, [[SHA]] 100; EG-DAG: LSHR {{.*}}, [[SHB]] 101; EG-DAG: LSHR {{.*}}, [[SHA]] 102; EG-DAG: LSHR {{.*}}, [[SHB]] 103; EG-DAG: OR_INT 104; EG-DAG: OR_INT 105; EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal 106; EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal 107; EG-DAG: LSHR 108; EG-DAG: LSHR 109; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal 110; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal 111; EG-DAG: CNDE_INT {{.*}}, 0.0 112; EG-DAG: CNDE_INT {{.*}}, 0.0 113; EG-DAG: CNDE_INT 114; EG-DAG: CNDE_INT 115define amdgpu_kernel void @lshr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) { 116 %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1 117 %a = load <2 x i64>, <2 x i64> addrspace(1)* %in 118 %b = load <2 x i64>, <2 x i64> addrspace(1)* %b_ptr 119 %result = lshr <2 x i64> %a, %b 120 store <2 x i64> %result, <2 x i64> addrspace(1)* %out 121 ret void 122} 123 124; FUNC-LABEL: {{^}}lshr_v4i64: 125; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 126; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 127; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 128; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 129 130; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 131; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 132; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 133; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 134 135; EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] 136; EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] 137; EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]] 138; EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]] 139; EG-DAG: LSHL {{\*? *}}[[COMPSHA]] 140; EG-DAG: LSHL {{\*? *}}[[COMPSHB]] 141; EG-DAG: LSHL {{\*? *}}[[COMPSHC]] 142; EG-DAG: LSHL {{\*? *}}[[COMPSHD]] 143; EG-DAG: LSHL {{.*}}, 1 144; EG-DAG: LSHL {{.*}}, 1 145; EG-DAG: LSHL {{.*}}, 1 146; EG-DAG: LSHL {{.*}}, 1 147; EG-DAG: LSHR {{.*}}, [[SHA]] 148; EG-DAG: LSHR {{.*}}, [[SHB]] 149; EG-DAG: LSHR {{.*}}, [[SHC]] 150; EG-DAG: LSHR {{.*}}, [[SHD]] 151; EG-DAG: LSHR {{.*}}, [[SHA]] 152; EG-DAG: LSHR {{.*}}, [[SHB]] 153; EG-DAG: LSHR {{.*}}, [[SHC]] 154; EG-DAG: LSHR {{.*}}, [[SHD]] 155; EG-DAG: OR_INT 156; EG-DAG: OR_INT 157; EG-DAG: OR_INT 158; EG-DAG: OR_INT 159; EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal 160; EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal 161; EG-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal 162; EG-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal 163; EG-DAG: LSHR 164; EG-DAG: LSHR 165; EG-DAG: LSHR 166; EG-DAG: LSHR 167; EG-DAG: LSHR 168; EG-DAG: LSHR 169; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal 170; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal 171; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal 172; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal 173; EG-DAG: CNDE_INT {{.*}}, 0.0 174; EG-DAG: CNDE_INT {{.*}}, 0.0 175; EG-DAG: CNDE_INT {{.*}}, 0.0 176; EG-DAG: CNDE_INT {{.*}}, 0.0 177; EG-DAG: CNDE_INT 178; EG-DAG: CNDE_INT 179; EG-DAG: CNDE_INT 180; EG-DAG: CNDE_INT 181define amdgpu_kernel void @lshr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) { 182 %b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1 183 %a = load <4 x i64>, <4 x i64> addrspace(1)* %in 184 %b = load <4 x i64>, <4 x i64> addrspace(1)* %b_ptr 185 %result = lshr <4 x i64> %a, %b 186 store <4 x i64> %result, <4 x i64> addrspace(1)* %out 187 ret void 188} 189 190; Make sure load width gets reduced to i32 load. 191; GCN-LABEL: {{^}}s_lshr_32_i64: 192; GCN-DAG: s_load_dword [[HI_A:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x14{{$}} 193; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], 0{{$}} 194; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], [[HI_A]] 195; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} 196define amdgpu_kernel void @s_lshr_32_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) { 197 %result = lshr i64 %a, 32 198 store i64 %result, i64 addrspace(1)* %out 199 ret void 200} 201 202; GCN-LABEL: {{^}}v_lshr_32_i64: 203; GCN-DAG: buffer_load_dword v[[HI_A:[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 204; GCN-DAG: v_mov_b32_e32 v[[VHI1:[0-9]+]], 0{{$}} 205; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], v[[VHI1]]{{$}} 206; GCN: buffer_store_dwordx2 v{{\[}}[[HI_A]]:[[VHI]]{{\]}} 207define amdgpu_kernel void @v_lshr_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { 208 %tid = call i32 @llvm.r600.read.tidig.x() #0 209 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid 210 %gep.out = getelementptr i64, i64 addrspace(1)* %out, i32 %tid 211 %a = load i64, i64 addrspace(1)* %gep.in 212 %result = lshr i64 %a, 32 213 store i64 %result, i64 addrspace(1)* %gep.out 214 ret void 215} 216 217attributes #0 = { nounwind readnone } 218