1; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s 2 3; RUN: llc -mtriple=amdgcn--amdhsa -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s 4; RUN: llc -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP %s 5; RUN: llc -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s 6 7; enable trap handler feature 8; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP %s 9; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT %s 10 11; disable trap handler feature 12; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP %s 13; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s 14 15; RUN: llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s 16 17declare void @llvm.trap() #0 18declare void @llvm.debugtrap() #1 19 20; MESA-TRAP: .section .AMDGPU.config 21; MESA-TRAP: .long 47180 22; MESA-TRAP-NEXT: .long 208 23 24; NOMESA-TRAP: .section .AMDGPU.config 25; NOMESA-TRAP: .long 47180 26; NOMESA-TRAP-NEXT: .long 144 27 28; GCN-LABEL: {{^}}hsa_trap: 29; HSA-TRAP: enable_trap_handler = 0 30; HSA-TRAP: s_mov_b64 s[0:1], s[4:5] 31; HSA-TRAP: s_trap 2 32 33; for llvm.trap in hsa path without ABI, direct generate s_endpgm instruction without any warning information 34; NO-HSA-TRAP: enable_trap_handler = 0 35; NO-HSA-TRAP: s_endpgm 36; NO-HSA-TRAP: COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 37 38; TRAP-BIT: enable_trap_handler = 1 39; NO-TRAP-BIT: enable_trap_handler = 0 40; NO-MESA-TRAP: s_endpgm 41define amdgpu_kernel void @hsa_trap(i32 addrspace(1)* nocapture readonly %arg0) { 42 store volatile i32 1, i32 addrspace(1)* %arg0 43 call void @llvm.trap() 44 unreachable 45 store volatile i32 2, i32 addrspace(1)* %arg0 46 ret void 47} 48 49; MESA-TRAP: .section .AMDGPU.config 50; MESA-TRAP: .long 47180 51; MESA-TRAP-NEXT: .long 208 52 53; NOMESA-TRAP: .section .AMDGPU.config 54; NOMESA-TRAP: .long 47180 55; NOMESA-TRAP-NEXT: .long 144 56 57; GCN-WARNING: warning: <unknown>:0:0: in function hsa_debugtrap void (i32 addrspace(1)*): debugtrap handler not supported 58; GCN-LABEL: {{^}}hsa_debugtrap: 59; HSA-TRAP: enable_trap_handler = 0 60; HSA-TRAP: s_trap 3 61; HSA-TRAP: flat_store_dword v[0:1], v3 62 63; for llvm.debugtrap in non-hsa path without ABI, generate a warning and a s_endpgm instruction 64; NO-HSA-TRAP: enable_trap_handler = 0 65; NO-HSA-TRAP: s_endpgm 66 67; TRAP-BIT: enable_trap_handler = 1 68; NO-TRAP-BIT: enable_trap_handler = 0 69; NO-MESA-TRAP: s_endpgm 70define amdgpu_kernel void @hsa_debugtrap(i32 addrspace(1)* nocapture readonly %arg0) { 71 store volatile i32 1, i32 addrspace(1)* %arg0 72 call void @llvm.debugtrap() 73 store volatile i32 2, i32 addrspace(1)* %arg0 74 ret void 75} 76 77; For non-HSA path 78; GCN-LABEL: {{^}}trap: 79; TRAP-BIT: enable_trap_handler = 1 80; NO-TRAP-BIT: enable_trap_handler = 0 81; NO-HSA-TRAP: s_endpgm 82; NO-MESA-TRAP: s_endpgm 83define amdgpu_kernel void @trap(i32 addrspace(1)* nocapture readonly %arg0) { 84 store volatile i32 1, i32 addrspace(1)* %arg0 85 call void @llvm.trap() 86 unreachable 87 store volatile i32 2, i32 addrspace(1)* %arg0 88 ret void 89} 90 91; GCN-LABEL: {{^}}non_entry_trap: 92; TRAP-BIT: enable_trap_handler = 1 93; NO-TRAP-BIT: enable_trap_handler = 0 94 95; HSA-TRAP: BB{{[0-9]_[0-9]+}}: ; %trap 96; HSA-TRAP: s_mov_b64 s[0:1], s[4:5] 97; HSA-TRAP-NEXT: s_trap 2 98define amdgpu_kernel void @non_entry_trap(i32 addrspace(1)* nocapture readonly %arg0) local_unnamed_addr { 99entry: 100 %tmp29 = load volatile i32, i32 addrspace(1)* %arg0 101 %cmp = icmp eq i32 %tmp29, -1 102 br i1 %cmp, label %ret, label %trap 103 104trap: 105 call void @llvm.trap() 106 unreachable 107 108ret: 109 store volatile i32 3, i32 addrspace(1)* %arg0 110 ret void 111} 112 113attributes #0 = { nounwind noreturn } 114attributes #1 = { nounwind } 115