1; RUN: llc -mtriple=arm-eabi -float-abi=hard -mcpu=cortex-a15 -mattr=+neon,+neonfp %s -o - \ 2; RUN: | FileCheck %s 3 4; This test checks that the VMLxForwarting feature is disabled for A15. 5; CHECK: fun_a: 6define <4 x i32> @fun_a(<4 x i32> %x, <4 x i32> %y) nounwind{ 7 %1 = add <4 x i32> %x, %y 8; CHECK-NOT: vmul 9; CHECK: vmla 10 %2 = mul <4 x i32> %1, %1 11 %3 = add <4 x i32> %y, %2 12 ret <4 x i32> %3 13} 14 15; This tests checks that VMLA FP patterns can be matched in instruction selection when targeting 16; Cortex-A15. 17; CHECK: fun_b: 18define <4 x float> @fun_b(<4 x float> %x, <4 x float> %y, <4 x float> %z) nounwind{ 19; CHECK: vmla.f32 20 %t = fmul <4 x float> %x, %y 21 %r = fadd <4 x float> %t, %z 22 ret <4 x float> %r 23} 24 25; This tests checks that FP VMLA instructions are not expanded into separate multiply/addition 26; operations when targeting Cortex-A15. 27; CHECK: fun_c: 28define <4 x float> @fun_c(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %u, <4 x float> %v) nounwind{ 29; CHECK: vmla.f32 30 %t1 = fmul <4 x float> %x, %y 31 %r1 = fadd <4 x float> %t1, %z 32; CHECK: vmla.f32 33 %t2 = fmul <4 x float> %u, %v 34 %r2 = fadd <4 x float> %t2, %r1 35 ret <4 x float> %r2 36} 37 38