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1; RUN: llc -mtriple=armv7-linux < %s | FileCheck %s
2
3declare arm_aapcscc void @addrof_i32(i32*)
4declare arm_aapcscc void @addrof_i64(i64*)
5
6define arm_aapcscc void @simple(i32, i32, i32, i32, i32 %x) {
7entry:
8  %x.addr = alloca i32
9  store i32 %x, i32* %x.addr
10  call void @addrof_i32(i32* %x.addr)
11  ret void
12}
13
14; CHECK-LABEL: simple:
15; CHECK: push {r11, lr}
16; CHECK: add r0, sp, #8
17; CHECK: bl addrof_i32
18; CHECK: pop {r11, pc}
19
20
21; We need to load %x before calling addrof_i32 now because it could mutate %x in
22; place.
23
24define arm_aapcscc i32 @use_arg(i32, i32, i32, i32, i32 %x) {
25entry:
26  %x.addr = alloca i32
27  store i32 %x, i32* %x.addr
28  call void @addrof_i32(i32* %x.addr)
29  ret i32 %x
30}
31
32; CHECK-LABEL: use_arg:
33; CHECK: push {[[csr:[^ ]*]], lr}
34; CHECK: add r0, sp, #8
35; CHECK: ldr [[csr]], [sp, #8]
36; CHECK: bl addrof_i32
37; CHECK: mov r0, [[csr]]
38; CHECK: pop {[[csr]], pc}
39
40
41define arm_aapcscc i64 @split_i64(i32, i32, i32, i32, i64 %x) {
42entry:
43  %x.addr = alloca i64, align 4
44  store i64 %x, i64* %x.addr, align 4
45  call void @addrof_i64(i64* %x.addr)
46  ret i64 %x
47}
48
49; CHECK-LABEL: split_i64:
50; CHECK: push    {r4, r5, r11, lr}
51; CHECK: sub     sp, sp, #8
52; CHECK: ldr     r4, [sp, #28]
53; CHECK: mov     r0, sp
54; CHECK: ldr     r5, [sp, #24]
55; CHECK: str     r4, [sp, #4]
56; CHECK: str     r5, [sp]
57; CHECK: bl      addrof_i64
58; CHECK: mov     r0, r5
59; CHECK: mov     r1, r4
60; CHECK: add     sp, sp, #8
61; CHECK: pop     {r4, r5, r11, pc}
62