1; RUN: llc -mtriple=thumbv7m -arm-disable-cgp=false %s -o - | FileCheck %s 2; RUN: llc -mtriple=thumbv8m.main -arm-disable-cgp=false %s -o - | FileCheck %s 3; RUN: llc -mtriple=thumbv7 %s -arm-disable-cgp=false -o - | FileCheck %s 4; RUN: llc -mtriple=armv8 %s -arm-disable-cgp=false -o - | FileCheck %s 5 6; Test to check that ARMCodeGenPrepare doesn't optimised away sign extends. 7; CHECK-LABEL: test_signed_load: 8; CHECK: uxth 9define i16 @test_signed_load(i16* %ptr) { 10 %load = load i16, i16* %ptr 11 %conv0 = zext i16 %load to i32 12 %conv1 = sext i16 %load to i32 13 %cmp = icmp eq i32 %conv0, %conv1 14 %conv2 = zext i1 %cmp to i16 15 ret i16 %conv2 16} 17 18; Don't allow sign bit generating opcodes. 19; CHECK-LABEL: test_ashr: 20; CHECK: sxth 21define i16 @test_ashr(i16 zeroext %arg) { 22 %ashr = ashr i16 %arg, 1 23 %cmp = icmp eq i16 %ashr, 0 24 %conv = zext i1 %cmp to i16 25 ret i16 %conv 26} 27 28; CHECK-LABEL: test_sdiv: 29; CHECK: sxth 30define i16 @test_sdiv(i16 zeroext %arg) { 31 %sdiv = sdiv i16 %arg, 2 32 %cmp = icmp ne i16 %sdiv, 0 33 %conv = zext i1 %cmp to i16 34 ret i16 %conv 35} 36 37; CHECK-LABEL: test_srem 38; CHECK: sxth 39define i16 @test_srem(i16 zeroext %arg) { 40 %srem = srem i16 %arg, 4 41 %cmp = icmp ne i16 %srem, 0 42 %conv = zext i1 %cmp to i16 43 ret i16 %conv 44} 45 46