1; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s 2; 3; Alias check: check that the rewrite isn't triggered when there's a store 4; instruction possibly aliasing any mul load operands; arguments are passed 5; without 'restrict' enabled. 6; 7; CHECK-NOT: call i32 @llvm.arm.smlad 8; 9define dso_local i32 @test(i32 %arg, i32* nocapture %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) { 10entry: 11 %cmp24 = icmp sgt i32 %arg, 0 12 br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup 13 14for.body.preheader: 15 %.pre = load i16, i16* %arg3, align 2 16 %.pre27 = load i16, i16* %arg2, align 2 17 br label %for.body 18 19for.cond.cleanup: 20 %mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ] 21 ret i32 %mac1.0.lcssa 22 23for.body: 24 %mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ] 25 %i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ] 26 %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025 27 %0 = load i16, i16* %arrayidx, align 2 28 29; Store inserted here, aliasing with arrayidx, arrayidx1, arrayidx3 30 store i16 42, i16* %arrayidx, align 2 31 32 %add = add nuw nsw i32 %i.025, 1 33 %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add 34 %1 = load i16, i16* %arrayidx1, align 2 35 %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025 36 %2 = load i16, i16* %arrayidx3, align 2 37 %conv = sext i16 %2 to i32 38 %conv4 = sext i16 %0 to i32 39 %mul = mul nsw i32 %conv, %conv4 40 %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add 41 %3 = load i16, i16* %arrayidx6, align 2 42 %conv7 = sext i16 %3 to i32 43 %conv8 = sext i16 %1 to i32 44 %mul9 = mul nsw i32 %conv7, %conv8 45 %add10 = add i32 %mul, %mac1.026 46 %add11 = add i32 %mul9, %add10 47 %exitcond = icmp ne i32 %add, %arg 48 br i1 %exitcond, label %for.body, label %for.cond.cleanup 49} 50 51