1; RUN: llc -mtriple=armv7-apple-ios6.0 -mcpu=swift < %s | FileCheck %s 2; RUN: llc -mtriple=armv7-apple-ios6.0 < %s | FileCheck %s --check-prefix=CHECK-STRICT-ATOMIC 3 4; Release operations only need the store barrier provided by a "dmb ishst", 5 6define void @test_store_release(i32* %p, i32 %v) { 7; CHECK-LABEL: test_store_release: 8; CHECK: dmb ishst 9; CHECK: str 10 11; CHECK-STRICT-ATOMIC-LABEL: test_store_release: 12; CHECK-STRICT-ATOMIC: dmb {{ish$}} 13 store atomic i32 %v, i32* %p release, align 4 14 ret void 15} 16 17; However, if sequential consistency is needed *something* must ensure a release 18; followed by an acquire does not get reordered. In that case a "dmb ishst" is 19; not adequate. 20define i32 @test_seq_cst(i32* %p, i32 %v) { 21; CHECK-LABEL: test_seq_cst: 22; CHECK: dmb ishst 23; CHECK: str 24; CHECK: dmb {{ish$}} 25; CHECK: ldr 26; CHECK: dmb {{ish$}} 27 28; CHECK-STRICT-ATOMIC-LABEL: test_seq_cst: 29; CHECK-STRICT-ATOMIC: dmb {{ish$}} 30; CHECK-STRICT-ATOMIC: str 31; CHECK-STRICT-ATOMIC: dmb {{ish$}} 32; CHECK-STRICT-ATOMIC: ldr 33; CHECK-STRICT-ATOMIC: dmb {{ish$}} 34 35 store atomic i32 %v, i32* %p seq_cst, align 4 36 %val = load atomic i32, i32* %p seq_cst, align 4 37 ret i32 %val 38} 39 40; Also, pure acquire operations should definitely not have an ishst barrier. 41 42define i32 @test_acq(i32* %addr) { 43; CHECK-LABEL: test_acq: 44; CHECK: ldr 45; CHECK: dmb {{ish$}} 46 47; CHECK-STRICT-ATOMIC-LABEL: test_acq: 48; CHECK-STRICT-ATOMIC: dmb {{ish$}} 49 %val = load atomic i32, i32* %addr acquire, align 4 50 ret i32 %val 51} 52