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1; RUN: llc -march=hexagon < %s | FileCheck %s
2
3; This testcase exposed a problem with a previous handling of selecting
4; constant vectors (for vdelta). Originally a bitcast of a vsplat was
5; created (both being ISD, not machine nodes). Selection of vsplat relies
6; on its return type, and there was no way to get these nodes to be
7; selected in the right order, without getting the main selection algorithm
8; confused.
9
10; Make sure this compiles successfully.
11; CHECK: call f1
12
13target triple = "hexagon"
14
15%s.0 = type { %s.1 }
16%s.1 = type { i32, i8* }
17%s.2 = type { i8, i8, [16 x i8], i8, [16 x i8] }
18
19; Function Attrs: nounwind
20define dso_local zeroext i8 @f0(i8 zeroext %a0, %s.2* nocapture readonly %a1, i8 signext %a2) local_unnamed_addr #0 {
21b0:
22  br i1 undef, label %b2, label %b1
23
24b1:                                               ; preds = %b0
25  %v0 = load <64 x i8>, <64 x i8>* undef, align 1
26  %v1 = icmp ult <64 x i8> %v0, <i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52>
27  %v2 = xor <64 x i1> %v1, zeroinitializer
28  %v3 = select <64 x i1> %v2, <64 x i32> undef, <64 x i32> zeroinitializer
29  %v4 = select <64 x i1> zeroinitializer, <64 x i32> <i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000>, <64 x i32> %v3
30  %v5 = add <64 x i32> %v4, zeroinitializer
31  br label %b2
32
33b2:                                               ; preds = %b1, %b0
34  %v6 = phi <64 x i32> [ undef, %b0 ], [ %v5, %b1 ]
35  %v7 = add <64 x i32> %v6, undef
36  %v8 = add <64 x i32> %v7, undef
37  %v9 = add <64 x i32> %v8, undef
38  %v10 = add <64 x i32> %v9, undef
39  %v11 = add <64 x i32> %v10, undef
40  %v12 = add <64 x i32> %v11, undef
41  %v13 = extractelement <64 x i32> %v12, i32 0
42  tail call void @f1(%s.0* null, i32 undef, i32 undef, i32 %v13, i32 undef) #2
43  unreachable
44}
45
46declare dso_local void @f1(%s.0*, i32, i32, i32, i32) local_unnamed_addr #1
47
48attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
49attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
50attributes #2 = { nounwind }
51