1# RUN: llc -march=hexagon -run-pass expand-condsets -o - %s -verify-machineinstrs -debug-only=expand-condsets 2>&1 | FileCheck %s 2# REQUIRES: asserts 3 4# Check that coalesced registers are removed from live intervals. 5# 6# Check that %3 is coalesced into %4, and that after coalescing 7# it is no longer in live intervals. 8 9# CHECK-LABEL: After expand-condsets 10# CHECK: INTERVALS 11# CHECK-NOT: %3 12# CHECK: MACHINEINSTRS 13 14 15--- | 16 define void @fred() { ret void } 17 18... 19--- 20 21name: fred 22tracksRegLiveness: true 23registers: 24 - { id: 0, class: intregs } 25 - { id: 1, class: intregs } 26 - { id: 2, class: predregs } 27 - { id: 3, class: intregs } 28 - { id: 4, class: intregs } 29liveins: 30 - { reg: '$r0', virtual-reg: '%0' } 31 - { reg: '$r1', virtual-reg: '%1' } 32 - { reg: '$p0', virtual-reg: '%2' } 33 34body: | 35 bb.0: 36 liveins: $r0, $r1, $p0 37 %0 = COPY $r0 38 %0 = COPY $r0 ; Force isSSA = false. 39 %1 = COPY $r1 40 %2 = COPY $p0 41 ; Check that %3 was coalesced into %4. 42 ; CHECK: %4:intregs = A2_abs %1 43 ; CHECK: %4:intregs = A2_tfrt killed %2, killed %0, implicit %4 44 %3 = A2_abs %1 45 %4 = C2_mux %2, %0, %3 46 $r0 = COPY %4 47 J2_jumpr $r31, implicit $r0, implicit-def $pc 48... 49 50