1; RUN: llc -march=hexagon < %s | FileCheck %s 2 3; After register allocation it is possible to have a spill of a register 4; that is only partially defined. That in itself it fine, but creates a 5; problem for double vector registers. Stores of such registers are pseudo 6; instructions that are expanded into pairs of individual vector stores, 7; and in case of a partially defined source, one of the stores may use 8; an entirely undefined register. 9; 10; This testcase used to crash. Make sure we can handle it, and that we 11; do generate a store for the defined part of W0: 12 13; CHECK-LABEL: fred: 14; CHECK: v[[REG:[0-9]+]] = vsplat 15; CHECK: vmem(r29+#{{[0-9]+}}) = v[[REG]] 16 17 18target triple = "hexagon" 19 20declare void @danny() local_unnamed_addr #0 21declare void @sammy() local_unnamed_addr #0 22declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #1 23declare <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32) #1 24declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #1 25declare <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32>, <32 x i32>) #1 26declare <32 x i32> @llvm.hexagon.V6.vlsrh.128B(<32 x i32>, i32) #1 27declare <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32>, <64 x i32>) #1 28 29define hidden void @fred() #2 { 30b0: 31 %v1 = load i32, i32* null, align 4 32 %v2 = icmp ult i64 0, 2147483648 33 br i1 %v2, label %b3, label %b5 34 35b3: ; preds = %b0 36 %v4 = icmp sgt i32 0, -1 37 br i1 %v4, label %b6, label %b5 38 39b5: ; preds = %b3, %b0 40 ret void 41 42b6: ; preds = %b3 43 tail call void @danny() 44 br label %b7 45 46b7: ; preds = %b21, %b6 47 %v8 = icmp sgt i32 %v1, 0 48 %v9 = select i1 %v8, i32 %v1, i32 0 49 %v10 = select i1 false, i32 0, i32 %v9 50 %v11 = icmp slt i32 %v10, 0 51 %v12 = select i1 %v11, i32 %v10, i32 0 52 %v13 = icmp slt i32 0, %v12 53 br i1 %v13, label %b14, label %b18 54 55b14: ; preds = %b16, %b7 56 br i1 false, label %b15, label %b16 57 58b15: ; preds = %b14 59 br label %b16 60 61b16: ; preds = %b15, %b14 62 %v17 = icmp eq i32 0, %v12 63 br i1 %v17, label %b18, label %b14 64 65b18: ; preds = %b16, %b7 66 tail call void @danny() 67 %v19 = tail call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 524296) #0 68 %v20 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %v19, <32 x i32> %v19) 69 br label %b22 70 71b21: ; preds = %b22 72 tail call void @sammy() #3 73 br label %b7 74 75b22: ; preds = %b22, %b18 76 %v23 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> zeroinitializer, <64 x i32> %v20) #0 77 %v24 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v23) 78 %v25 = tail call <32 x i32> @llvm.hexagon.V6.vlsrh.128B(<32 x i32> %v24, i32 4) #0 79 %v26 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> zeroinitializer, <32 x i32> %v25) 80 %v27 = tail call <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32> zeroinitializer, <32 x i32> zeroinitializer) #0 81 %v28 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v26) #0 82 %v29 = tail call <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32> zeroinitializer, <32 x i32> %v28) #0 83 store <32 x i32> %v27, <32 x i32>* null, align 128 84 %v30 = add nsw i32 0, 128 85 %v31 = getelementptr inbounds i8, i8* null, i32 %v30 86 %v32 = bitcast i8* %v31 to <32 x i32>* 87 store <32 x i32> %v29, <32 x i32>* %v32, align 128 88 %v33 = icmp eq i32 0, 0 89 br i1 %v33, label %b21, label %b22 90} 91 92attributes #0 = { nounwind } 93attributes #1 = { nounwind readnone } 94attributes #2 = { nounwind "reciprocal-estimates"="none" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } 95attributes #3 = { nobuiltin nounwind } 96