1; RUN: llc -O3 -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s 2; XFAIL: * 3; 4; Generate hardware loop when loop 'latch' block is different 5; from the loop 'exiting' block. 6 7; CHECK: loop0(.LBB{{.}}_{{.}}, r{{[0-9]+}}) 8; CHECK: endloop0 9 10define void @test(i32* nocapture %pFL, i16 signext %nBS, i16* nocapture readonly %pHT) #0 { 11entry: 12 %0 = load i32, i32* %pFL, align 4 13 %1 = tail call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %0, i32 246) 14 %2 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %1, i32 -13) 15 %3 = tail call i32 @llvm.hexagon.A2.sat(i64 %2) 16 store i32 %3, i32* %pFL, align 4 17 %cmp16 = icmp sgt i16 %nBS, 0 18 br i1 %cmp16, label %for.body.lr.ph, label %for.end 19 20for.body.lr.ph: 21 %4 = sext i16 %nBS to i32 22 br label %for.body 23 24for.body: 25 %5 = phi i32 [ %3, %for.body.lr.ph ], [ %.pre, %for.body.for.body_crit_edge ] 26 %arrayidx3.phi = phi i32* [ %pFL, %for.body.lr.ph ], [ %arrayidx3.inc, %for.body.for.body_crit_edge ] 27 %arrayidx5.phi = phi i16* [ %pHT, %for.body.lr.ph ], [ %arrayidx5.inc, %for.body.for.body_crit_edge ] 28 %i.017.pmt = phi i32 [ 1, %for.body.lr.ph ], [ %phitmp, %for.body.for.body_crit_edge ] 29 %6 = load i16, i16* %arrayidx5.phi, align 2 30 %conv6 = sext i16 %6 to i32 31 %7 = tail call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %5, i32 %conv6) 32 %8 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %7, i32 -13) 33 %9 = tail call i32 @llvm.hexagon.A2.sat(i64 %8) 34 store i32 %9, i32* %arrayidx3.phi, align 4 35 %exitcond = icmp eq i32 %i.017.pmt, %4 36 %arrayidx3.inc = getelementptr i32, i32* %arrayidx3.phi, i32 1 37 br i1 %exitcond, label %for.end.loopexit, label %for.body.for.body_crit_edge 38 39for.body.for.body_crit_edge: 40 %arrayidx5.inc = getelementptr i16, i16* %arrayidx5.phi, i32 1 41 %.pre = load i32, i32* %arrayidx3.inc, align 4 42 %phitmp = add i32 %i.017.pmt, 1 43 br label %for.body 44 45for.end.loopexit: 46 br label %for.end 47 48for.end: 49 ret void 50} 51 52declare i32 @llvm.hexagon.A2.sat(i64) #1 53 54declare i64 @llvm.hexagon.S2.asl.r.p(i64, i32) #1 55 56declare i64 @llvm.hexagon.M2.dpmpyss.s0(i32, i32) #1 57 58attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "ssp-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } 59attributes #1 = { nounwind readnone } 60