1; RUN: llc -march=hexagon < %s 2; REQUIRES: asserts 3 4target triple = "hexagon" 5 6%s.0 = type { %s.1 } 7%s.1 = type { i32, i8* } 8 9@g0 = external unnamed_addr constant [6 x [2 x i32]], align 8 10@g1 = external constant %s.0, align 4 11 12; Function Attrs: nounwind 13define void @f0() #0 { 14b0: 15 br i1 undef, label %b1, label %b2 16 17b1: ; preds = %b0 18 unreachable 19 20b2: ; preds = %b0 21 br i1 undef, label %b3, label %b4 22 23b3: ; preds = %b2 24 switch i32 undef, label %b4 [ 25 i32 10, label %b5 26 ] 27 28b4: ; preds = %b3, %b2 29 unreachable 30 31b5: ; preds = %b3 32 br i1 undef, label %b7, label %b6 33 34b6: ; preds = %b5 35 switch i32 undef, label %b40 [ 36 i32 10, label %b38 37 i32 5, label %b8 38 ] 39 40b7: ; preds = %b5 41 unreachable 42 43b8: ; preds = %b6 44 br i1 undef, label %b9, label %b37 45 46b9: ; preds = %b8 47 br i1 undef, label %b10, label %b37 48 49b10: ; preds = %b9 50 br i1 undef, label %b12, label %b11 51 52b11: ; preds = %b10 53 unreachable 54 55b12: ; preds = %b10 56 br i1 undef, label %b13, label %b17 57 58b13: ; preds = %b12 59 br i1 undef, label %b14, label %b15 60 61b14: ; preds = %b13 62 unreachable 63 64b15: ; preds = %b13 65 br i1 undef, label %b16, label %b18 66 67b16: ; preds = %b15 68 unreachable 69 70b17: ; preds = %b12 71 unreachable 72 73b18: ; preds = %b15 74 br i1 undef, label %b19, label %b20 75 76b19: ; preds = %b18 77 br label %b21 78 79b20: ; preds = %b18 80 unreachable 81 82b21: ; preds = %b35, %b19 83 %v0 = phi i32 [ 0, %b19 ], [ %v43, %b35 ] 84 %v1 = phi i32 [ 0, %b19 ], [ %v44, %b35 ] 85 %v2 = phi i16 [ undef, %b19 ], [ %v42, %b35 ] 86 %v3 = trunc i32 %v1 to i10 87 %v4 = lshr i10 366, %v3 88 %v5 = and i10 %v4, 1 89 %v6 = icmp eq i10 %v5, 0 90 br i1 %v6, label %b35, label %b22 91 92b22: ; preds = %b21 93 %v7 = load i32, i32* undef, align 4, !tbaa !0 94 %v8 = load i32, i32* undef, align 4, !tbaa !4 95 %v9 = load i32, i32* undef, align 4, !tbaa !4 96 %v10 = icmp ne i32 %v8, 0 97 %v11 = and i1 %v10, undef 98 %v12 = and i1 undef, %v11 99 br i1 %v12, label %b23, label %b24 100 101b23: ; preds = %b22 102 %v13 = mul nsw i32 %v9, %v9 103 %v14 = sdiv i32 %v13, undef 104 %v15 = trunc i32 %v14 to i16 105 br label %b24 106 107b24: ; preds = %b23, %b22 108 %v16 = phi i16 [ %v15, %b23 ], [ 0, %b22 ] 109 %v17 = icmp ugt i16 %v16, undef 110 %v18 = zext i1 %v17 to i32 111 %v19 = add nsw i32 %v18, %v0 112 %v20 = load i8, i8* undef, align 4, !tbaa !6 113 %v21 = zext i8 %v20 to i32 114 %v22 = sub nsw i32 6, %v21 115 %v23 = add nsw i32 %v22, -1 116 br i1 false, label %b39, label %b25, !prof !19 117 118b25: ; preds = %b24 119 %v24 = getelementptr inbounds [6 x [2 x i32]], [6 x [2 x i32]]* @g0, i32 0, i32 %v21, i32 0 120 %v25 = load i32, i32* %v24, align 8, !tbaa !0 121 %v26 = icmp eq i32 undef, %v25 122 br i1 %v26, label %b26, label %b27 123 124b26: ; preds = %b25 125 br i1 undef, label %b32, label %b27 126 127b27: ; preds = %b26, %b25 128 %v27 = getelementptr inbounds [6 x [2 x i32]], [6 x [2 x i32]]* @g0, i32 0, i32 %v23, i32 0 129 %v28 = load i32, i32* %v27, align 8, !tbaa !0 130 %v29 = icmp eq i32 undef, %v28 131 br i1 %v29, label %b28, label %b29 132 133b28: ; preds = %b27 134 br i1 undef, label %b32, label %b29 135 136b29: ; preds = %b28, %b27 137 %v30 = load i32, i32* undef, align 4, !tbaa !4 138 %v31 = load i32, i32* undef, align 4, !tbaa !4 139 %v32 = icmp ne i32 %v30, 0 140 %v33 = and i1 %v32, undef 141 %v34 = and i1 undef, %v33 142 br i1 %v34, label %b30, label %b31 143 144b30: ; preds = %b29 145 %v35 = mul nsw i32 %v31, %v31 146 %v36 = sdiv i32 %v35, 0 147 %v37 = trunc i32 %v36 to i16 148 br label %b31 149 150b31: ; preds = %b30, %b29 151 %v38 = phi i16 [ %v37, %b30 ], [ 0, %b29 ] 152 br label %b32 153 154b32: ; preds = %b31, %b28, %b26 155 %v39 = phi i16 [ %v38, %b31 ], [ %v2, %b28 ], [ %v2, %b26 ] 156 br i1 undef, label %b33, label %b34 157 158b33: ; preds = %b32 159 call void (%s.0*, i32, ...) @f1(%s.0* nonnull @g1, i32 6, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 %v7) #0 160 br label %b34 161 162b34: ; preds = %b33, %b32 163 %v40 = icmp slt i32 %v19, 0 164 %v41 = and i1 %v40, undef 165 br i1 %v41, label %b35, label %b36 166 167b35: ; preds = %b34, %b21 168 %v42 = phi i16 [ %v2, %b21 ], [ %v39, %b34 ] 169 %v43 = phi i32 [ %v0, %b21 ], [ %v19, %b34 ] 170 %v44 = add nuw nsw i32 %v1, 1 171 br label %b21 172 173b36: ; preds = %b34 174 unreachable 175 176b37: ; preds = %b9, %b8 177 unreachable 178 179b38: ; preds = %b6 180 unreachable 181 182b39: ; preds = %b24 183 unreachable 184 185b40: ; preds = %b6 186 ret void 187} 188 189; Function Attrs: nounwind 190declare void @f1(%s.0*, i32, ...) #0 191 192attributes #0 = { nounwind "target-cpu"="hexagonv55" } 193 194!0 = !{!1, !1, i64 0} 195!1 = !{!"int", !2, i64 0} 196!2 = !{!"omnipotent char", !3, i64 0} 197!3 = !{!"Simple C/C++ TBAA"} 198!4 = !{!5, !5, i64 0} 199!5 = !{!"long", !2, i64 0} 200!6 = !{!7, !2, i64 136} 201!7 = !{!"x", !8, i64 0, !9, i64 8, !11, i64 52, !14, i64 88, !2, i64 116, !2, i64 117, !18, i64 118, !15, i64 128, !15, i64 132, !2, i64 136, !2, i64 140, !2, i64 180, !12, i64 220} 202!8 = !{!"", !2, i64 0, !2, i64 1, !2, i64 2, !2, i64 3, !2, i64 4, !2, i64 5} 203!9 = !{!"", !2, i64 0, !5, i64 4, !5, i64 8, !5, i64 12, !5, i64 16, !5, i64 20, !5, i64 24, !10, i64 28, !2, i64 32, !2, i64 33, !10, i64 36, !5, i64 40} 204!10 = !{!"any pointer", !2, i64 0} 205!11 = !{!"", !5, i64 0, !2, i64 4, !12, i64 20, !2, i64 32} 206!12 = !{!"", !13, i64 0, !13, i64 2, !13, i64 4, !13, i64 6, !13, i64 8, !13, i64 10} 207!13 = !{!"short", !2, i64 0} 208!14 = !{!"", !15, i64 0, !13, i64 2, !13, i64 4, !16, i64 8} 209!15 = !{!"", !2, i64 0} 210!16 = !{!"", !1, i64 0, !2, i64 4, !2, i64 5, !17, i64 8} 211!17 = !{!"", !2, i64 0, !5, i64 4, !5, i64 8} 212!18 = !{!"", !2, i64 0, !2, i64 1, !2, i64 2, !2, i64 3, !8, i64 4} 213!19 = !{!"branch_weights", i32 4, i32 64} 214