1; RUN: llc -march=hexagon < %s | FileCheck %s 2 3; Make sure we generate a hardware loop and pipeline the inner loop using 4; 4 packets, which is equivalent to the hand-coded version. 5 6; CHECK: loop0(.LBB0_[[LOOP:.]], 7; CHECK: .LBB0_[[LOOP]]: 8; CHECK: { 9; CHECK: } 10; CHECK: { 11; CHECK: } 12; CHECK: { 13; CHECK: } 14; CHECK: { 15; CHECK: } 16; CHECK: { 17; CHECK-NOT: } 18; CHECK: }{{[ \t]*}}:endloop0 19 20define void @f0(i8* noalias %a0, i32 %a1, i32 %a2, i32 %a3, i8* noalias nocapture %a4, i32 %a5, i32 %a6) #0 { 21b0: 22 %v0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 8388736) 23 %v1 = zext i32 %a3 to i64 24 %v2 = shl nuw i64 %v1, 32 25 %v3 = zext i32 %a1 to i64 26 %v4 = shl nuw nsw i64 %v3, 16 27 %v5 = or i64 %v4, %v2 28 %v6 = or i64 %v5, 281474976710658 29 tail call void asm sideeffect " l2fetch($0, $1)\0A", "r,r"(i8* %a0, i64 %v6) #2, !srcloc !0 30 %v7 = tail call i32 @llvm.hexagon.S2.ct0(i32 %a6) 31 %v8 = add i32 %v7, 1 32 %v9 = lshr i32 %a1, %v8 33 %v10 = mul i32 %a6, 2 34 %v11 = mul i32 %v10, %v9 35 %v12 = sub i32 %a1, %v11 36 %v13 = lshr i32 %v12, 1 37 %v14 = tail call <512 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %v13) 38 %v15 = icmp eq i32 %a2, 0 39 br i1 %v15, label %b11, label %b1 40 41b1: ; preds = %b0 42 %v16 = mul i32 %a3, 2 43 %v17 = icmp eq i32 %v9, 0 44 %v18 = icmp eq i32 %v11, %a1 45 %v19 = icmp ugt i32 %v12, %a6 46 %v20 = mul i32 %v9, 64 47 %v21 = getelementptr i8, i8* %a4, i32 %v20 48 %v22 = mul i32 %v9, 128 49 %v23 = add i32 %v22, %a3 50 %v24 = getelementptr i8, i8* %a0, i32 %v23 51 %v25 = getelementptr i8, i8* %a0, i32 %v22 52 br label %b2 53 54b2: ; preds = %b10, %b1 55 %v26 = phi i8* [ %v25, %b1 ], [ %v90, %b10 ] 56 %v27 = phi i8* [ %v24, %b1 ], [ %v89, %b10 ] 57 %v28 = phi i8* [ %v21, %b1 ], [ %v88, %b10 ] 58 %v29 = phi <16 x i32> [ undef, %b1 ], [ %v85, %b10 ] 59 %v30 = phi <16 x i32> [ undef, %b1 ], [ %v84, %b10 ] 60 %v31 = phi i8* [ %a0, %b1 ], [ %v86, %b10 ] 61 %v32 = phi i8* [ %a4, %b1 ], [ %v87, %b10 ] 62 %v33 = phi i32 [ 0, %b1 ], [ %v37, %b10 ] 63 %v34 = bitcast i8* %v26 to <16 x i32>* 64 %v35 = bitcast i8* %v27 to <16 x i32>* 65 %v36 = bitcast i8* %v28 to <16 x i32>* 66 %v37 = add nsw i32 %v33, 2 67 %v38 = icmp ult i32 %v37, %a2 68 br i1 %v38, label %b3, label %b4 69 70b3: ; preds = %b2 71 %v39 = getelementptr inbounds i8, i8* %v31, i32 %v16 72 tail call void asm sideeffect " l2fetch($0, $1)\0A", "r,r"(i8* %v39, i64 %v6) #2, !srcloc !1 73 br label %b4 74 75b4: ; preds = %b3, %b2 76 %v40 = bitcast i8* %v32 to <16 x i32>* 77 %v41 = bitcast i8* %v31 to <16 x i32>* 78 %v42 = getelementptr inbounds i8, i8* %v31, i32 %a3 79 %v43 = bitcast i8* %v42 to <16 x i32>* 80 br i1 %v17, label %b6, label %b5 81 82b5: ; preds = %b5, %b4 83 %v44 = phi <16 x i32>* [ %v54, %b5 ], [ %v43, %b4 ] 84 %v45 = phi <16 x i32>* [ %v52, %b5 ], [ %v41, %b4 ] 85 %v46 = phi <16 x i32>* [ %v61, %b5 ], [ %v40, %b4 ] 86 %v47 = phi i32 [ %v62, %b5 ], [ 0, %b4 ] 87 %v48 = getelementptr inbounds <16 x i32>, <16 x i32>* %v45, i32 1 88 %v49 = load <16 x i32>, <16 x i32>* %v45, align 64, !tbaa !2 89 %v50 = getelementptr inbounds <16 x i32>, <16 x i32>* %v44, i32 1 90 %v51 = load <16 x i32>, <16 x i32>* %v44, align 64, !tbaa !2 91 %v52 = getelementptr inbounds <16 x i32>, <16 x i32>* %v45, i32 2 92 %v53 = load <16 x i32>, <16 x i32>* %v48, align 64, !tbaa !2 93 %v54 = getelementptr inbounds <16 x i32>, <16 x i32>* %v44, i32 2 94 %v55 = load <16 x i32>, <16 x i32>* %v50, align 64, !tbaa !2 95 %v56 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v0, <16 x i32> %v49, i32 1077952576) 96 %v57 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v0, <16 x i32> %v53, i32 1077952576) 97 %v58 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v56, <16 x i32> %v51, i32 1077952576) 98 %v59 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v57, <16 x i32> %v55, i32 1077952576) 99 %v60 = tail call <16 x i32> @llvm.hexagon.V6.vpackob(<16 x i32> %v59, <16 x i32> %v58) 100 %v61 = getelementptr inbounds <16 x i32>, <16 x i32>* %v46, i32 1 101 store <16 x i32> %v60, <16 x i32>* %v46, align 64, !tbaa !2 102 %v62 = add nsw i32 %v47, 1 103 %v63 = icmp eq i32 %v62, %v9 104 br i1 %v63, label %b6, label %b5 105 106b6: ; preds = %b5, %b4 107 %v64 = phi <16 x i32> [ %v29, %b4 ], [ %v55, %b5 ] 108 %v65 = phi <16 x i32> [ %v30, %b4 ], [ %v53, %b5 ] 109 %v66 = phi <16 x i32>* [ %v43, %b4 ], [ %v35, %b5 ] 110 %v67 = phi <16 x i32>* [ %v41, %b4 ], [ %v34, %b5 ] 111 %v68 = phi <16 x i32>* [ %v40, %b4 ], [ %v36, %b5 ] 112 br i1 %v18, label %b10, label %b7 113 114b7: ; preds = %b6 115 %v69 = load <16 x i32>, <16 x i32>* %v67, align 64, !tbaa !2 116 %v70 = load <16 x i32>, <16 x i32>* %v66, align 64, !tbaa !2 117 br i1 %v19, label %b8, label %b9 118 119b8: ; preds = %b7 120 %v71 = getelementptr inbounds <16 x i32>, <16 x i32>* %v66, i32 1 121 %v72 = getelementptr inbounds <16 x i32>, <16 x i32>* %v67, i32 1 122 %v73 = load <16 x i32>, <16 x i32>* %v72, align 64, !tbaa !2 123 %v74 = load <16 x i32>, <16 x i32>* %v71, align 64, !tbaa !2 124 br label %b9 125 126b9: ; preds = %b8, %b7 127 %v75 = phi <16 x i32> [ %v73, %b8 ], [ %v65, %b7 ] 128 %v76 = phi <16 x i32> [ %v74, %b8 ], [ %v64, %b7 ] 129 %v77 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v0, <16 x i32> %v69, i32 1077952576) 130 %v78 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v0, <16 x i32> %v75, i32 1077952576) 131 %v79 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v77, <16 x i32> %v70, i32 1077952576) 132 %v80 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v78, <16 x i32> %v76, i32 1077952576) 133 %v81 = tail call <16 x i32> @llvm.hexagon.V6.vpackob(<16 x i32> %v80, <16 x i32> %v79) 134 %v82 = load <16 x i32>, <16 x i32>* %v68, align 64, !tbaa !2 135 %v83 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1> %v14, <16 x i32> %v81, <16 x i32> %v82) 136 store <16 x i32> %v83, <16 x i32>* %v68, align 64, !tbaa !2 137 br label %b10 138 139b10: ; preds = %b9, %b6 140 %v84 = phi <16 x i32> [ %v75, %b9 ], [ %v65, %b6 ] 141 %v85 = phi <16 x i32> [ %v76, %b9 ], [ %v64, %b6 ] 142 %v86 = getelementptr inbounds i8, i8* %v31, i32 %v16 143 %v87 = getelementptr inbounds i8, i8* %v32, i32 %a5 144 %v88 = getelementptr i8, i8* %v28, i32 %a5 145 %v89 = getelementptr i8, i8* %v27, i32 %v16 146 %v90 = getelementptr i8, i8* %v26, i32 %v16 147 br i1 %v38, label %b2, label %b11 148 149b11: ; preds = %b10, %b0 150 ret void 151} 152 153; Function Attrs: nounwind readnone 154declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1 155 156; Function Attrs: nounwind readnone 157declare i32 @llvm.hexagon.S2.ct0(i32) #1 158 159; Function Attrs: nounwind readnone 160declare <512 x i1> @llvm.hexagon.V6.pred.scalar2(i32) #1 161 162; Function Attrs: nounwind readnone 163declare <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32>, <16 x i32>, i32) #1 164 165; Function Attrs: nounwind readnone 166declare <16 x i32> @llvm.hexagon.V6.vpackob(<16 x i32>, <16 x i32>) #1 167 168; Function Attrs: nounwind readnone 169declare <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1>, <16 x i32>, <16 x i32>) #1 170 171attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 172attributes #1 = { nounwind readnone } 173attributes #2 = { nounwind } 174 175!0 = !{i32 -2146401371} 176!1 = !{i32 -2146401153} 177!2 = !{!3, !3, i64 0} 178!3 = !{!"omnipotent char", !4, i64 0} 179!4 = !{!"Simple C/C++ TBAA"} 180