1; RUN: llc -fast-isel-sink-local-values -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ 2; RUN: -fast-isel-abort=3 -verify-machineinstrs < %s | \ 3; RUN: FileCheck %s -check-prefixes=ALL,32R1 4; RUN: llc -fast-isel-sink-local-values -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ 5; RUN: -fast-isel-abort=3 -verify-machineinstrs < %s | \ 6; RUN: FileCheck %s -check-prefixes=ALL,32R2 7 8declare void @xb(i8) 9 10define void @cxb() { 11 ; ALL-LABEL: cxb: 12 13 ; ALL: addiu $[[T0:[0-9]+]], $zero, 10 14 15 ; 32R1: sll $[[T1:[0-9]+]], $[[T0]], 24 16 ; 32R1: sra $4, $[[T1]], 24 17 18 ; 32R2: seb $4, $[[T0]] 19 call void @xb(i8 10) 20 ret void 21} 22 23declare void @xh(i16) 24 25define void @cxh() { 26 ; ALL-LABEL: cxh: 27 28 ; ALL: addiu $[[T0:[0-9]+]], $zero, 10 29 30 ; 32R1: sll $[[T1:[0-9]+]], $[[T0]], 16 31 ; 32R1: sra $4, $[[T1]], 16 32 33 ; 32R2: seh $4, $[[T0]] 34 call void @xh(i16 10) 35 ret void 36} 37 38declare void @xi(i32) 39 40define void @cxi() { 41 ; ALL-LABEL: cxi: 42 43 ; ALL-DAG: addiu $4, $zero, 10 44 ; ALL-DAG: lw $25, %got(xi)(${{[0-9]+}}) 45 ; ALL: jalr $25 46 call void @xi(i32 10) 47 ret void 48} 49 50declare void @xbb(i8, i8) 51 52define void @cxbb() { 53 ; ALL-LABEL: cxbb: 54 55 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 76 56 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 101 57 58 ; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T0]], 24 59 ; 32R1-DAG: sra $[[T3:[0-9]+]], $[[T2]], 24 60 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 24 61 ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 24 62 63 ; 32R2-DAG: seb $4, $[[T0]] 64 ; 32R2-DAG: seb $5, $[[T1]] 65 call void @xbb(i8 76, i8 101) 66 ret void 67} 68 69declare void @xhh(i16, i16) 70 71define void @cxhh() { 72 ; ALL-LABEL: cxhh: 73 74 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 76 75 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 101 76 77 ; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T0]], 16 78 ; 32R1-DAG: sra $[[T3:[0-9]+]], $[[T2]], 16 79 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 16 80 ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 16 81 82 ; 32R2-DAG: seh $4, $[[T0]] 83 ; 32R2-DAG: seh $5, $[[T1]] 84 call void @xhh(i16 76, i16 101) 85 ret void 86} 87 88declare void @xii(i32, i32) 89 90define void @cxii() { 91 ; ALL-LABEL: cxii: 92 93 ; ALL-DAG: addiu $4, $zero, 746 94 ; ALL-DAG: addiu $5, $zero, 892 95 ; ALL-DAG: lw $25, %got(xii)(${{[0-9]+}}) 96 ; ALL: jalr $25 97 call void @xii(i32 746, i32 892) 98 ret void 99} 100 101declare void @xccc(i8, i8, i8) 102 103define void @cxccc() { 104 ; ALL-LABEL: cxccc: 105 106 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88 107 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44 108 ; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11 109 110 ; 32R1-DAG: sll $[[T3:[0-9]+]], $[[T0]], 24 111 ; 32R1-DAG: sra $4, $[[T3]], 24 112 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 24 113 ; 32R1-DAG: sra $5, $[[T4]], 24 114 ; 32R1-DAG: sll $[[T5:[0-9]+]], $[[T2]], 24 115 ; 32R1-DAG: sra $6, $[[T5]], 24 116 117 ; 32R2-DAG: seb $4, $[[T0]] 118 ; 32R2-DAG: seb $5, $[[T1]] 119 ; 32R2-DAG: seb $6, $[[T2]] 120 call void @xccc(i8 88, i8 44, i8 11) 121 ret void 122} 123 124declare void @xhhh(i16, i16, i16) 125 126define void @cxhhh() { 127 ; ALL-LABEL: cxhhh: 128 129 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88 130 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44 131 ; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11 132 133 ; 32R1-DAG: sll $[[T3:[0-9]+]], $[[T0]], 16 134 ; 32R1-DAG: sra $4, $[[T3]], 16 135 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 16 136 ; 32R1-DAG: sra $5, $[[T4]], 16 137 ; 32R1-DAG: sll $[[T5:[0-9]+]], $[[T2]], 16 138 ; 32R1-DAG: sra $6, $[[T5]], 16 139 140 ; 32R2-DAG: seh $4, $[[T0]] 141 ; 32R2-DAG: seh $5, $[[T1]] 142 ; 32R2-DAG: seh $6, $[[T2]] 143 call void @xhhh(i16 88, i16 44, i16 11) 144 ret void 145} 146 147declare void @xiii(i32, i32, i32) 148 149define void @cxiii() { 150 ; ALL-LABEL: cxiii: 151 152 ; ALL-DAG: addiu $4, $zero, 88 153 ; ALL-DAG: addiu $5, $zero, 44 154 ; ALL-DAG: addiu $6, $zero, 11 155 ; ALL-DAG: lw $25, %got(xiii)(${{[0-9]+}}) 156 ; ALL: jalr $25 157 call void @xiii(i32 88, i32 44, i32 11) 158 ret void 159} 160 161declare void @xcccc(i8, i8, i8, i8) 162 163define void @cxcccc() { 164 ; ALL-LABEL: cxcccc: 165 166 ; ALL: addiu $[[R:[0-9]+]], $zero, 88 167 ; 32R1: sll $[[R:[0-9]+]], $[[R]], 24 168 ; 32R1: sra $4, $[[R]], 24 169 ; 32R2: seb $4, $[[R]] 170 ; ALL: addiu $[[R:[0-9]+]], $zero, 44 171 ; 32R1: sll $[[R:[0-9]+]], $[[R]], 24 172 ; 32R1: sra $5, $[[R]], 24 173 ; 32R2: seb $5, $[[R]] 174 ; ALL: addiu $[[R:[0-9]+]], $zero, 11 175 ; 32R1: sll $[[R:[0-9]+]], $[[R]], 24 176 ; 32R1: sra $6, $[[R]], 24 177 ; 32R2: seb $6, $[[R]] 178 ; ALL: addiu $[[R:[0-9]+]], $zero, 33 179 ; 32R1: sll $[[R:[0-9]+]], $[[R]], 24 180 ; 32R1: sra $7, $[[R]], 24 181 ; 32R2: seb $7, $[[R]] 182 183 ; ALL: lw $25, %got(xcccc)($2) 184 ; ALL: jalr $25 185 ; ALL: jr $ra 186 call void @xcccc(i8 88, i8 44, i8 11, i8 33) 187 ret void 188} 189 190declare void @xhhhh(i16, i16, i16, i16) 191 192define void @cxhhhh() { 193 ; ALL-LABEL: cxhhhh: 194 195 ; ALL: addiu $[[R:[0-9]+]], $zero, 88 196 ; 32R1: sll $[[R]], $[[R]], 16 197 ; 32R1: sra $4, $[[R]], 16 198 ; 32R2: seh $4, $[[R]] 199 ; ALL: addiu $[[R:[0-9]+]], $zero, 44 200 ; 32R1: sll $[[R]], $[[R]], 16 201 ; 32R1: sra $5, $[[R]], 16 202 ; 32R2: seh $5, $[[R]] 203 ; ALL: addiu $[[R:[0-9]+]], $zero, 11 204 ; 32R1: sll $[[R]], $[[R]], 16 205 ; 32R1: sra $6, $[[R]], 16 206 ; 32R2: seh $6, $[[R]] 207 ; ALL: addiu $[[R:[0-9]+]], $zero, 33 208 ; 32R1: sll $[[R]], $[[R]], 16 209 ; 32R1: sra $7, $[[R]], 16 210 ; 32R2: seh $7, $[[R]] 211 212 ; ALL: lw $25, %got(xhhhh)($2) 213 ; ALL: jalr $25 214 ; ALL: jr $ra 215 216 call void @xhhhh(i16 88, i16 44, i16 11, i16 33) 217 ret void 218} 219 220declare void @xiiii(i32, i32, i32, i32) 221 222define void @cxiiii() { 223 ; ALL-LABEL: cxiiii: 224 225 ; ALL-DAG: addiu $4, $zero, 167 226 ; ALL-DAG: addiu $5, $zero, 320 227 ; ALL-DAG: addiu $6, $zero, 97 228 ; ALL-DAG: addiu $7, $zero, 14 229 ; ALL-DAG: lw $25, %got(xiiii)(${{[0-9]+}}) 230 ; ALL: jalr $25 231 call void @xiiii(i32 167, i32 320, i32 97, i32 14) 232 ret void 233} 234 235@c1 = global i8 -45, align 1 236@uc1 = global i8 27, align 1 237@s1 = global i16 -1789, align 2 238@us1 = global i16 1256, align 2 239 240define void @cxiiiiconv() { 241 ; ALL-LABEL: cxiiiiconv: 242 243 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 244 ; ALL-DAG: lw $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]]) 245 ; ALL-DAG: lbu $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]]) 246 ; 32R1-DAG: sll $[[REG_C1_1:[0-9]+]], $[[REG_C1]], 24 247 ; 32R1-DAG: sra $4, $[[REG_C1_1]], 24 248 ; 32R2-DAG: seb $4, $[[REG_C1]] 249 ; FIXME: andi is superfulous 250 ; ALL-DAG: lw $[[REG_UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) 251 ; ALL-DAG: lbu $[[REG_UC1:[0-9]+]], 0($[[REG_UC1_ADDR]]) 252 ; ALL-DAG: andi $5, $[[REG_UC1]], 255 253 ; ALL-DAG: lw $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]]) 254 ; ALL-DAG: lhu $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]]) 255 ; 32R1-DAG: sll $[[REG_S1_1:[0-9]+]], $[[REG_S1]], 16 256 ; 32R1-DAG: sra $6, $[[REG_S1_1]], 16 257 ; 32R2-DAG: seh $6, $[[REG_S1]] 258 ; FIXME andi is superfulous 259 ; ALL-DAG: lw $[[REG_US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) 260 ; ALL-DAG: lhu $[[REG_US1:[0-9]+]], 0($[[REG_US1_ADDR]]) 261 ; ALL-DAG: andi $7, $[[REG_US1]], 65535 262 ; ALL: jalr $25 263 %1 = load i8, i8* @c1, align 1 264 %conv = sext i8 %1 to i32 265 %2 = load i8, i8* @uc1, align 1 266 %conv1 = zext i8 %2 to i32 267 %3 = load i16, i16* @s1, align 2 268 %conv2 = sext i16 %3 to i32 269 %4 = load i16, i16* @us1, align 2 270 %conv3 = zext i16 %4 to i32 271 call void @xiiii(i32 %conv, i32 %conv1, i32 %conv2, i32 %conv3) 272 ret void 273} 274 275declare void @xf(float) 276 277define void @cxf() { 278 ; ALL-LABEL: cxf: 279 280 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 281 ; ALL: lui $[[REG_FPCONST_1:[0-9]+]], 17886 282 ; ALL: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 17067 283 ; ALL: mtc1 $[[REG_FPCONST]], $f12 284 ; ALL: lw $25, %got(xf)($[[REG_GP]]) 285 ; ALL: jalr $25 286 call void @xf(float 0x40BBC85560000000) 287 ret void 288} 289 290declare void @xff(float, float) 291 292define void @cxff() { 293 ; ALL-LABEL: cxff: 294 295 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 296 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16314 297 ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 21349 298 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12 299 ; ALL-DAG: lui $[[REG_FPCONST_2:[0-9]+]], 16593 300 ; ALL-DAG: ori $[[REG_FPCONST_3:[0-9]+]], $[[REG_FPCONST_2]], 24642 301 ; ALL-DAG: mtc1 $[[REG_FPCONST_3]], $f14 302 ; ALL-DAG: lw $25, %got(xff)($[[REG_GP]]) 303 ; ALL: jalr $25 304 call void @xff(float 0x3FF74A6CA0000000, float 0x401A2C0840000000) 305 ret void 306} 307 308declare void @xfi(float, i32) 309 310define void @cxfi() { 311 ; ALL-LABEL: cxfi: 312 313 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 314 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16540 315 ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 33554 316 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12 317 ; ALL-DAG: addiu $5, $zero, 102 318 ; ALL-DAG: lw $25, %got(xfi)($[[REG_GP]]) 319 ; ALL: jalr $25 320 call void @xfi(float 0x4013906240000000, i32 102) 321 ret void 322} 323 324declare void @xfii(float, i32, i32) 325 326define void @cxfii() { 327 ; ALL-LABEL: cxfii: 328 329 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 330 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17142 331 ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 16240 332 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12 333 ; ALL-DAG: addiu $5, $zero, 9993 334 ; ALL-DAG: addiu $6, $zero, 10922 335 ; ALL-DAG: lw $25, %got(xfii)($[[REG_GP]]) 336 ; ALL: jalr $25 337 call void @xfii(float 0x405EC7EE00000000, i32 9993, i32 10922) 338 ret void 339} 340 341declare void @xfiii(float, i32, i32, i32) 342 343define void @cxfiii() { 344 ; ALL-LABEL: cxfiii: 345 346 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 347 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17120 348 ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 14681 349 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12 350 ; ALL-DAG: addiu $5, $zero, 3948 351 ; ALL-DAG: lui $[[REG_I_1:[0-9]+]], 1 352 ; ALL-DAG: ori $6, $[[REG_I_1]], 23475 353 ; ALL-DAG: lui $[[REG_I_2:[0-9]+]], 1 354 ; ALL-DAG: ori $7, $[[REG_I_2]], 45686 355 ; ALL-DAG: lw $25, %got(xfiii)($[[REG_GP]]) 356 ; ALL: jalr $25 357 call void @xfiii(float 0x405C072B20000000, i32 3948, i32 89011, i32 111222) 358 ret void 359} 360 361declare void @xd(double) 362 363define void @cxd() { 364 ; ALL-LABEL: cxd: 365 366 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 367 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16514 368 ; ALL-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 48037 369 ; ALL-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 58195 370 ; ALL-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 63439 371 ; ALL-DAG: mtc1 $[[REG_FPCONST_4]], $f12 372 ; 32R1-DAG: mtc1 $[[REG_FPCONST_2]], $f13 373 ; 32R2-DAG: mthc1 $[[REG_FPCONST_2]], $f12 374 ; ALL-DAG: lw $25, %got(xd)($[[REG_GP]]) 375 ; ALL: jalr $25 376 call void @xd(double 5.994560e+02) 377 ret void 378} 379 380declare void @xdd(double, double) 381 382define void @cxdd() { 383 ; ALL-LABEL: cxdd: 384 385 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 386 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16531 387 ; ALL-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 19435 388 ; ALL-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 34078 389 ; ALL-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 47186 390 ; ALL-DAG: mtc1 $[[REG_FPCONST_4]], $f12 391 ; 32R1-DAG: mtc1 $[[REG_FPCONST_2]], $f13 392 ; 32R2-DAG: mthc1 $[[REG_FPCONST_2]], $f12 393 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16629 394 ; ALL-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 45873 395 ; ALL-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 63438 396 ; ALL-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 55575 397 ; ALL-DAG: mtc1 $[[REG_FPCONST_4]], $f14 398 ; 32R1-DAG: mtc1 $[[REG_FPCONST_2]], $f15 399 ; 32R2-DAG: mthc1 $[[REG_FPCONST_2]], $f14 400 ; ALL-DAG: lw $25, %got(xdd)($[[REG_GP]]) 401 ; ALL: jalr $25 402 call void @xdd(double 1.234980e+03, double 0x40F5B331F7CED917) 403 ret void 404} 405 406declare void @xif(i32, float) 407 408define void @cxif() { 409 ; ALL-LABEL: cxif: 410 411 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 412 ; ALL-DAG: addiu $4, $zero, 345 413 ; ALL-DAG: lui $[[REGF_1:[0-9]+]], 17374 414 ; ALL-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 29393 415 ; ALL-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]] 416 ; ALL-DAG: mfc1 $5, $f[[REGF_3]] 417 ; ALL-DAG: lw $25, %got(xif)($[[REG_GP]]) 418 ; ALL: jalr $25 419 call void @xif(i32 345, float 0x407BCE5A20000000) 420 ret void 421} 422 423declare void @xiff(i32, float, float) 424 425define void @cxiff() { 426 ; ALL-LABEL: cxiff: 427 428 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 429 ; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 17526 430 ; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 55706 431 ; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]] 432 ; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 16543 433 ; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 65326 434 ; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]] 435 ; ALL-DAG: addiu $4, $zero, 12239 436 ; ALL-DAG: mfc1 $5, $f[[REGF0_3]] 437 ; ALL-DAG: mfc1 $6, $f[[REGF1_3]] 438 ; ALL-DAG: lw $25, %got(xiff)($[[REG_GP]]) 439 ; ALL: jalr $25 440 call void @xiff(i32 12239, float 0x408EDB3340000000, float 0x4013FFE5C0000000) 441 ret void 442} 443 444declare void @xifi(i32, float, i32) 445 446define void @cxifi() { 447 ; ALL-LABEL: cxifi: 448 449 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 450 ; ALL-DAG: addiu $4, $zero, 887 451 ; ALL-DAG: lui $[[REGF_1:[0-9]+]], 16659 452 ; ALL-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 48759 453 ; ALL-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]] 454 ; ALL-DAG: mfc1 $5, $f[[REGF_3]] 455 ; ALL-DAG: addiu $6, $zero, 888 456 ; ALL-DAG: lw $25, %got(xifi)($[[REG_GP]]) 457 ; ALL: jalr $25 458 call void @xifi(i32 887, float 0x402277CEE0000000, i32 888) 459 ret void 460} 461 462declare void @xifif(i32, float, i32, float) 463 464define void @cxifif() { 465 ; ALL-LABEL: cxifif: 466 467 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 468 ; ALL-DAG: lui $[[REGI:[0-9]+]], 1 469 ; ALL-DAG: ori $4, $[[REGI]], 2238 470 ; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 17527 471 ; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 2015 472 ; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]] 473 ; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 17802 474 ; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 58470 475 ; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]] 476 ; ALL-DAG: mfc1 $5, $f[[REGF0_3]] 477 ; ALL-DAG: addiu $6, $zero, 9991 478 ; ALL-DAG: mfc1 $7, $f[[REGF1_3]] 479 ; ALL-DAG: lw $25, %got(xifif)($[[REG_GP]]) 480 ; ALL: jalr $25 481 call void @xifif(i32 67774, float 0x408EE0FBE0000000, 482 i32 9991, float 0x40B15C8CC0000000) 483 ret void 484} 485 486declare void @xiffi(i32, float, float, i32) 487 488define void @cxiffi() { 489 ; ALL-LABEL: cxiffi: 490 491 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 492 ; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 16307 493 ; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 13107 494 ; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]] 495 ; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 17529 496 ; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 39322 497 ; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]] 498 ; ALL-DAG: addiu $4, $zero, 45 499 ; ALL-DAG: mfc1 $5, $f[[REGF0_3]] 500 ; ALL-DAG: mfc1 $6, $f[[REGF1_3]] 501 ; ALL-DAG: addiu $7, $zero, 234 502 ; ALL-DAG: lw $25, %got(xiffi)($[[REG_GP]]) 503 ; ALL: jalr $25 504 call void @xiffi(i32 45, float 0x3FF6666660000000, 505 float 0x408F333340000000, i32 234) 506 ret void 507} 508 509declare void @xifii(i32, float, i32, i32) 510 511define void @cxifii() { 512 ; ALL-LABEL: cxifii: 513 514 ; ALL-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 515 ; ALL-DAG: addiu $4, $zero, 12239 516 ; ALL-DAG: lui $[[REGF_1:[0-9]+]], 17526 517 ; ALL-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 55706 518 ; ALL-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]] 519 ; ALL-DAG: mfc1 $5, $f[[REGF_3]] 520 ; ALL-DAG: lui $[[REGI2:[0-9]+]], 15 521 ; ALL-DAG: ori $6, $[[REGI2]], 15837 522 ; ALL-DAG: addiu $7, $zero, 1234 523 ; ALL-DAG: lw $25, %got(xifii)($[[REG_GP]]) 524 ; ALL: jalr $25 525 call void @xifii(i32 12239, float 0x408EDB3340000000, i32 998877, i32 1234) 526 ret void 527} 528