1; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s 2 3; Currently, the following IR assembly generates a KILL instruction between 4; the bitwise-and instruction and the return instruction. We verify that the 5; delay slot filler ignores such KILL instructions by filling the slot of the 6; return instruction properly. 7define signext i32 @f1(i32 signext %a, i32 signext %b) { 8entry: 9 ; CHECK: jr $ra 10 ; CHECK-NEXT: and $2, $4, $5 11 12 %r = and i32 %a, %b 13 ret i32 %r 14} 15