1; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32 2; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64 3; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM 4; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64 5; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6 6 7; TODO: Test for cvt_w_d is missing, could not generate instruction 8 9define double @cvt_d_s(float %a) { 10; MIPS32: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D32_S 11; MIPS32FP64: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_S 12; MM: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D32_S_MM 13; MMFP64: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_S_MM 14; MMR6: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_S_MM 15 %1 = fpext float %a to double 16 ret double %1 17} 18 19define double @cvt_d_w(i32 %a) { 20; MIPS32: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D32_W 21; MIPS32FP64: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_W 22; MM: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D32_W_MM 23; MMFP64: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_W_MM 24; MMR6: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_W_MM 25 %1 = sitofp i32 %a to double 26 ret double %1 27} 28 29define float @cvt_s_d(double %a) { 30; MIPS32: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D32 31; MIPS32FP64: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D64 32; MM: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D32_MM 33; MMFP64: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D64_MM 34; MMR6: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D64_MM 35 %1 = fptrunc double %a to float 36 ret float %1 37} 38