1; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ 2; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \ 3; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s 4 5define void @qpFmadd(fp128* nocapture readonly %a, fp128* nocapture %b, 6 fp128* nocapture readonly %c, fp128* nocapture %res) { 7entry: 8 %0 = load fp128, fp128* %a, align 16 9 %1 = load fp128, fp128* %b, align 16 10 %2 = load fp128, fp128* %c, align 16 11 %madd = tail call fp128 @llvm.fmuladd.f128(fp128 %0, fp128 %1, fp128 %2) 12 store fp128 %madd, fp128* %res, align 16 13 ret void 14; CHECK-LABEL: qpFmadd 15; CHECK-NOT: bl fmal 16; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3) 17; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4) 18; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5) 19; CHECK: xsmaddqp v[[REG5]], v[[REG3]], v[[REG4]] 20; CHECK-NEXT: stxv v[[REG5]], 0(r6) 21; CHECK-NEXT: blr 22} 23declare fp128 @llvm.fmuladd.f128(fp128, fp128, fp128) 24 25; Function Attrs: norecurse nounwind 26define void @qpFmadd_02(fp128* nocapture readonly %a, 27 fp128* nocapture readonly %b, 28 fp128* nocapture readonly %c, fp128* nocapture %res) { 29entry: 30 %0 = load fp128, fp128* %a, align 16 31 %1 = load fp128, fp128* %b, align 16 32 %2 = load fp128, fp128* %c, align 16 33 %mul = fmul contract fp128 %1, %2 34 %add = fadd contract fp128 %0, %mul 35 store fp128 %add, fp128* %res, align 16 36 ret void 37; CHECK-LABEL: qpFmadd_02 38; CHECK-NOT: bl __multf3 39; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3) 40; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4) 41; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5) 42; CHECK: xsmaddqp v[[REG3]], v[[REG4]], v[[REG5]] 43; CHECK-NEXT: stxv v[[REG3]], 0(r6) 44; CHECK-NEXT: blr 45} 46 47; Function Attrs: norecurse nounwind 48define void @qpFmadd_03(fp128* nocapture readonly %a, 49 fp128* nocapture readonly %b, 50 fp128* nocapture readonly %c, fp128* nocapture %res) { 51entry: 52 %0 = load fp128, fp128* %a, align 16 53 %1 = load fp128, fp128* %b, align 16 54 %mul = fmul contract fp128 %0, %1 55 %2 = load fp128, fp128* %c, align 16 56 %add = fadd contract fp128 %mul, %2 57 store fp128 %add, fp128* %res, align 16 58 ret void 59; CHECK-LABEL: qpFmadd_03 60; CHECK-NOT: bl __multf3 61; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3) 62; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4) 63; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5) 64; CHECK: xsmaddqp v[[REG5]], v[[REG3]], v[[REG4]] 65; CHECK-NEXT: stxv v[[REG5]], 0(r6) 66; CHECK-NEXT: blr 67} 68 69; Function Attrs: norecurse nounwind 70define void @qpFnmadd(fp128* nocapture readonly %a, 71 fp128* nocapture readonly %b, 72 fp128* nocapture readonly %c, fp128* nocapture %res) { 73entry: 74 %0 = load fp128, fp128* %a, align 16 75 %1 = load fp128, fp128* %b, align 16 76 %2 = load fp128, fp128* %c, align 16 77 %mul = fmul contract fp128 %1, %2 78 %add = fadd contract fp128 %0, %mul 79 %sub = fsub fp128 0xL00000000000000008000000000000000, %add 80 store fp128 %sub, fp128* %res, align 16 81 ret void 82; CHECK-LABEL: qpFnmadd 83; CHECK-NOT: bl __multf3 84; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3) 85; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4) 86; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5) 87; CHECK: xsnmaddqp v[[REG3]], v[[REG4]], v[[REG5]] 88; CHECK-NEXT: stxv v[[REG3]], 0(r6) 89; CHECK-NEXT: blr 90} 91 92; Function Attrs: norecurse nounwind 93define void @qpFnmadd_02(fp128* nocapture readonly %a, 94 fp128* nocapture readonly %b, 95 fp128* nocapture readonly %c, fp128* nocapture %res) { 96entry: 97 %0 = load fp128, fp128* %a, align 16 98 %1 = load fp128, fp128* %b, align 16 99 %mul = fmul contract fp128 %0, %1 100 %2 = load fp128, fp128* %c, align 16 101 %add = fadd contract fp128 %mul, %2 102 %sub = fsub fp128 0xL00000000000000008000000000000000, %add 103 store fp128 %sub, fp128* %res, align 16 104 ret void 105; CHECK-LABEL: qpFnmadd_02 106; CHECK-NOT: bl __multf3 107; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3) 108; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4) 109; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5) 110; CHECK: xsnmaddqp v[[REG5]], v[[REG3]], v[[REG4]] 111; CHECK-NEXT: stxv v[[REG5]], 0(r6) 112; CHECK-NEXT: blr 113} 114 115; Function Attrs: norecurse nounwind 116define void @qpFmsub(fp128* nocapture readonly %a, 117 fp128* nocapture readonly %b, 118 fp128* nocapture readonly %c, fp128* nocapture %res) { 119entry: 120 %0 = load fp128, fp128* %a, align 16 121 %1 = load fp128, fp128* %b, align 16 122 %2 = load fp128, fp128* %c, align 16 123 %mul = fmul contract fp128 %1, %2 124 %sub = fsub contract fp128 %0, %mul 125 store fp128 %sub, fp128* %res, align 16 126 ret void 127; CHECK-LABEL: qpFmsub 128; CHECK-NOT: bl __multf3 129; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3) 130; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4) 131; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5) 132; CHECK: xsnmsubqp v[[REG3]], v[[REG5]], v[[REG4]] 133; CHECK-NEXT: stxv v[[REG3]], 0(r6) 134; CHECK-NEXT: blr 135} 136 137; Function Attrs: norecurse nounwind 138define void @qpFmsub_02(fp128* nocapture readonly %a, 139 fp128* nocapture readonly %b, 140 fp128* nocapture readonly %c, fp128* nocapture %res) { 141entry: 142 %0 = load fp128, fp128* %a, align 16 143 %1 = load fp128, fp128* %b, align 16 144 %mul = fmul contract fp128 %0, %1 145 %2 = load fp128, fp128* %c, align 16 146 %sub = fsub contract fp128 %mul, %2 147 store fp128 %sub, fp128* %res, align 16 148 ret void 149; CHECK-LABEL: qpFmsub_02 150; CHECK-NOT: bl __multf3 151; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3) 152; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4) 153; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5) 154; CHECK: xsmsubqp v[[REG5]], v[[REG3]], v[[REG4]] 155; CHECK-NEXT: stxv v[[REG5]], 0(r6) 156; CHECK-NEXT: blr 157} 158 159; Function Attrs: norecurse nounwind 160define void @qpFnmsub(fp128* nocapture readonly %a, 161 fp128* nocapture readonly %b, 162 fp128* nocapture readonly %c, fp128* nocapture %res) { 163entry: 164 %0 = load fp128, fp128* %a, align 16 165 %1 = load fp128, fp128* %b, align 16 166 %2 = load fp128, fp128* %c, align 16 167 %mul = fmul contract fp128 %1, %2 168 %sub = fsub contract fp128 %0, %mul 169 %sub1 = fsub fp128 0xL00000000000000008000000000000000, %sub 170 store fp128 %sub1, fp128* %res, align 16 171 ret void 172; CHECK-LABEL: qpFnmsub 173; CHECK-NOT: bl __multf3 174; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3) 175; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4) 176; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5) 177; CHECK: xsnegqp v[[REG4]], v[[REG4]] 178; CHECK: xsnmaddqp v[[REG3]], v[[REG4]], v[[REG5]] 179; CHECK-NEXT: stxv v[[REG3]], 0(r6) 180; CHECK-NEXT: blr 181} 182 183; Function Attrs: norecurse nounwind 184define void @qpFnmsub_02(fp128* nocapture readonly %a, 185 fp128* nocapture readonly %b, 186 fp128* nocapture readonly %c, fp128* nocapture %res) { 187entry: 188 %0 = load fp128, fp128* %a, align 16 189 %1 = load fp128, fp128* %b, align 16 190 %mul = fmul contract fp128 %0, %1 191 %2 = load fp128, fp128* %c, align 16 192 %sub = fsub contract fp128 %mul, %2 193 %sub1 = fsub fp128 0xL00000000000000008000000000000000, %sub 194 store fp128 %sub1, fp128* %res, align 16 195 ret void 196; CHECK-LABEL: qpFnmsub_02 197; CHECK-NOT: bl __multf3 198; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3) 199; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4) 200; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5) 201; CHECK: xsnmsubqp v[[REG5]], v[[REG3]], v[[REG4]] 202; CHECK-NEXT: stxv v[[REG5]], 0(r6) 203; CHECK-NEXT: blr 204} 205