1; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -ppc-vsr-nums-as-vr \ 2; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s 3; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu -ppc-vsr-nums-as-vr \ 4; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=CHECK-BE 5 6@Globi = external global i32, align 4 7@Globf = external global float, align 4 8 9define <2 x i64> @test1(i64 %a, i64 %b) { 10; CHECK-LABEL: test1: 11; CHECK: # %bb.0: # %entry 12; CHECK-NEXT: mtvsrdd v2, r4, r3 13; CHECK-NEXT: blr 14 15; CHECK-BE-LABEL: test1: 16; CHECK-BE: # %bb.0: # %entry 17; CHECK-BE-NEXT: mtvsrdd v2, r3, r4 18; CHECK-BE-NEXT: blr 19entry: 20; The FIXME below is due to the lowering for BUILD_VECTOR needing a re-vamp 21; which will happen in a subsequent patch. 22 %vecins = insertelement <2 x i64> undef, i64 %a, i32 0 23 %vecins1 = insertelement <2 x i64> %vecins, i64 %b, i32 1 24 ret <2 x i64> %vecins1 25} 26 27define i64 @test2(<2 x i64> %a) { 28; CHECK-LABEL: test2: 29; CHECK: # %bb.0: # %entry 30; CHECK-NEXT: mfvsrld r3, v2 31; CHECK-NEXT: blr 32 33; CHECK-BE-LABEL: test2: 34; CHECK-BE: # %bb.0: # %entry 35; CHECK-BE-NEXT: mfvsrd r3, v2 36; CHECK-BE-NEXT: blr 37entry: 38 %0 = extractelement <2 x i64> %a, i32 0 39 ret i64 %0 40} 41 42define i64 @test3(<2 x i64> %a) { 43; CHECK-LABEL: test3: 44; CHECK: # %bb.0: # %entry 45; CHECK-NEXT: mfvsrd r3, v2 46; CHECK-NEXT: blr 47 48; CHECK-BE-LABEL: test3: 49; CHECK-BE: # %bb.0: # %entry 50; CHECK-BE-NEXT: mfvsrld r3, v2 51; CHECK-BE-NEXT: blr 52entry: 53 %0 = extractelement <2 x i64> %a, i32 1 54 ret i64 %0 55} 56 57define <4 x i32> @test4(i32* nocapture readonly %in) { 58; CHECK-LABEL: test4: 59; CHECK: # %bb.0: # %entry 60; CHECK-NEXT: lfiwzx f0, 0, r3 61; CHECK-NEXT: xxpermdi vs0, f0, f0, 2 62; CHECK-NEXT: xxspltw v2, vs0, 3 63; CHECK-NEXT: blr 64 65; CHECK-BE-LABEL: test4: 66; CHECK-BE: # %bb.0: # %entry 67; CHECK-BE-NEXT: lfiwzx f0, 0, r3 68; CHECK-BE-NEXT: xxsldwi vs0, f0, f0, 1 69; CHECK-BE-NEXT: xxspltw v2, vs0, 0 70; CHECK-BE-NEXT: blr 71entry: 72 %0 = load i32, i32* %in, align 4 73 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 74 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 75 ret <4 x i32> %splat.splat 76} 77 78define <4 x float> @test5(float* nocapture readonly %in) { 79; CHECK-LABEL: test5: 80; CHECK: # %bb.0: # %entry 81; CHECK-NEXT: lfiwzx f0, 0, r3 82; CHECK-NEXT: xxpermdi vs0, f0, f0, 2 83; CHECK-NEXT: xxspltw v2, vs0, 3 84; CHECK-NEXT: blr 85 86; CHECK-BE-LABEL: test5: 87; CHECK-BE: # %bb.0: # %entry 88; CHECK-BE-NEXT: lfiwzx f0, 0, r3 89; CHECK-BE-NEXT: xxsldwi vs0, f0, f0, 1 90; CHECK-BE-NEXT: xxspltw v2, vs0, 0 91; CHECK-BE-NEXT: blr 92entry: 93 %0 = load float, float* %in, align 4 94 %splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0 95 %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer 96 ret <4 x float> %splat.splat 97} 98 99define <4 x i32> @test6() { 100; CHECK-LABEL: test6: 101; CHECK: # %bb.0: # %entry 102; CHECK-NEXT: addis r3, r2, .LC0@toc@ha 103; CHECK-NEXT: ld r3, .LC0@toc@l(r3) 104; CHECK-NEXT: lfiwzx f0, 0, r3 105; CHECK-NEXT: xxpermdi vs0, f0, f0, 2 106; CHECK-NEXT: xxspltw v2, vs0, 3 107; CHECK-NEXT: blr 108 109; CHECK-BE-LABEL: test6: 110; CHECK-BE: # %bb.0: # %entry 111; CHECK-BE-NEXT: addis r3, r2, .LC0@toc@ha 112; CHECK-BE-NEXT: ld r3, .LC0@toc@l(r3) 113; CHECK-BE-NEXT: lfiwzx f0, 0, r3 114; CHECK-BE-NEXT: xxsldwi vs0, f0, f0, 1 115; CHECK-BE-NEXT: xxspltw v2, vs0, 0 116; CHECK-BE-NEXT: blr 117entry: 118 %0 = load i32, i32* @Globi, align 4 119 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 120 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 121 ret <4 x i32> %splat.splat 122} 123 124define <4 x float> @test7() { 125; CHECK-LABEL: test7: 126; CHECK: # %bb.0: # %entry 127; CHECK-NEXT: addis r3, r2, .LC1@toc@ha 128; CHECK-NEXT: ld r3, .LC1@toc@l(r3) 129; CHECK-NEXT: lfiwzx f0, 0, r3 130; CHECK-NEXT: xxpermdi vs0, f0, f0, 2 131; CHECK-NEXT: xxspltw v2, vs0, 3 132; CHECK-NEXT: blr 133 134; CHECK-BE-LABEL: test7: 135; CHECK-BE: # %bb.0: # %entry 136; CHECK-BE-NEXT: addis r3, r2, .LC1@toc@ha 137; CHECK-BE-NEXT: ld r3, .LC1@toc@l(r3) 138; CHECK-BE-NEXT: lfiwzx f0, 0, r3 139; CHECK-BE-NEXT: xxsldwi vs0, f0, f0, 1 140; CHECK-BE-NEXT: xxspltw v2, vs0, 0 141; CHECK-BE-NEXT: blr 142entry: 143 %0 = load float, float* @Globf, align 4 144 %splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0 145 %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer 146 ret <4 x float> %splat.splat 147} 148 149define <16 x i8> @test8() { 150; CHECK-LABEL: test8: 151; CHECK: # %bb.0: # %entry 152; CHECK-NEXT: xxlxor v2, v2, v2 153; CHECK-NEXT: blr 154 155; CHECK-BE-LABEL: test8: 156; CHECK-BE: # %bb.0: # %entry 157; CHECK-BE-NEXT: xxlxor v2, v2, v2 158; CHECK-BE-NEXT: blr 159entry: 160 ret <16 x i8> zeroinitializer 161} 162 163define <16 x i8> @test9() { 164; CHECK-LABEL: test9: 165; CHECK: # %bb.0: # %entry 166; CHECK-NEXT: xxspltib v2, 1 167; CHECK-NEXT: blr 168 169; CHECK-BE-LABEL: test9: 170; CHECK-BE: # %bb.0: # %entry 171; CHECK-BE-NEXT: xxspltib v2, 1 172; CHECK-BE-NEXT: blr 173entry: 174 ret <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 175} 176 177define <16 x i8> @test10() { 178; CHECK-LABEL: test10: 179; CHECK: # %bb.0: # %entry 180; CHECK-NEXT: xxspltib v2, 127 181; CHECK-NEXT: blr 182 183; CHECK-BE-LABEL: test10: 184; CHECK-BE: # %bb.0: # %entry 185; CHECK-BE-NEXT: xxspltib v2, 127 186; CHECK-BE-NEXT: blr 187entry: 188 ret <16 x i8> <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127> 189} 190 191define <16 x i8> @test11() { 192; CHECK-LABEL: test11: 193; CHECK: # %bb.0: # %entry 194; CHECK-NEXT: xxspltib v2, 128 195; CHECK-NEXT: blr 196 197; CHECK-BE-LABEL: test11: 198; CHECK-BE: # %bb.0: # %entry 199; CHECK-BE-NEXT: xxspltib v2, 128 200; CHECK-BE-NEXT: blr 201entry: 202 ret <16 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128> 203} 204 205define <16 x i8> @test12() { 206; CHECK-LABEL: test12: 207; CHECK: # %bb.0: # %entry 208; CHECK-NEXT: xxspltib v2, 255 209; CHECK-NEXT: blr 210 211; CHECK-BE-LABEL: test12: 212; CHECK-BE: # %bb.0: # %entry 213; CHECK-BE-NEXT: xxspltib v2, 255 214; CHECK-BE-NEXT: blr 215entry: 216 ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 217} 218 219define <16 x i8> @test13() { 220; CHECK-LABEL: test13: 221; CHECK: # %bb.0: # %entry 222; CHECK-NEXT: xxspltib v2, 129 223; CHECK-NEXT: blr 224 225; CHECK-BE-LABEL: test13: 226; CHECK-BE: # %bb.0: # %entry 227; CHECK-BE-NEXT: xxspltib v2, 129 228; CHECK-BE-NEXT: blr 229entry: 230 ret <16 x i8> <i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127> 231} 232 233define <16 x i8> @test13E127() { 234; CHECK-LABEL: test13E127: 235; CHECK: # %bb.0: # %entry 236; CHECK-NEXT: xxspltib v2, 200 237; CHECK-NEXT: blr 238 239; CHECK-BE-LABEL: test13E127: 240; CHECK-BE: # %bb.0: # %entry 241; CHECK-BE-NEXT: xxspltib v2, 200 242; CHECK-BE-NEXT: blr 243entry: 244 ret <16 x i8> <i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200> 245} 246 247define <4 x i32> @test14(<4 x i32> %a, i32* nocapture readonly %b) { 248; CHECK-LABEL: test14: 249; CHECK: # %bb.0: # %entry 250; CHECK-NEXT: lwz r3, 0(r5) 251; CHECK-NEXT: mtvsrws v2, r3 252; CHECK-NEXT: addi r3, r3, 5 253; CHECK-NEXT: stw r3, 0(r5) 254; CHECK-NEXT: blr 255 256; CHECK-BE-LABEL: test14: 257; CHECK-BE: # %bb.0: # %entry 258; CHECK-BE-NEXT: lwz r3, 0(r5) 259; CHECK-BE-NEXT: mtvsrws v2, r3 260; CHECK-BE-NEXT: addi r3, r3, 5 261; CHECK-BE-NEXT: stw r3, 0(r5) 262; CHECK-BE-NEXT: blr 263entry: 264 %0 = load i32, i32* %b, align 4 265 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 266 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 267 %1 = add i32 %0, 5 268 store i32 %1, i32* %b, align 4 269 ret <4 x i32> %splat.splat 270} 271