1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 3; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 4; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 6; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 7; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 8@glob = common local_unnamed_addr global i8 0, align 1 9 10define signext i32 @test_igesc(i8 signext %a, i8 signext %b) { 11; CHECK-LABEL: test_igesc: 12; CHECK: # %bb.0: # %entry 13; CHECK-NEXT: sub r3, r3, r4 14; CHECK-NEXT: rldicl r3, r3, 1, 63 15; CHECK-NEXT: xori r3, r3, 1 16; CHECK-NEXT: blr 17entry: 18 %cmp = icmp sge i8 %a, %b 19 %conv2 = zext i1 %cmp to i32 20 ret i32 %conv2 21} 22 23define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) { 24; CHECK-LABEL: test_igesc_sext: 25; CHECK: # %bb.0: # %entry 26; CHECK-NEXT: sub r3, r3, r4 27; CHECK-NEXT: rldicl r3, r3, 1, 63 28; CHECK-NEXT: addi r3, r3, -1 29; CHECK-NEXT: blr 30entry: 31 %cmp = icmp sge i8 %a, %b 32 %sub = sext i1 %cmp to i32 33 ret i32 %sub 34} 35 36define void @test_igesc_store(i8 signext %a, i8 signext %b) { 37; CHECK-LABEL: test_igesc_store: 38; CHECK: # %bb.0: # %entry 39; CHECK-NEXT: addis r5, r2, .LC0@toc@ha 40; CHECK-NEXT: sub r3, r3, r4 41; CHECK-NEXT: ld r4, .LC0@toc@l(r5) 42; CHECK-NEXT: rldicl r3, r3, 1, 63 43; CHECK-NEXT: xori r3, r3, 1 44; CHECK-NEXT: stb r3, 0(r4) 45; CHECK-NEXT: blr 46entry: 47 %cmp = icmp sge i8 %a, %b 48 %conv3 = zext i1 %cmp to i8 49 store i8 %conv3, i8* @glob, align 1 50 ret void 51} 52 53define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) { 54; CHECK-LABEL: test_igesc_sext_store: 55; CHECK: # %bb.0: # %entry 56; CHECK-NEXT: addis r5, r2, .LC0@toc@ha 57; CHECK-NEXT: sub r3, r3, r4 58; CHECK-NEXT: ld r4, .LC0@toc@l(r5) 59; CHECK-NEXT: rldicl r3, r3, 1, 63 60; CHECK-NEXT: addi r3, r3, -1 61; CHECK-NEXT: stb r3, 0(r4) 62; CHECK-NEXT: blr 63entry: 64 %cmp = icmp sge i8 %a, %b 65 %conv3 = sext i1 %cmp to i8 66 store i8 %conv3, i8* @glob, align 1 67 ret void 68} 69