1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 3; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 4; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 6; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 7; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 8 9@glob = common local_unnamed_addr global i16 0, align 2 10 11define signext i32 @test_ineus(i16 zeroext %a, i16 zeroext %b) { 12; CHECK-LABEL: test_ineus: 13; CHECK: # %bb.0: # %entry 14; CHECK-NEXT: xor r3, r3, r4 15; CHECK-NEXT: cntlzw r3, r3 16; CHECK-NEXT: srwi r3, r3, 5 17; CHECK-NEXT: xori r3, r3, 1 18; CHECK-NEXT: blr 19entry: 20 %cmp = icmp ne i16 %a, %b 21 %conv2 = zext i1 %cmp to i32 22 ret i32 %conv2 23} 24 25define signext i32 @test_ineus_sext(i16 zeroext %a, i16 zeroext %b) { 26; CHECK-LABEL: test_ineus_sext: 27; CHECK: # %bb.0: # %entry 28; CHECK-NEXT: xor r3, r3, r4 29; CHECK-NEXT: cntlzw r3, r3 30; CHECK-NEXT: srwi r3, r3, 5 31; CHECK-NEXT: xori r3, r3, 1 32; CHECK-NEXT: neg r3, r3 33; CHECK-NEXT: blr 34entry: 35 %cmp = icmp ne i16 %a, %b 36 %sub = sext i1 %cmp to i32 37 ret i32 %sub 38} 39 40define signext i32 @test_ineus_z(i16 zeroext %a) { 41; CHECK-LABEL: test_ineus_z: 42; CHECK: # %bb.0: # %entry 43; CHECK-NEXT: cntlzw r3, r3 44; CHECK-NEXT: srwi r3, r3, 5 45; CHECK-NEXT: xori r3, r3, 1 46; CHECK-NEXT: blr 47entry: 48 %cmp = icmp ne i16 %a, 0 49 %conv1 = zext i1 %cmp to i32 50 ret i32 %conv1 51} 52 53define signext i32 @test_ineus_sext_z(i16 zeroext %a) { 54; CHECK-LABEL: test_ineus_sext_z: 55; CHECK: # %bb.0: # %entry 56; CHECK-NEXT: cntlzw r3, r3 57; CHECK-NEXT: srwi r3, r3, 5 58; CHECK-NEXT: xori r3, r3, 1 59; CHECK-NEXT: neg r3, r3 60; CHECK-NEXT: blr 61entry: 62 %cmp = icmp ne i16 %a, 0 63 %sub = sext i1 %cmp to i32 64 ret i32 %sub 65} 66 67define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) { 68; CHECK-LABEL: test_ineus_store: 69; CHECK: # %bb.0: # %entry 70; CHECK-NEXT: addis r5, r2, .LC0@toc@ha 71; CHECK-NEXT: xor r3, r3, r4 72; CHECK-NEXT: cntlzw r3, r3 73; CHECK-NEXT: ld r4, .LC0@toc@l(r5) 74; CHECK-NEXT: srwi r3, r3, 5 75; CHECK-NEXT: xori r3, r3, 1 76; CHECK-NEXT: sth r3, 0(r4) 77; CHECK-NEXT: blr 78entry: 79 %cmp = icmp ne i16 %a, %b 80 %conv3 = zext i1 %cmp to i16 81 store i16 %conv3, i16* @glob, align 2 82 ret void 83} 84 85define void @test_ineus_sext_store(i16 zeroext %a, i16 zeroext %b) { 86; CHECK-LABEL: test_ineus_sext_store: 87; CHECK: # %bb.0: # %entry 88; CHECK-NEXT: xor r3, r3, r4 89; CHECK-NEXT: addis r5, r2, .LC0@toc@ha 90; CHECK-NEXT: cntlzw r3, r3 91; CHECK-NEXT: ld r4, .LC0@toc@l(r5) 92; CHECK-NEXT: srwi r3, r3, 5 93; CHECK-NEXT: xori r3, r3, 1 94; CHECK-NEXT: neg r3, r3 95; CHECK-NEXT: sth r3, 0(r4) 96; CHECK-NEXT: blr 97entry: 98 %cmp = icmp ne i16 %a, %b 99 %conv3 = sext i1 %cmp to i16 100 store i16 %conv3, i16* @glob, align 2 101 ret void 102} 103 104define void @test_ineus_z_store(i16 zeroext %a) { 105; CHECK-LABEL: test_ineus_z_store: 106; CHECK: # %bb.0: # %entry 107; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 108; CHECK-NEXT: cntlzw r3, r3 109; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 110; CHECK-NEXT: srwi r3, r3, 5 111; CHECK-NEXT: xori r3, r3, 1 112; CHECK-NEXT: sth r3, 0(r4) 113; CHECK-NEXT: blr 114entry: 115 %cmp = icmp ne i16 %a, 0 116 %conv2 = zext i1 %cmp to i16 117 store i16 %conv2, i16* @glob, align 2 118 ret void 119} 120 121define void @test_ineus_sext_z_store(i16 zeroext %a) { 122; CHECK-LABEL: test_ineus_sext_z_store: 123; CHECK: # %bb.0: # %entry 124; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 125; CHECK-NEXT: cntlzw r3, r3 126; CHECK-NEXT: srwi r3, r3, 5 127; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 128; CHECK-NEXT: xori r3, r3, 1 129; CHECK-NEXT: neg r3, r3 130; CHECK-NEXT: sth r3, 0(r4) 131; CHECK-NEXT: blr 132entry: 133 %cmp = icmp ne i16 %a, 0 134 %conv2 = sext i1 %cmp to i16 135 store i16 %conv2, i16* @glob, align 2 136 ret void 137} 138